diff --git a/index.html b/index.html
index b96296e..9f81742 100644
--- a/index.html
+++ b/index.html
@@ -197,22 +197,22 @@
 <div id="content" class="content">
 <h1 class="title">ocpu</h1>
 
-<div id="outline-container-orgfb92850" class="outline-2">
-<h2 id="orgfb92850">GRU ocpu - yet another cpu design</h2>
-<div class="outline-text-2" id="text-orgfb92850">
+<div id="outline-container-org59ce0e8" class="outline-2">
+<h2 id="org59ce0e8">GRU ocpu - yet another cpu design</h2>
+<div class="outline-text-2" id="text-org59ce0e8">
 </div>
-<div id="outline-container-org3484607" class="outline-3">
-<h3 id="org3484607">Features</h3>
-<div class="outline-text-3" id="text-org3484607">
+<div id="outline-container-orgf798eeb" class="outline-3">
+<h3 id="orgf798eeb">Features</h3>
+<div class="outline-text-3" id="text-orgf798eeb">
 <ul class="org-ul">
 <li>little endian</li>
 <li>16-bit</li>
 </ul>
 </div>
 </div>
-<div id="outline-container-orge29449e" class="outline-3">
-<h3 id="orge29449e">Registers</h3>
-<div class="outline-text-3" id="text-orge29449e">
+<div id="outline-container-orgc029f05" class="outline-3">
+<h3 id="orgc029f05">Registers</h3>
+<div class="outline-text-3" id="text-orgc029f05">
 <table border="2" cellspacing="0" cellpadding="6" rules="groups" frame="hsides">
 
 
@@ -408,9 +408,9 @@
 </div>
 </div>
 
-<div id="outline-container-orga7d5604" class="outline-3">
-<h3 id="orga7d5604">Instuctions</h3>
-<div class="outline-text-3" id="text-orga7d5604">
+<div id="outline-container-orged9566e" class="outline-3">
+<h3 id="orged9566e">Instuctions</h3>
+<div class="outline-text-3" id="text-orged9566e">
 <table border="2" cellspacing="0" cellpadding="6" rules="groups" frame="hsides">
 
 
@@ -546,79 +546,86 @@
 </tbody>
 <tbody>
 <tr>
-<td class="org-left">AND reg, imm16</td>
+<td class="org-left">NOT reg</td>
 <td class="org-right">0x20</td>
+<td class="org-left">Logical NOT</td>
+</tr>
+</tbody>
+<tbody>
+<tr>
+<td class="org-left">AND reg, imm16</td>
+<td class="org-right">0x21</td>
 <td class="org-left">Logical AND</td>
 </tr>
 
 <tr>
 <td class="org-left">AND reg, reg</td>
-<td class="org-right">0xC0</td>
-<td class="org-left">&#xa0;</td>
-</tr>
-</tbody>
-<tbody>
-<tr>
-<td class="org-left">OR reg, imm16</td>
-<td class="org-right">0x21</td>
-<td class="org-left">Logical OR</td>
-</tr>
-
-<tr>
-<td class="org-left">OR reg, reg</td>
 <td class="org-right">0xC1</td>
 <td class="org-left">&#xa0;</td>
 </tr>
 </tbody>
 <tbody>
 <tr>
-<td class="org-left">NOR reg, imm16</td>
+<td class="org-left">OR reg, imm16</td>
 <td class="org-right">0x22</td>
-<td class="org-left">Logical NOR</td>
+<td class="org-left">Logical OR</td>
 </tr>
 
 <tr>
-<td class="org-left">NOR reg, reg</td>
+<td class="org-left">OR reg, reg</td>
 <td class="org-right">0xC2</td>
 <td class="org-left">&#xa0;</td>
 </tr>
 </tbody>
 <tbody>
 <tr>
-<td class="org-left">XOR reg, imm16</td>
+<td class="org-left">NOR reg, imm16</td>
 <td class="org-right">0x23</td>
-<td class="org-left">Logical XOR</td>
+<td class="org-left">Logical NOR</td>
 </tr>
 
 <tr>
-<td class="org-left">XOR reg, reg</td>
+<td class="org-left">NOR reg, reg</td>
 <td class="org-right">0xC3</td>
 <td class="org-left">&#xa0;</td>
 </tr>
 </tbody>
 <tbody>
 <tr>
-<td class="org-left">NAND reg, imm16</td>
+<td class="org-left">XOR reg, imm16</td>
 <td class="org-right">0x24</td>
-<td class="org-left">Logical NAND</td>
+<td class="org-left">Logical XOR</td>
 </tr>
 
 <tr>
-<td class="org-left">NAND reg, reg</td>
+<td class="org-left">XOR reg, reg</td>
 <td class="org-right">0xC4</td>
 <td class="org-left">&#xa0;</td>
 </tr>
 </tbody>
 <tbody>
 <tr>
-<td class="org-left">CMP reg, imm16, imm16</td>
+<td class="org-left">NAND reg, imm16</td>
 <td class="org-right">0x25</td>
+<td class="org-left">Logical NAND</td>
+</tr>
+
+<tr>
+<td class="org-left">NAND reg, reg</td>
+<td class="org-right">0xC5</td>
+<td class="org-left">&#xa0;</td>
+</tr>
+</tbody>
+<tbody>
+<tr>
+<td class="org-left">CMP reg, imm16, imm16</td>
+<td class="org-right">0x26</td>
 <td class="org-left">Compare</td>
 </tr>
 
 <tr>
 <td class="org-left">CMP reg, reg, imm16</td>
-<td class="org-right">0xC5</td>
+<td class="org-right">0xC6</td>
 <td class="org-left">&#xa0;</td>
 </tr>
 
diff --git a/ocpu.org b/ocpu.org
index 14516c2..13c99a6 100644
--- a/ocpu.org
+++ b/ocpu.org
@@ -92,23 +92,25 @@
    |-----------------------+--------+-------------------------------------------|
    | DEC reg               |   0x16 | Decrement                                 |
    |-----------------------+--------+-------------------------------------------|
-   | AND reg, imm16        |   0x20 | Logical AND                               |
-   | AND reg, reg          |   0xC0 |                                           |
+   | NOT reg               |   0x20 | Logical NOT                               |
    |-----------------------+--------+-------------------------------------------|
-   | OR reg, imm16         |   0x21 | Logical OR                                |
-   | OR reg, reg           |   0xC1 |                                           |
+   | AND reg, imm16        |   0x21 | Logical AND                               |
+   | AND reg, reg          |   0xC1 |                                           |
    |-----------------------+--------+-------------------------------------------|
-   | NOR reg, imm16        |   0x22 | Logical NOR                               |
-   | NOR reg, reg          |   0xC2 |                                           |
+   | OR reg, imm16         |   0x22 | Logical OR                                |
+   | OR reg, reg           |   0xC2 |                                           |
    |-----------------------+--------+-------------------------------------------|
-   | XOR reg, imm16        |   0x23 | Logical XOR                               |
-   | XOR reg, reg          |   0xC3 |                                           |
+   | NOR reg, imm16        |   0x23 | Logical NOR                               |
+   | NOR reg, reg          |   0xC3 |                                           |
    |-----------------------+--------+-------------------------------------------|
-   | NAND reg, imm16       |   0x24 | Logical NAND                              |
-   | NAND reg, reg         |   0xC4 |                                           |
+   | XOR reg, imm16        |   0x24 | Logical XOR                               |
+   | XOR reg, reg          |   0xC4 |                                           |
    |-----------------------+--------+-------------------------------------------|
-   | CMP reg, imm16, imm16 |   0x25 | Compare                                   |
-   | CMP reg, reg, imm16   |   0xC5 |                                           |
+   | NAND reg, imm16       |   0x25 | Logical NAND                              |
+   | NAND reg, reg         |   0xC5 |                                           |
+   |-----------------------+--------+-------------------------------------------|
+   | CMP reg, imm16, imm16 |   0x26 | Compare                                   |
+   | CMP reg, reg, imm16   |   0xC6 |                                           |
    | CMP reg, reg, reg     |        |                                           |
    |-----------------------+--------+-------------------------------------------|
    | PUSH imm16            |   0x30 | Push to stack                             |