221 lines
6.3 KiB
C
221 lines
6.3 KiB
C
#define IRQ0 32
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#define IRQ1 33
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#define IRQ2 34
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#define IRQ3 35
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#define IRQ4 36
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#define IRQ5 37
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#define IRQ6 38
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#define IRQ7 39
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#define IRQ8 40
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#define IRQ9 41
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#define IRQ10 42
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#define IRQ11 43
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#define IRQ12 44
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#define IRQ13 45
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#define IRQ14 46
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#define IRQ15 47
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//#include "asm_helper.h"
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struct idt_entry_struct
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{
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uint16_t base_lo; // The lower 16 bits of the ISR's address
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uint16_t sel; // The GDT segment selector that the CPU will load into CS before calling the ISR
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uint8_t always0; // Always set to zero
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uint8_t flags; // Type and attributes
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uint16_t base_hi; // The higher 16 bits of the ISR's address
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} __attribute__((packed));
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typedef struct idt_entry_struct idt_entry_t;
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struct idt_ptr_struct {
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uint16_t limit;
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uint32_t base;
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} __attribute__((packed));
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typedef struct idt_ptr_struct idt_ptr_t;
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idt_entry_t idt_entries[256];
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idt_ptr_t idt_ptr;
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typedef struct registers
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{
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uint32_t ds; // Data segment selector
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uint32_t edi, esi, ebp, esp, ebx, edx, ecx, eax; // Pushed by pusha.
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uint32_t int_no, err_code; // Interrupt number and error code (if applicable)
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uint32_t eip, cs, eflags, useresp, ss; // Pushed by the processor automatically.
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} registers_t;
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typedef void (*isr_t)(registers_t);
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isr_t interrupt_handlers[256];
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void idt_set_gate(uint8_t num, uint32_t base, uint16_t sel, uint8_t flags) {
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idt_entries[num].base_lo = base & 0xFFFF;
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idt_entries[num].base_hi = (base >> 16) & 0xFFFF;
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idt_entries[num].sel = sel;
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idt_entries[num].always0 = 0;
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idt_entries[num].flags = flags;
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}
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void idt_init(void);
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void idt_init() {
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idt_ptr.limit = sizeof(idt_entry_t) * 256 - 1;
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idt_ptr.base = (uint32_t)idt_entries;
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memset(idt_entries, 0, sizeof(idt_entry_t)*256);
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extern isr_t isr0;
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extern isr_t isr1;
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extern isr_t isr2;
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extern isr_t isr3;
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extern isr_t isr4;
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extern isr_t isr5;
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extern isr_t isr6;
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extern isr_t isr7;
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extern isr_t isr8;
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extern isr_t isr9;
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extern isr_t isr10;
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extern isr_t isr11;
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extern isr_t isr12;
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extern isr_t isr13;
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extern isr_t isr14;
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extern isr_t isr15;
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extern isr_t isr16;
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extern isr_t isr17;
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extern isr_t isr18;
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extern isr_t isr19;
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extern isr_t isr20;
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extern isr_t isr21;
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extern isr_t isr22;
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extern isr_t isr23;
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extern isr_t isr24;
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extern isr_t isr25;
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extern isr_t isr26;
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extern isr_t isr27;
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extern isr_t isr28;
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extern isr_t isr29;
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extern isr_t isr30;
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extern isr_t isr31;
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extern isr_t irq0;
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extern isr_t irq1;
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extern isr_t irq2;
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extern isr_t irq3;
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extern isr_t irq4;
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extern isr_t irq5;
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extern isr_t irq6;
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extern isr_t irq7;
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extern isr_t irq8;
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extern isr_t irq9;
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extern isr_t irq10;
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extern isr_t irq11;
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extern isr_t irq12;
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extern isr_t irq13;
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extern isr_t irq14;
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extern isr_t irq15;
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idt_set_gate(0, (uint32_t)&isr0, 0x08, 0x8E);
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idt_set_gate(1, (uint32_t)&isr1, 0x08, 0x8E);
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idt_set_gate(2, (uint32_t)&isr2, 0x08, 0x8E);
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idt_set_gate(3, (uint32_t)&isr3, 0x08, 0x8E);
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idt_set_gate(4, (uint32_t)&isr4, 0x08, 0x8E);
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idt_set_gate(5, (uint32_t)&isr5, 0x08, 0x8E);
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idt_set_gate(6, (uint32_t)&isr6, 0x08, 0x8E);
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idt_set_gate(7, (uint32_t)&isr7, 0x08, 0x8E);
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idt_set_gate(8, (uint32_t)&isr8, 0x08, 0x8E);
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idt_set_gate(9, (uint32_t)&isr9, 0x08, 0x8E);
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idt_set_gate(10, (uint32_t)&isr10, 0x08, 0x8E);
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idt_set_gate(11, (uint32_t)&isr11, 0x08, 0x8E);
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idt_set_gate(12, (uint32_t)&isr12, 0x08, 0x8E);
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idt_set_gate(13, (uint32_t)&isr13, 0x08, 0x8E);
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idt_set_gate(14, (uint32_t)&isr14, 0x08, 0x8E);
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idt_set_gate(15, (uint32_t)&isr15, 0x08, 0x8E);
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idt_set_gate(16, (uint32_t)&isr16, 0x08, 0x8E);
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idt_set_gate(17, (uint32_t)&isr17, 0x08, 0x8E);
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idt_set_gate(18, (uint32_t)&isr18, 0x08, 0x8E);
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idt_set_gate(19, (uint32_t)&isr19, 0x08, 0x8E);
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idt_set_gate(20, (uint32_t)&isr20, 0x08, 0x8E);
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idt_set_gate(21, (uint32_t)&isr21, 0x08, 0x8E);
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idt_set_gate(22, (uint32_t)&isr22, 0x08, 0x8E);
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idt_set_gate(23, (uint32_t)&isr23, 0x08, 0x8E);
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idt_set_gate(24, (uint32_t)&isr24, 0x08, 0x8E);
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idt_set_gate(25, (uint32_t)&isr25, 0x08, 0x8E);
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idt_set_gate(26, (uint32_t)&isr26, 0x08, 0x8E);
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idt_set_gate(27, (uint32_t)&isr27, 0x08, 0x8E);
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idt_set_gate(28, (uint32_t)&isr28, 0x08, 0x8E);
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idt_set_gate(29, (uint32_t)&isr29, 0x08, 0x8E);
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idt_set_gate(30, (uint32_t)&isr30, 0x08, 0x8E);
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idt_set_gate(31, (uint32_t)&isr31, 0x08, 0x8E);
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extern void idt_flush(uint32_t);
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idt_flush((uint32_t)&idt_ptr);
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// Remap the irq table.
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outb(0x20, 0x11);
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outb(0xA0, 0x11);
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outb(0x21, 0x20);
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outb(0xA1, 0x28);
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outb(0x21, 0x04);
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outb(0xA1, 0x02);
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outb(0x21, 0x01);
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outb(0xA1, 0x01);
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outb(0x21, 0x0);
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outb(0xA1, 0x0);
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idt_set_gate(32, (uint32_t)&irq0, 0x08, 0x8E);
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idt_set_gate(33, (uint32_t)&irq1, 0x08, 0x8E);
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idt_set_gate(34, (uint32_t)&irq2, 0x08, 0x8E);
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idt_set_gate(35, (uint32_t)&irq3, 0x08, 0x8E);
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idt_set_gate(36, (uint32_t)&irq4, 0x08, 0x8E);
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idt_set_gate(37, (uint32_t)&irq5, 0x08, 0x8E);
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idt_set_gate(38, (uint32_t)&irq6, 0x08, 0x8E);
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idt_set_gate(39, (uint32_t)&irq7, 0x08, 0x8E);
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idt_set_gate(40, (uint32_t)&irq8, 0x08, 0x8E);
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idt_set_gate(41, (uint32_t)&irq9, 0x08, 0x8E);
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idt_set_gate(42, (uint32_t)&irq10, 0x08, 0x8E);
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idt_set_gate(43, (uint32_t)&irq11, 0x08, 0x8E);
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idt_set_gate(44, (uint32_t)&irq12, 0x08, 0x8E);
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idt_set_gate(45, (uint32_t)&irq13, 0x08, 0x8E);
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idt_set_gate(46, (uint32_t)&irq14, 0x08, 0x8E);
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idt_set_gate(47, (uint32_t)&irq15, 0x08, 0x8E);
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}
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void isr_handler(registers_t regs)
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{
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if (interrupt_handlers[regs.int_no] != 0)
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{
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isr_t handler = interrupt_handlers[regs.int_no];
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handler(regs);
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} else {
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//printf("Unhandled interrupt: %c\n", regs.int_no); // FIXME: Fix from %s to %X
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//serial_printf("Unhandled interrupt: %c\n", regs.int_no); // FIXME: Fix from %s to %X
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}
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}
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void irq_handler(registers_t regs)
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{
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// Send an EOI (end of interrupt) signal to the PICs.
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// If this interrupt involved the slave.
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if (regs.int_no >= 40)
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{
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// Send reset signal to slave.
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outb(0xA0, 0x20);
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}
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// Send reset signal to master. (As well as slave, if necessary).
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outb(0x20, 0x20);
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if (interrupt_handlers[regs.int_no] != 0)
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{
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isr_t handler = interrupt_handlers[regs.int_no];
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handler(regs);
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} else {
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//serial_printf("Unhandled IRQ interrupt: %c\n", regs.int_no); // FIXME: Fix from %s to %X
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}
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}
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void register_interrupt_handler(uint8_t n, isr_t handler)
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{
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interrupt_handlers[n] = handler;
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}
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