https://github.com/akkartik/mu/blob/master/subx/031check_operands.cc

      1 //: Since we're tagging operands with their types, let's start checking these
      2 //: operand types for each instruction.
      3
      4 void test_check_missing_imm8_operand() {
      5   Hide_errors = true;
      6   run(
      7       "== 0x1\n"  // code segment
      8       "cd\n"  // interrupt ??
      9   );
     10   CHECK_TRACE_CONTENTS(
     11       "error: 'cd' (software interrupt): missing imm8 operand\n"
     12   );
     13 }
     14
     15 :(before "Pack Operands(segment code)")
     16 check_operands(code);
     17 if (trace_contains_errors()) return;
     18
     19 :(code)
     20 void check_operands(const segment& code) {
     21   trace(3, "transform") << "-- check operands" << end();
     22   for (int i = 0;  i < SIZE(code.lines);  ++i) {
     23     check_operands(code.lines.at(i));
     24     if (trace_contains_errors()) return;  // stop at the first mal-formed instruction
     25   }
     26 }
     27
     28 void check_operands(const line& inst) {
     29   word op = preprocess_op(inst.words.at(0));
     30   if (op.data == "0f") {
     31     check_operands_0f(inst);
     32     return;
     33   }
     34   if (op.data == "f3") {
     35     check_operands_f3(inst);
     36     return;
     37   }
     38   check_operands(inst, op);
     39 }
     40
     41 word preprocess_op(word/*copy*/ op) {
     42   op.data = tolower(op.data.c_str());
     43   // opcodes can't be negative
     44   if (starts_with(op.data, "0x"))
     45     op.data = op.data.substr(2);
     46   if (SIZE(op.data) == 1)
     47     op.data = string("0")+op.data;
     48   return op;
     49 }
     50
     51 void test_preprocess_op() {
     52   word w1;  w1.data = "0xf";
     53   word w2;  w2.data = "0f";
     54   CHECK_EQ(preprocess_op(w1).data, preprocess_op(w2).data);
     55 }
     56
     57 //: To check the operands for an opcode, we'll track the permitted operands
     58 //: for each supported opcode in a bitvector. That way we can often compute the
     59 //: 'received' operand bitvector for each instruction's operands and compare
     60 //: it with the 'expected' bitvector.
     61 //:
     62 //: The 'expected' and 'received' bitvectors can be different; the MODRM bit
     63 //: in the 'expected' bitvector maps to multiple 'received' operand types in
     64 //: an instruction. We deal in expected bitvectors throughout.
     65
     66 :(before "End Types")
     67 enum expected_operand_type {
     68   // start from the least significant bit
     69   MODRM,  // more complex, may also involve disp8 or disp32
     70   SUBOP,
     71   DISP8,
     72   DISP16,
     73   DISP32,
     74   IMM8,
     75   IMM32,
     76   NUM_OPERAND_TYPES
     77 };
     78 :(before "End Globals")
     79 vector<string> Operand_type_name;
     80 map<string, expected_operand_type> Operand_type;
     81 :(before "End One-time Setup")
     82 init_op_types();
     83 :(code)
     84 void init_op_types() {
     85   assert(NUM_OPERAND_TYPES <= /*bits in a uint8_t*/8);
     86   Operand_type_name.resize(NUM_OPERAND_TYPES);
     87   #define DEF(type) Operand_type_name.at(type) = tolower(#type), put(Operand_type, tolower(#type), type);
     88   DEF(MODRM);
     89   DEF(SUBOP);
     90   DEF(DISP8);
     91   DEF(DISP16);
     92   DEF(DISP32);
     93   DEF(IMM8);
     94   DEF(IMM32);
     95   #undef DEF
     96 }
     97
     98 :(before "End Globals")
     99 map</*op*/string, /*bitvector*/uint8_t> Permitted_operands;
    100 const uint8_t INVALID_OPERANDS = 0xff;  // no instruction uses all the operand types
    101 :(before "End One-time Setup")
    102 init_permitted_operands();
    103 :(code)
    104 void init_permitted_operands() {
    105   //// Class A: just op, no operands
    106   // halt
    107   put(Permitted_operands, "f4", 0x00);
    108   // inc
    109   put(Permitted_operands, "40", 0x00);
    110   put(Permitted_operands, "41", 0x00);
    111   put(Permitted_operands, "42", 0x00);
    112   put(Permitted_operands, "43", 0x00);
    113   put(Permitted_operands, "44", 0x00);
    114   put(Permitted_operands, "45", 0x00);
    115   put(Permitted_operands, "46", 0x00);
    116   put(Permitted_operands, "47", 0x00);
    117   // dec
    118   put(Permitted_operands, "48", 0x00);
    119   put(Permitted_operands, "49", 0x00);
    120   put(Permitted_operands, "4a", 0x00);
    121   put(Permitted_operands, "4b", 0x00);
    122   put(Permitted_operands, "4c", 0x00);
    123   put(Permitted_operands, "4d", 0x00);
    124   put(Permitted_operands, "4e", 0x00);
    125   put(Permitted_operands, "4f", 0x00);
    126   // push
    127   put(Permitted_operands, "50", 0x00);
    128   put(Permitted_operands, "51", 0x00);
    129   put(Permitted_operands, "52", 0x00);
    130   put(Permitted_operands, "53", 0x00);
    131   put(Permitted_operands, "54", 0x00);
    132   put(Permitted_operands, "55", 0x00);
    133   put(Permitted_operands, "56", 0x00);
    134   put(Permitted_operands, "57", 0x00);
    135   // pop
    136   put(Permitted_operands, "58", 0x00);
    137   put(Permitted_operands, "59", 0x00);
    138   put(Permitted_operands, "5a", 0x00);
    139   put(Permitted_operands, "5b", 0x00);
    140   put(Permitted_operands, "5c", 0x00);
    141   put(Permitted_operands, "5d", 0x00);
    142   put(Permitted_operands, "5e", 0x00);
    143   put(Permitted_operands, "5f", 0x00);
    144   // return
    145   put(Permitted_operands, "c3", 0x00);
    146
    147   //// Class B: just op and disp8
    148   //  imm32 imm8  disp32 |disp16  disp8 subop modrm
    149   //  0     0     0      |0       1     0     0
    150
    151   // jump
    152   put(Permitted_operands, "eb", 0x04);
    153   put(Permitted_operands, "74", 0x04);
    154   put(Permitted_operands, "75", 0x04);
    155   put(Permitted_operands, "7c", 0x04);
    156   put(Permitted_operands, "7d", 0x04);
    157   put(Permitted_operands, "7e", 0x04);
    158   put(Permitted_operands, "7f", 0x04);
    159
    160   //// Class D: just op and disp32
    161   //  imm32 imm8  disp32 |disp16  disp8 subop modrm
    162   //  0     0     1      |0       0     0     0
    163   put(Permitted_operands, "e8", 0x10);  // call
    164   put(Permitted_operands, "e9", 0x10);  // jump
    165
    166   //// Class E: just op and imm8
    167   //  imm32 imm8  disp32 |disp16  disp8 subop modrm
    168   //  0     1     0      |0       0     0     0
    169   put(Permitted_operands, "cd", 0x20);  // software interrupt
    170
    171   //// Class F: just op and imm32
    172   //  imm32 imm8  disp32 |disp16  disp8 subop modrm
    173   //  1     0     0      |0       0     0     0
    174   put(Permitted_operands, "05", 0x40);  // add
    175   put(Permitted_operands, "2d", 0x40);  // subtract
    176   put(Permitted_operands, "25", 0x40);  // and
    177   put(Permitted_operands, "0d", 0x40);  // or
    178   put(Permitted_operands, "35", 0x40);  // xor
    179   put(Permitted_operands, "3d", 0x40);  // compare
    180   put(Permitted_operands, "68", 0x40);  // push
    181   // copy
    182   put(Permitted_operands, "b8", 0x40);
    183   put(Permitted_operands, "b9", 0x40);
    184   put(Permitted_operands, "ba", 0x40);
    185   put(Permitted_operands, "bb", 0x40);
    186   put(Permitted_operands, "bc", 0x40);
    187   put(Permitted_operands, "bd", 0x40);
    188   put(Permitted_operands, "be", 0x40);
    189   put(Permitted_operands, "bf", 0x40);
    190
    191   //// Class M: using ModR/M byte
    192   //  imm32 imm8  disp32 |disp16  disp8 subop modrm
    193   //  0     0     0      |0       0     0     1
    194
    195   // add
    196   put(Permitted_operands, "01", 0x01);
    197   put(Permitted_operands, "03", 0x01);
    198   // subtract
    199   put(Permitted_operands, "29", 0x01);
    200   put(Permitted_operands, "2b", 0x01);
    201   // and
    202   put(Permitted_operands, "21", 0x01);
    203   put(Permitted_operands, "23", 0x01);
    204   // or
    205   put(Permitted_operands, "09", 0x01);
    206   put(Permitted_operands, "0b", 0x01);
    207   // xor
    208   put(Permitted_operands, "31", 0x01);
    209   put(Permitted_operands, "33", 0x01);
    210   // compare
    211   put(Permitted_operands, "39", 0x01);
    212   put(Permitted_operands, "3b", 0x01);
    213   // copy
    214   put(Permitted_operands, "88", 0x01);
    215   put(Permitted_operands, "89", 0x01);
    216   put(Permitted_operands, "8a", 0x01);
    217   put(Permitted_operands, "8b", 0x01);
    218   // swap
    219   put(Permitted_operands, "87", 0x01);
    220   // copy address (lea)
    221   put(Permitted_operands, "8d", 0x01);
    222   // pop
    223   put(Permitted_operands, "8f", 0x01);
    224
    225   //// Class N: op, ModR/M and subop (not r32)
    226   //  imm32 imm8  disp32 |disp16  disp8 subop modrm
    227   //  0     0     0      |0       0     1     1
    228   put(Permitted_operands, "d3", 0x03);  // shift
    229   put(Permitted_operands, "f7", 0x03);  // test/not/mul/div
    230   put(Permitted_operands, "ff", 0x03);  // jump/push/call
    231
    232   //// Class O: op, ModR/M, subop (not r32) and imm8
    233   //  imm32 imm8  disp32 |disp16  disp8 subop modrm
    234   //  0     1     0      |0       0     1     1
    235   put(Permitted_operands, "c1", 0x23);  // combine
    236   put(Permitted_operands, "c6", 0x23);  // copy
    237
    238   //// Class P: op, ModR/M, subop (not r32) and imm32
    239   //  imm32 imm8  disp32 |disp16  disp8 subop modrm
    240   //  1     0     0      |0       0     1     1
    241   put(Permitted_operands, "81", 0x43);  // combine
    242   put(Permitted_operands, "c7", 0x43);  // copy
    243
    244   // End Init Permitted Operands
    245 }
    246
    247 #define HAS(bitvector, bit)  ((bitvector) & (1 << (bit)))
    248 #define SET(bitvector, bit)  ((bitvector) | (1 << (bit)))
    249 #define CLEAR(bitvector, bit)  ((bitvector) & (~(1 << (bit))))
    250
    251 void check_operands(const line& inst, const word& op) {
    252   if (!is_hex_byte(op)) return;
    253   uint8_t expected_bitvector = get(Permitted_operands, op.data);
    254   if (HAS(expected_bitvector, MODRM)) {
    255     check_operands_modrm(inst, op);
    256     compare_bitvector_modrm(inst, expected_bitvector, op);
    257   }
    258   else {
    259     compare_bitvector(inst, expected_bitvector, op);
    260   }
    261 }
    262
    263 //: Many instructions can be checked just by comparing bitvectors.
    264
    265 void compare_bitvector(const line& inst, uint8_t expected, const word& op) {
    266   if (all_hex_bytes(inst) && has_operands(inst)) return;  // deliberately programming in raw hex; we'll raise a warning elsewhere
    267   uint8_t bitvector = compute_expected_operand_bitvector(inst);
    268   if (trace_contains_errors()) return;  // duplicate operand type
    269   if (bitvector == expected) return;  // all good with this instruction
    270   for (int i = 0;  i < NUM_OPERAND_TYPES;  ++i, bitvector >>= 1, expected >>= 1) {
    271 //?     cerr << "comparing " << HEXBYTE << NUM(bitvector) << " with " << NUM(expected) << '\n';
    272     if ((bitvector & 0x1) == (expected & 0x1)) continue;  // all good with this operand
    273     const string& optype = Operand_type_name.at(i);
    274     if ((bitvector & 0x1) > (expected & 0x1))
    275       raise << "'" << to_string(inst) << "'" << maybe_name(op) << ": unexpected " << optype << " operand\n" << end();
    276     else
    277       raise << "'" << to_string(inst) << "'" << maybe_name(op) << ": missing " << optype << " operand\n" << end();
    278     // continue giving all errors for a single instruction
    279   }
    280   // ignore settings in any unused bits
    281 }
    282
    283 string maybe_name(const word& op) {
    284   if (!is_hex_byte(op)) return "";
    285   if (!contains_key(Name, op.data)) return "";
    286   // strip stuff in parens from the name
    287   const string& s = get(Name, op.data);
    288   return " ("+s.substr(0, s.find(" ("))+')';
    289 }
    290
    291 uint32_t compute_expected_operand_bitvector(const line& inst) {
    292   set<string> operands_found;
    293   uint32_t bitvector = 0;
    294   for (int i = /*skip op*/1;  i < SIZE(inst.words);  ++i) {
    295     bitvector = bitvector | expected_bit_for_received_operand(inst.words.at(i), operands_found, inst);
    296     if (trace_contains_errors()) return INVALID_OPERANDS;  // duplicate operand type
    297   }
    298   return bitvector;
    299 }
    300
    301 bool has_operands(const line& inst) {
    302   return SIZE(inst.words) > first_operand(inst);
    303 }
    304
    305 int first_operand(const line& inst) {
    306   if (inst.words.at(0).data == "0f") return 2;
    307   if (inst.words.at(0).data == "f2" || inst.words.at(0).data == "f3") {
    308     if (inst.words.at(1).data == "0f")
    309       return 3;
    310     else
    311       return 2;
    312   }
    313   return 1;
    314 }
    315
    316 // Scan the metadata of 'w' and return the expected bit corresponding to any operand type.
    317 // Also raise an error if metadata contains multiple operand types.
    318 uint32_t expected_bit_for_received_operand(const word& w, set<string>& instruction_operands, const line& inst) {
    319   uint32_t bv = 0;
    320   bool found = false;
    321   for (int i = 0;  i < SIZE(w.metadata);  ++i) {
    322     string/*copy*/ curr = w.metadata.at(i);
    323     string expected_metadata = curr;
    324     if (curr == "mod" || curr == "rm32" || curr == "r32" || curr == "scale" || curr == "index" || curr == "base")
    325       expected_metadata = "modrm";
    326     else if (!contains_key(Operand_type, curr)) continue;  // ignore unrecognized metadata
    327     if (found) {
    328       raise << "'" << w.original << "' has conflicting operand types; it should have only one\n" << end();
    329       return INVALID_OPERANDS;
    330     }
    331     if (instruction_operands.find(curr) != instruction_operands.end()) {
    332       raise << "'" << to_string(inst) << "': duplicate " << curr << " operand\n" << end();
    333       return INVALID_OPERANDS;
    334     }
    335     instruction_operands.insert(curr);
    336     bv = (1 << get(Operand_type, expected_metadata));
    337     found = true;
    338   }
    339   return bv;
    340 }
    341
    342 void test_conflicting_operand_type() {
    343   Hide_errors = true;
    344   run(
    345       "== 0x1\n"  // code segment
    346       "cd/software-interrupt 80/imm8/imm32\n"
    347   );
    348   CHECK_TRACE_CONTENTS(
    349       "error: '80/imm8/imm32' has conflicting operand types; it should have only one\n"
    350   );
    351 }
    352
    353 //: Instructions computing effective addresses have more complex rules, so
    354 //: we'll hard-code a common set of instruction-decoding rules.
    355
    356 void test_check_missing_mod_operand() {
    357   Hide_errors = true;
    358   run(
    359       "== 0x1\n"  // code segment
    360       "81 0/add/subop       3/rm32/ebx 1/imm32\n"
    361   );
    362   CHECK_TRACE_CONTENTS(
    363       "error: '81 0/add/subop 3/rm32/ebx 1/imm32' (combine rm32 with imm32 based on subop): missing mod operand\n"
    364   );
    365 }
    366
    367 void check_operands_modrm(const line& inst, const word& op) {
    368   if (all_hex_bytes(inst)) return;  // deliberately programming in raw hex; we'll raise a warning elsewhere
    369   check_operand_metadata_present(inst, "mod", op);
    370   check_operand_metadata_present(inst, "rm32", op);
    371   // no check for r32; some instructions don't use it; just assume it's 0 if missing
    372   if (op.data == "81" || op.data == "8f" || op.data == "ff") {  // keep sync'd with 'help subop'
    373     check_operand_metadata_present(inst, "subop", op);
    374     check_operand_metadata_absent(inst, "r32", op, "should be replaced by subop");
    375   }
    376   if (trace_contains_errors()) return;
    377   if (metadata(inst, "rm32").data != "4") return;
    378   // SIB byte checks
    379   uint8_t mod = hex_byte(metadata(inst, "mod").data);
    380   if (mod != /*direct*/3) {
    381     check_operand_metadata_present(inst, "base", op);
    382     check_operand_metadata_present(inst, "index", op);  // otherwise why go to SIB?
    383   }
    384   else {
    385     check_operand_metadata_absent(inst, "base", op, "direct mode");
    386     check_operand_metadata_absent(inst, "index", op, "direct mode");
    387   }
    388   // no check for scale; 0 (2**0 = 1) by default
    389 }
    390
    391 // same as compare_bitvector, with one additional exception for modrm-based
    392 // instructions: they may use an extra displacement on occasion
    393 void compare_bitvector_modrm(const line& inst, uint8_t expected, const word& op) {
    394   if (all_hex_bytes(inst) && has_operands(inst)) return;  // deliberately programming in raw hex; we'll raise a warning elsewhere
    395   uint8_t bitvector = compute_expected_operand_bitvector(inst);
    396   if (trace_contains_errors()) return;  // duplicate operand type
    397   // update 'expected' bitvector for the additional exception
    398   if (has_operand_metadata(inst, "mod")) {
    399     int32_t mod = parse_int(metadata(inst, "mod").data);
    400     switch (mod) {
    401     case 0:
    402       if (has_operand_metadata(inst, "rm32") && parse_int(metadata(inst, "rm32").data) == 5)
    403         expected |= (1<<DISP32);
    404       break;
    405     case 1:
    406       expected |= (1<<DISP8);
    407       break;
    408     case 2:
    409       expected |= (1<<DISP32);
    410       break;
    411     }
    412   }
    413   if (bitvector == expected) return;  // all good with this instruction
    414   for (int i = 0;  i < NUM_OPERAND_TYPES;  ++i, bitvector >>= 1, expected >>= 1) {
    415 //?     cerr << "comparing for modrm " << HEXBYTE << NUM(bitvector) << " with " << NUM(expected) << '\n';
    416     if ((bitvector & 0x1) == (expected & 0x1)) continue;  // all good with this operand
    417     const string& optype = Operand_type_name.at(i);
    418     if ((bitvector & 0x1) > (expected & 0x1))
    419       raise << "'" << to_string(inst) << "'" << maybe_name(op) << ": unexpected " << optype << " operand\n" << end();
    420     else
    421       raise << "'" << to_string(inst) << "'" << maybe_name(op) << ": missing " << optype << " operand\n" << end();
    422     // continue giving all errors for a single instruction
    423   }
    424   // ignore settings in any unused bits
    425 }
    426
    427 void check_operand_metadata_present(const line& inst, const string& type, const word& op) {
    428   if (!has_operand_metadata(inst, type))
    429     raise << "'" << to_string(inst) << "'" << maybe_name(op) << ": missing " << type << " operand\n" << end();
    430 }
    431
    432 void check_operand_metadata_absent(const line& inst, const string& type, const word& op, const string& msg) {
    433   if (has_operand_metadata(inst, type))
    434     raise << "'" << to_string(inst) << "'" << maybe_name(op) << ": unexpected " << type << " operand (" << msg << ")\n" << end();
    435 }
    436
    437 void test_modrm_with_displacement() {
    438   Reg[EAX].u = 0x1;
    439   transform(
    440       "== 0x1\n"
    441       // just avoid null pointer
    442       "8b/copy 1/mod/lookup+disp8 0/rm32/EAX 2/r32/EDX 4/disp8\n"  // copy *(EAX+4) to EDX
    443   );
    444   CHECK_TRACE_COUNT("error", 0);
    445 }
    446
    447 void test_check_missing_disp8() {
    448   Hide_errors = true;
    449   transform(
    450       "== 0x1\n"  // code segment
    451       "89/copy 1/mod/lookup+disp8 0/rm32/EAX 1/r32/ECX\n"  // missing disp8
    452   );
    453   CHECK_TRACE_CONTENTS(
    454       "error: '89/copy 1/mod/lookup+disp8 0/rm32/EAX 1/r32/ECX' (copy r32 to rm32): missing disp8 operand\n"
    455   );
    456 }
    457
    458 void test_check_missing_disp32() {
    459   Hide_errors = true;
    460   transform(
    461       "== 0x1\n"  // code segment
    462       "8b/copy 0/mod/indirect 5/rm32/.disp32 2/r32/EDX\n"  // missing disp32
    463   );
    464   CHECK_TRACE_CONTENTS(
    465       "error: '8b/copy 0/mod/indirect 5/rm32/.disp32 2/r32/EDX' (copy rm32 to r32): missing disp32 operand\n"
    466   );
    467 }
    468
    469 void test_conflicting_operands_in_modrm_instruction() {
    470   Hide_errors = true;
    471   run(
    472       "== 0x1\n"  // code segment
    473       "01/add 0/mod 3/mod\n"
    474   );
    475   CHECK_TRACE_CONTENTS(
    476       "error: '01/add 0/mod 3/mod' has conflicting mod operands\n"
    477   );
    478 }
    479
    480 void test_conflicting_operand_type_modrm() {
    481   Hide_errors = true;
    482   run(
    483       "== 0x1\n"  // code segment
    484       "01/add 0/mod 3/rm32/r32\n"
    485   );
    486   CHECK_TRACE_CONTENTS(
    487       "error: '3/rm32/r32' has conflicting operand types; it should have only one\n"
    488   );
    489 }
    490
    491 void test_check_missing_rm32_operand() {
    492   Hide_errors = true;
    493   run(
    494       "== 0x1\n"  // code segment
    495       "81 0/add/subop 0/mod            1/imm32\n"
    496   );
    497   CHECK_TRACE_CONTENTS(
    498       "error: '81 0/add/subop 0/mod 1/imm32' (combine rm32 with imm32 based on subop): missing rm32 operand\n"
    499   );
    500 }
    501
    502 void test_check_missing_subop_operand() {
    503   Hide_errors = true;
    504   run(
    505       "== 0x1\n"  // code segment
    506       "81             0/mod 3/rm32/ebx 1/imm32\n"
    507   );
    508   CHECK_TRACE_CONTENTS(
    509       "error: '81 0/mod 3/rm32/ebx 1/imm32' (combine rm32 with imm32 based on subop): missing subop operand\n"
    510   );
    511 }
    512
    513 void test_check_missing_base_operand() {
    514   Hide_errors = true;
    515   run(
    516       "== 0x1\n"  // code segment
    517       "81 0/add/subop 0/mod/indirect 4/rm32/use-sib 1/imm32\n"
    518   );
    519   CHECK_TRACE_CONTENTS(
    520       "error: '81 0/add/subop 0/mod/indirect 4/rm32/use-sib 1/imm32' (combine rm32 with imm32 based on subop): missing base operand\n"
    521   );
    522 }
    523
    524 void test_check_missing_index_operand() {
    525   Hide_errors = true;
    526   run(
    527       "== 0x1\n"  // code segment
    528       "81 0/add/subop 0/mod/indirect 4/rm32/use-sib 0/base 1/imm32\n"
    529   );
    530   CHECK_TRACE_CONTENTS(
    531       "error: '81 0/add/subop 0/mod/indirect 4/rm32/use-sib 0/base 1/imm32' (combine rm32 with imm32 based on subop): missing index operand\n"
    532   );
    533 }
    534
    535 void test_check_missing_base_operand_2() {
    536   Hide_errors = true;
    537   run(
    538       "== 0x1\n"  // code segment
    539       "81 0/add/subop 0/mod/indirect 4/rm32/use-sib 2/index 3/scale 1/imm32\n"
    540   );
    541   CHECK_TRACE_CONTENTS(
    542       "error: '81 0/add/subop 0/mod/indirect 4/rm32/use-sib 2/index 3/scale 1/imm32' (combine rm32 with imm32 based on subop): missing base operand\n"
    543   );
    544 }
    545
    546 void test_check_extra_displacement() {
    547   Hide_errors = true;
    548   run(
    549       "== 0x1\n"  // code segment
    550       "89/copy 0/mod/indirect 0/rm32/EAX 1/r32/ECX 4/disp8\n"
    551   );
    552   CHECK_TRACE_CONTENTS(
    553       "error: '89/copy 0/mod/indirect 0/rm32/EAX 1/r32/ECX 4/disp8' (copy r32 to rm32): unexpected disp8 operand\n"
    554   );
    555 }
    556
    557 void test_check_duplicate_operand() {
    558   Hide_errors = true;
    559   run(
    560       "== 0x1\n"  // code segment
    561       "89/copy 0/mod/indirect 0/rm32/EAX 1/r32/ECX 1/r32\n"
    562   );
    563   CHECK_TRACE_CONTENTS(
    564       "error: '89/copy 0/mod/indirect 0/rm32/EAX 1/r32/ECX 1/r32': duplicate r32 operand\n"
    565   );
    566 }
    567
    568 void test_check_base_operand_not_needed_in_direct_mode() {
    569   run(
    570       "== 0x1\n"  // code segment
    571       "81 0/add/subop 3/mod/indirect 4/rm32/use-sib 1/imm32\n"
    572   );
    573   CHECK_TRACE_COUNT("error", 0);
    574 }
    575
    576 void test_extra_modrm() {
    577   Hide_errors = true;
    578   run(
    579       "== 0x1\n"  // code segment
    580       "59/pop-to-ECX  3/mod/direct 1/rm32/ECX 4/r32/ESP\n"
    581   );
    582   CHECK_TRACE_CONTENTS(
    583       "error: '59/pop-to-ECX 3/mod/direct 1/rm32/ECX 4/r32/ESP' (pop top of stack to ECX): unexpected modrm operand\n"
    584   );
    585 }
    586
    587 //:: similarly handle multi-byte opcodes
    588
    589 void check_operands_0f(const line& inst) {
    590   assert(inst.words.at(0).data == "0f");
    591   if (SIZE(inst.words) == 1) {
    592     raise << "opcode '0f' requires a second opcode\n" << end();
    593     return;
    594   }
    595   word op = preprocess_op(inst.words.at(1));
    596   if (!contains_key(Name_0f, op.data)) {
    597     raise << "unknown 2-byte opcode '0f " << op.data << "'\n" << end();
    598     return;
    599   }
    600   check_operands_0f(inst, op);
    601 }
    602
    603 void check_operands_f3(const line& /*unused*/) {
    604   raise << "no supported opcodes starting with f3\n" << end();
    605 }
    606
    607 void test_check_missing_disp32_operand() {
    608   Hide_errors = true;
    609   run(
    610       "== 0x1\n"  // code segment
    611       "  0f 84                                                                                                                                             # jmp if ZF to ??\n"
    612   );
    613   CHECK_TRACE_CONTENTS(
    614       "error: '0f 84' (jump disp32 bytes away if equal, if ZF is set): missing disp32 operand\n"
    615   );
    616 }
    617
    618 :(before "End Globals")
    619 map</*op*/string, /*bitvector*/uint8_t> Permitted_operands_0f;
    620 :(before "End Init Permitted Operands")
    621 //// Class D: just op and disp32
    622 //  imm32 imm8  disp32 |disp16  disp8 subop modrm
    623 //  0     0     1      |0       0     0     0
    624 put_new(Permitted_operands_0f, "84", 0x10);
    625 put_new(Permitted_operands_0f, "85", 0x10);
    626 put_new(Permitted_operands_0f, "8c", 0x10);
    627 put_new(Permitted_operands_0f, "8d", 0x10);
    628 put_new(Permitted_operands_0f, "8e", 0x10);
    629 put_new(Permitted_operands_0f, "8f", 0x10);
    630
    631 //// Class M: using ModR/M byte
    632 //  imm32 imm8  disp32 |disp16  disp8 subop modrm
    633 //  0     0     0      |0       0     0     1
    634 put_new(Permitted_operands_0f, "af", 0x01);
    635
    636 :(code)
    637 void check_operands_0f(const line& inst, const word& op) {
    638   uint8_t expected_bitvector = get(Permitted_operands_0f, op.data);
    639   if (HAS(expected_bitvector, MODRM))
    640     check_operands_modrm(inst, op);
    641   compare_bitvector_0f(inst, CLEAR(expected_bitvector, MODRM), op);
    642 }
    643
    644 void compare_bitvector_0f(const line& inst, uint8_t expected, const word& op) {
    645   if (all_hex_bytes(inst) && has_operands(inst)) return;  // deliberately programming in raw hex; we'll raise a warning elsewhere
    646   uint8_t bitvector = compute_expected_operand_bitvector(inst);
    647   if (trace_contains_errors()) return;  // duplicate operand type
    648   if (bitvector == expected) return;  // all good with this instruction
    649   for (int i = 0;  i < NUM_OPERAND_TYPES;  ++i, bitvector >>= 1, expected >>= 1) {
    650 //?     cerr << "comparing " << HEXBYTE << NUM(bitvector) << " with " << NUM(expected) << '\n';
    651     if ((bitvector & 0x1) == (expected & 0x1)) continue;  // all good with this operand
    652     const string& optype = Operand_type_name.at(i);
    653     if ((bitvector & 0x1) > (expected & 0x1))
    654       raise << "'" << to_string(inst) << "'" << maybe_name_0f(op) << ": unexpected " << optype << " operand\n" << end();
    655     else
    656       raise << "'" << to_string(inst) << "'" << maybe_name_0f(op) << ": missing " << optype << " operand\n" << end();
    657     // continue giving all errors for a single instruction
    658   }
    659   // ignore settings in any unused bits
    660 }
    661
    662 string maybe_name_0f(const word& op) {
    663   if (!is_hex_byte(op)) return "";
    664   if (!contains_key(Name_0f, op.data)) return "";
    665   // strip stuff in parens from the name
    666   const string& s = get(Name_0f, op.data);
    667   return " ("+s.substr(0, s.find(" ("))+')';
    668 }
    669
    670 string tolower(const char* s) {
    671   ostringstream out;
    672   for (/*nada*/;  *s;  ++s)
    673     out << static_cast<char>(tolower(*s));
    674   return out.str();
    675 }
    676
    677 #undef HAS
    678 #undef SET
    679 #undef CLEAR
    680
    681 :(before "End Includes")
    682 #include<cctype>