This commit is contained in:
Kartik K. Agaram 2018-01-24 22:43:05 -08:00
parent 9c1d07baec
commit 0c6c7ff714
3 changed files with 20 additions and 28 deletions

View File

@ -28,19 +28,21 @@ int32_t* effective_address(uint8_t modrm) {
uint8_t mod = (modrm>>6);
// ignore middle 3 'reg opcode' bits
uint8_t rm = modrm & 0x7;
int32_t* result = 0;
uint32_t addr = 0;
switch (mod) {
case 3:
// mod 3 is just register direct addressing
trace(2, "run") << "r/m32 is " << rname(rm) << end();
result = &Reg[rm].i;
break;
// End Mod Special-cases
return &Reg[rm].i;
// End Mod Special-cases(addr)
default:
cerr << "unrecognized mod bits: " << NUM(mod) << '\n';
exit(1);
}
return result;
//: other mods are indirect, and they'll set addr appropriately
assert(addr > 0);
assert(addr + sizeof(int32_t) <= Mem.size());
return reinterpret_cast<int32_t*>(&Mem.at(addr)); // rely on the host itself being in little-endian order
}
//:: subtract

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@ -11,15 +11,14 @@
+run: effective address is 0x60 (EAX)
+run: storing 0x00000011
:(before "End Mod Special-cases")
:(before "End Mod Special-cases(addr)")
case 0: // indirect addressing
switch (rm) {
default: // address in register
trace(2, "run") << "effective address is 0x" << std::hex << Reg[rm].u << " (" << rname(rm) << ")" << end();
assert(Reg[rm].u + sizeof(int32_t) <= Mem.size());
result = reinterpret_cast<int32_t*>(&Mem.at(Reg[rm].u)); // rely on the host itself being in little-endian order
addr = Reg[rm].u;
break;
// End Mod 0 Special-cases
// End Mod 0 Special-cases(addr)
}
break;
@ -422,12 +421,10 @@ case 0x8f: { // pop stack into r/m32
+run: storing 0x00000011
:(before "End Mod 0 Special-cases")
case 5: { // exception: mod 0b00 rm 0b101 => incoming disp32
uint32_t addr = imm32();
result = reinterpret_cast<int32_t*>(&Mem.at(addr));
case 5: // exception: mod 0b00 rm 0b101 => incoming disp32
addr = imm32();
trace(2, "run") << "effective address is 0x" << std::hex << addr << " (disp32)" << end();
break;
}
//:
@ -442,18 +439,16 @@ case 5: { // exception: mod 0b00 rm 0b101 => incoming disp32
+run: effective address is 0x60 (EAX+disp8)
+run: storing 0x00000011
:(before "End Mod Special-cases")
:(before "End Mod Special-cases(addr)")
case 1: // indirect + disp8 addressing
switch (rm) {
default: {
int8_t disp = next();
uint32_t addr = Reg[rm].u + disp;
addr = Reg[rm].u + disp;
trace(2, "run") << "effective address is 0x" << std::hex << addr << " (" << rname(rm) << "+disp8)" << end();
assert(addr + sizeof(int32_t) <= Mem.size());
result = reinterpret_cast<int32_t*>(&Mem.at(addr)); // rely on the host itself being in little-endian order
break;
}
// End Mod 1 Special-cases
// End Mod 1 Special-cases(addr)
}
break;
@ -481,18 +476,16 @@ case 1: // indirect + disp8 addressing
+run: effective address is 0x60 (EAX+disp32)
+run: storing 0x00000011
:(before "End Mod Special-cases")
:(before "End Mod Special-cases(addr)")
case 2: // indirect + disp32 addressing
switch (rm) {
default: {
int32_t disp = imm32();
uint32_t addr = Reg[rm].u + disp;
addr = Reg[rm].u + disp;
trace(2, "run") << "effective address is 0x" << std::hex << addr << " (" << rname(rm) << "+disp32)" << end();
assert(addr + sizeof(int32_t) <= Mem.size());
result = reinterpret_cast<int32_t*>(&Mem.at(addr)); // rely on the host itself being in little-endian order
break;
}
// End Mod 2 Special-cases
// End Mod 2 Special-cases(addr)
}
break;

View File

@ -14,12 +14,9 @@
+run: storing 0x00000011
:(before "End Mod 0 Special-cases")
case 4: { // exception: mod 0b00 rm 0b100 => incoming SIB (scale-index-base) byte
uint32_t addr = effective_address_from_sib(mod);
if (addr == 0) break;
result = reinterpret_cast<int32_t*>(&Mem.at(addr));
case 4: // exception: mod 0b00 rm 0b100 => incoming SIB (scale-index-base) byte
addr = effective_address_from_sib(mod);
break;
}
:(code)
uint32_t effective_address_from_sib(uint8_t mod) {
uint8_t sib = next();