parent
7c0f7d69ae
commit
1091118ae5
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@ -98,10 +98,10 @@ void run(const string& text_bytes) {
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void run_one_instruction() {
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uint8_t op=0, op2=0, op3=0;
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switch (op = next()) {
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// our first opcode
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case 0xf4: // hlt
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EIP = End_of_program;
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break;
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// our first opcode
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case 0x05: { // add imm32 to EAX
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int32_t arg2 = imm32();
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trace(2, "run") << "add imm32 0x" << HEXWORD << arg2 << " to reg EAX" << end();
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@ -29,18 +29,21 @@ int32_t* effective_address(uint8_t modrm) {
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uint8_t rm = modrm & 0x7;
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int32_t* result = 0;
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switch (mod) {
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case 0:
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// mod 0 is usually indirect addressing
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switch (rm) {
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default:
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trace(99, "run") << "effective address is mem at address 0x" << std::hex << Reg[rm].u << " (reg " << static_cast<int>(rm) << ")" << end();
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assert(Reg[rm].u + sizeof(int32_t) <= Mem.size());
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result = reinterpret_cast<int32_t*>(&Mem.at(Reg[rm].u)); // rely on the host itself being in little-endian order
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break;
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// End Mod 0 Special-Cases
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}
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case 0:
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// mod 0 is usually indirect addressing
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switch (rm) {
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default:
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trace(99, "run") << "effective address is mem at address 0x" << std::hex << Reg[rm].u << " (reg " << static_cast<int>(rm) << ")" << end();
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assert(Reg[rm].u + sizeof(int32_t) <= Mem.size());
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result = reinterpret_cast<int32_t*>(&Mem.at(Reg[rm].u)); // rely on the host itself being in little-endian order
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break;
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// End Mod Special-Cases
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// End Mod 0 Special-Cases
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}
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break;
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// End Mod Special-Cases
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default:
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cerr << "unrecognized mod bits: " << static_cast<int>(mod) << '\n';
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exit(1);
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}
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return result;
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}
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