Fix non-standard switch statement.
This commit is contained in:
Kartik K. Agaram 2017-10-12 21:02:11 -07:00
parent 7c0f7d69ae
commit 1091118ae5
2 changed files with 15 additions and 12 deletions

View File

@ -98,10 +98,10 @@ void run(const string& text_bytes) {
void run_one_instruction() {
uint8_t op=0, op2=0, op3=0;
switch (op = next()) {
// our first opcode
case 0xf4: // hlt
EIP = End_of_program;
break;
// our first opcode
case 0x05: { // add imm32 to EAX
int32_t arg2 = imm32();
trace(2, "run") << "add imm32 0x" << HEXWORD << arg2 << " to reg EAX" << end();

View File

@ -29,18 +29,21 @@ int32_t* effective_address(uint8_t modrm) {
uint8_t rm = modrm & 0x7;
int32_t* result = 0;
switch (mod) {
case 0:
// mod 0 is usually indirect addressing
switch (rm) {
default:
trace(99, "run") << "effective address is mem at address 0x" << std::hex << Reg[rm].u << " (reg " << static_cast<int>(rm) << ")" << end();
assert(Reg[rm].u + sizeof(int32_t) <= Mem.size());
result = reinterpret_cast<int32_t*>(&Mem.at(Reg[rm].u)); // rely on the host itself being in little-endian order
break;
// End Mod 0 Special-Cases
}
case 0:
// mod 0 is usually indirect addressing
switch (rm) {
default:
trace(99, "run") << "effective address is mem at address 0x" << std::hex << Reg[rm].u << " (reg " << static_cast<int>(rm) << ")" << end();
assert(Reg[rm].u + sizeof(int32_t) <= Mem.size());
result = reinterpret_cast<int32_t*>(&Mem.at(Reg[rm].u)); // rely on the host itself being in little-endian order
break;
// End Mod Special-Cases
// End Mod 0 Special-Cases
}
break;
// End Mod Special-Cases
default:
cerr << "unrecognized mod bits: " << static_cast<int>(mod) << '\n';
exit(1);
}
return result;
}