4049
Instead of organizing layers by instruction, do so by addressing mode.
This commit is contained in:
Kartik K. Agaram
parent
293dd258ff
commit
159af42367
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@ -1,4 +1,4 @@
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//:: register indirect addressing
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//: operating on memory at the address provided by some register
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:(scenario add_r32_to_mem_at_r32)
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% Reg[3].i = 0x10;
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@ -50,56 +50,6 @@ int32_t* effective_address(uint8_t modrm) {
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return result;
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}
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//:: register direct addressing
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:(scenario add_imm32_to_r32)
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% Reg[3].i = 1;
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# op ModRM SIB displacement immediate
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81 c3 0a 0b 0c 0d # add 0x0d0c0b0a to EBX (reg 3)
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+run: combine imm32 0x0d0c0b0a with effective address
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+run: effective address is reg 3
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+run: subop add
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+run: storing 0x0d0c0b0b
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:(before "End Single-Byte Opcodes")
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case 0x81: { // combine imm32 with r/m32
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uint8_t modrm = next();
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int32_t arg2 = imm32();
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trace(2, "run") << "combine imm32 0x" << HEXWORD << arg2 << " with effective address" << end();
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int32_t* arg1 = effective_address(modrm);
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uint8_t subop = (modrm>>3)&0x7; // middle 3 'reg opcode' bits
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switch (subop) {
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case 0:
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trace(2, "run") << "subop add" << end();
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BINARY_ARITHMETIC_OP(+, *arg1, arg2);
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break;
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// End Op 81 Subops
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default:
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cerr << "unrecognized sub-opcode after 81: " << NUM(subop) << '\n';
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exit(1);
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}
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break;
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}
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:(before "End Mod Special-cases")
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case 3:
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// mod 3 is just register direct addressing
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trace(2, "run") << "effective address is reg " << NUM(rm) << end();
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result = &Reg[rm].i;
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break;
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//:: lots more tests
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:(scenario add_imm32_to_mem_at_r32)
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% Reg[3].i = 0x60;
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% Mem.at(0x60) = 1;
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# op ModR/M SIB displacement immediate
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81 03 0a 0b 0c 0d # add 0x0d0c0b0a to *EBX (reg 3)
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+run: combine imm32 0x0d0c0b0a with effective address
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+run: effective address is mem at address 0x60 (reg 3)
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+run: subop add
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+run: storing 0x0d0c0b0b
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//:
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:(scenario add_mem_at_r32_to_r32)
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@ -122,54 +72,7 @@ case 0x03: { // add r/m32 to r32
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break;
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}
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//:
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:(scenario sub_imm32_from_eax)
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% Reg[EAX].i = 0x0d0c0baa;
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# op ModR/M SIB displacement immediate
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2d 0a 0b 0c 0d # subtract 0x0d0c0b0a from EAX (reg 0)
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+run: subtract imm32 0x0d0c0b0a from reg EAX
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+run: storing 0x000000a0
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:(before "End Single-Byte Opcodes")
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case 0x2d: { // subtract imm32 from EAX
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int32_t arg2 = imm32();
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trace(2, "run") << "subtract imm32 0x" << HEXWORD << arg2 << " from reg EAX" << end();
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BINARY_ARITHMETIC_OP(-, Reg[EAX].i, arg2);
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break;
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}
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//:
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:(scenario sub_imm32_from_r32)
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% Reg[3].i = 10;
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# op ModRM SIB displacement immediate
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81 eb 01 00 00 00 # subtract 1 from EBX (reg 3)
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+run: combine imm32 0x00000001 with effective address
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+run: effective address is reg 3
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+run: subop subtract
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+run: storing 0x00000009
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:(before "End Op 81 Subops")
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case 5: {
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trace(2, "run") << "subop subtract" << end();
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BINARY_ARITHMETIC_OP(-, *arg1, arg2);
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break;
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}
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//:
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:(scenario sub_imm32_from_mem_at_r32)
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% Reg[3].i = 0x60;
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% Mem.at(0x60) = 10;
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# op ModRM SIB displacement immediate
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81 2b 01 00 00 00 # subtract 1 from *EBX (reg 3)
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+run: combine imm32 0x00000001 with effective address
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+run: effective address is mem at address 0x60 (reg 3)
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+run: subop subtract
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+run: storing 0x00000009
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//:
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//:: subtract
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:(scenario sub_r32_from_mem_at_r32)
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% Reg[0].i = 0x60;
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@ -0,0 +1,10 @@
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//: operating directly on a register
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:(before "End Mod Special-cases")
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case 3:
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// mod 3 is just register direct addressing
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trace(2, "run") << "effective address is reg " << NUM(rm) << end();
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result = &Reg[rm].i;
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break;
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//:: subtract
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@ -0,0 +1,89 @@
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//: instructions that (immediately) contain an argument to act with
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:(scenario add_imm32_to_r32)
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% Reg[3].i = 1;
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# op ModRM SIB displacement immediate
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81 c3 0a 0b 0c 0d # add 0x0d0c0b0a to EBX (reg 3)
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+run: combine imm32 0x0d0c0b0a with effective address
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+run: effective address is reg 3
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+run: subop add
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+run: storing 0x0d0c0b0b
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:(before "End Single-Byte Opcodes")
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case 0x81: { // combine imm32 with r/m32
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uint8_t modrm = next();
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int32_t arg2 = imm32();
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trace(2, "run") << "combine imm32 0x" << HEXWORD << arg2 << " with effective address" << end();
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int32_t* arg1 = effective_address(modrm);
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uint8_t subop = (modrm>>3)&0x7; // middle 3 'reg opcode' bits
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switch (subop) {
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case 0:
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trace(2, "run") << "subop add" << end();
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BINARY_ARITHMETIC_OP(+, *arg1, arg2);
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break;
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// End Op 81 Subops
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default:
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cerr << "unrecognized sub-opcode after 81: " << NUM(subop) << '\n';
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exit(1);
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}
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break;
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}
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//:
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:(scenario add_imm32_to_mem_at_r32)
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% Reg[3].i = 0x60;
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% Mem.at(0x60) = 1;
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# op ModR/M SIB displacement immediate
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81 03 0a 0b 0c 0d # add 0x0d0c0b0a to *EBX (reg 3)
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+run: combine imm32 0x0d0c0b0a with effective address
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+run: effective address is mem at address 0x60 (reg 3)
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+run: subop add
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+run: storing 0x0d0c0b0b
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//:: subtract
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:(scenario sub_imm32_from_eax)
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% Reg[EAX].i = 0x0d0c0baa;
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# op ModR/M SIB displacement immediate
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2d 0a 0b 0c 0d # subtract 0x0d0c0b0a from EAX (reg 0)
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+run: subtract imm32 0x0d0c0b0a from reg EAX
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+run: storing 0x000000a0
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:(before "End Single-Byte Opcodes")
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case 0x2d: { // subtract imm32 from EAX
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int32_t arg2 = imm32();
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trace(2, "run") << "subtract imm32 0x" << HEXWORD << arg2 << " from reg EAX" << end();
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BINARY_ARITHMETIC_OP(-, Reg[EAX].i, arg2);
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break;
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}
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//:
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:(scenario sub_imm32_from_mem_at_r32)
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% Reg[3].i = 0x60;
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% Mem.at(0x60) = 10;
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# op ModRM SIB displacement immediate
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81 2b 01 00 00 00 # subtract 1 from *EBX (reg 3)
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+run: combine imm32 0x00000001 with effective address
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+run: effective address is mem at address 0x60 (reg 3)
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+run: subop subtract
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+run: storing 0x00000009
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//:
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:(scenario sub_imm32_from_r32)
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% Reg[3].i = 10;
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# op ModRM SIB displacement immediate
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81 eb 01 00 00 00 # subtract 1 from EBX (reg 3)
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+run: combine imm32 0x00000001 with effective address
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+run: effective address is reg 3
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+run: subop subtract
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+run: storing 0x00000009
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:(before "End Op 81 Subops")
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case 5: {
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trace(2, "run") << "subop subtract" << end();
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BINARY_ARITHMETIC_OP(-, *arg1, arg2);
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break;
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}
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