4055
subx: Implement 'and' for the addressing modes we've built so far.
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@ -62,3 +62,24 @@ case 0x29: { // subtract r32 from r/m32
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BINARY_ARITHMETIC_OP(-, *arg1, Reg[arg2].i);
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BINARY_ARITHMETIC_OP(-, *arg1, Reg[arg2].i);
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break;
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break;
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}
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}
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//:: and
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:(scenario and_r32_with_r32)
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% Reg[0].i = 0x0a0b0c0d;
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% Reg[3].i = 0x000000ff;
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# op ModR/M SIB displacement immediate
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21 d8 # and EBX (reg 3) with destination EAX (reg 0)
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+run: and reg 3 with effective address
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+run: effective address is reg 0
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+run: storing 0x0000000d
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:(before "End Single-Byte Opcodes")
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case 0x21: { // and r32 with r/m32
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uint8_t modrm = next();
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uint8_t arg2 = (modrm>>3)&0x7;
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trace(2, "run") << "and reg " << NUM(arg2) << " with effective address" << end();
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int32_t* arg1 = effective_address(modrm);
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BINARY_BITWISE_OP(&, *arg1, Reg[arg2].u);
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break;
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}
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@ -79,3 +79,40 @@ case 0x2b: { // subtract r/m32 from r32
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BINARY_ARITHMETIC_OP(-, Reg[arg1].i, *arg2);
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BINARY_ARITHMETIC_OP(-, Reg[arg1].i, *arg2);
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break;
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break;
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}
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}
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//:: and
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:(scenario and_r32_with_mem_at_r32)
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% Reg[0].i = 0x60;
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% Mem.at(0x60) = 0x0d;
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% Mem.at(0x61) = 0x0c;
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% Mem.at(0x62) = 0x0b;
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% Mem.at(0x63) = 0x0a;
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% Reg[3].i = 0xff;
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# op ModRM SIB displacement immediate
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21 18 # and EBX (reg 3) with *EAX (reg 0)
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+run: and reg 3 with effective address
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+run: effective address is mem at address 0x60 (reg 0)
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+run: storing 0x0000000d
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//:
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:(scenario and_mem_at_r32_with_r32)
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% Reg[0].i = 0x60;
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% Mem.at(0x60) = 0xff;
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% Reg[3].i = 0x0a0b0c0d;
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# op ModRM SIB displacement immediate
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23 18 # and *EAX (reg 0) with EBX (reg 3)
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+run: and effective address with reg 3
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+run: effective address is mem at address 0x60 (reg 0)
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+run: storing 0x0000000d
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:(before "End Single-Byte Opcodes")
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case 0x23: { // and r/m32 with r32
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uint8_t modrm = next();
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uint8_t arg1 = (modrm>>3)&0x7;
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trace(2, "run") << "and effective address with reg " << NUM(arg1) << end();
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const int32_t* arg2 = effective_address(modrm);
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BINARY_BITWISE_OP(&, Reg[arg1].u, *arg2);
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break;
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}
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@ -87,3 +87,50 @@ case 5: {
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BINARY_ARITHMETIC_OP(-, *arg1, arg2);
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BINARY_ARITHMETIC_OP(-, *arg1, arg2);
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break;
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break;
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}
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}
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//:: and
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:(scenario and_imm32_with_eax)
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% Reg[EAX].i = 0xff;
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# op ModR/M SIB displacement immediate
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25 0a 0b 0c 0d # and 0x0d0c0b0a with EAX (reg 0)
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+run: and imm32 0x0d0c0b0a with reg EAX
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+run: storing 0x0000000a
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:(before "End Single-Byte Opcodes")
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case 0x25: { // and imm32 with EAX
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int32_t arg2 = imm32();
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trace(2, "run") << "and imm32 0x" << HEXWORD << arg2 << " with reg EAX" << end();
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BINARY_BITWISE_OP(&, Reg[EAX].i, arg2);
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break;
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}
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//:
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:(scenario and_imm32_with_mem_at_r32)
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% Reg[3].i = 0x60;
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% Mem.at(0x60) = 0xff;
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# op ModRM SIB displacement immediate
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81 23 0a 0b 0c 0d # and 0x0d0c0b0a with *EBX (reg 3)
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+run: combine imm32 0x0d0c0b0a with effective address
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+run: effective address is mem at address 0x60 (reg 3)
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+run: subop and
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+run: storing 0x0000000a
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//:
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:(scenario and_imm32_with_r32)
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% Reg[3].i = 0xff;
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# op ModRM SIB displacement immediate
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81 e3 0a 0b 0c 0d # and 0x0d0c0b0a with EBX (reg 3)
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+run: combine imm32 0x0d0c0b0a with effective address
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+run: effective address is reg 3
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+run: subop and
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+run: storing 0x0000000a
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:(before "End Op 81 Subops")
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case 4: {
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trace(2, "run") << "subop and" << end();
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BINARY_BITWISE_OP(&, *arg1, arg2);
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break;
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}
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