diff --git a/subx/011direct_addressing.cc b/subx/011direct_addressing.cc
index de5e923a..bbd482d4 100644
--- a/subx/011direct_addressing.cc
+++ b/subx/011direct_addressing.cc
@@ -83,3 +83,24 @@ case 0x21: {  // and r32 with r/m32
   BINARY_BITWISE_OP(&, *arg1, Reg[arg2].u);
   break;
 }
+
+//:: or
+
+:(scenario or_r32_with_r32)
+% Reg[0].i = 0x0a0b0c0d;
+% Reg[3].i = 0xa0b0c0d0;
+# op  ModR/M  SIB   displacement  immediate
+  09  d8                                      # or EBX (reg 3) with destination EAX (reg 0)
++run: or reg 3 with effective address
++run: effective address is reg 0
++run: storing 0xaabbccdd
+
+:(before "End Single-Byte Opcodes")
+case 0x09: {  // or r32 with r/m32
+  uint8_t modrm = next();
+  uint8_t arg2 = (modrm>>3)&0x7;
+  trace(2, "run") << "or reg " << NUM(arg2) << " with effective address" << end();
+  int32_t* arg1 = effective_address(modrm);
+  BINARY_BITWISE_OP(|, *arg1, Reg[arg2].u);
+  break;
+}
diff --git a/subx/012indirect_addressing.cc b/subx/012indirect_addressing.cc
index 6e9a5f01..4cc3cb9d 100644
--- a/subx/012indirect_addressing.cc
+++ b/subx/012indirect_addressing.cc
@@ -116,3 +116,43 @@ case 0x23: {  // and r/m32 with r32
   BINARY_BITWISE_OP(&, Reg[arg1].u, *arg2);
   break;
 }
+
+//:: or
+
+:(scenario or_r32_with_mem_at_r32)
+% Reg[0].i = 0x60;
+% Mem.at(0x60) = 0x0d;
+% Mem.at(0x61) = 0x0c;
+% Mem.at(0x62) = 0x0b;
+% Mem.at(0x63) = 0x0a;
+% Reg[3].i = 0xa0b0c0d0;
+# op  ModRM   SIB   displacement  immediate
+  09  18                                      # or EBX (reg 3) with *EAX (reg 0)
++run: or reg 3 with effective address
++run: effective address is mem at address 0x60 (reg 0)
++run: storing 0xaabbccdd
+
+//:
+
+:(scenario or_mem_at_r32_with_r32)
+% Reg[0].i = 0x60;
+% Mem.at(0x60) = 0x0d;
+% Mem.at(0x61) = 0x0c;
+% Mem.at(0x62) = 0x0b;
+% Mem.at(0x63) = 0x0a;
+% Reg[3].i = 0xa0b0c0d0;
+# op  ModRM   SIB   displacement  immediate
+  0b  18                                      # or *EAX (reg 0) with EBX (reg 3)
++run: or effective address with reg 3
++run: effective address is mem at address 0x60 (reg 0)
++run: storing 0xaabbccdd
+
+:(before "End Single-Byte Opcodes")
+case 0x0b: {  // or r/m32 with r32
+  uint8_t modrm = next();
+  uint8_t arg1 = (modrm>>3)&0x7;
+  trace(2, "run") << "or effective address with reg " << NUM(arg1) << end();
+  const int32_t* arg2 = effective_address(modrm);
+  BINARY_BITWISE_OP(|, Reg[arg1].u, *arg2);
+  break;
+}
diff --git a/subx/013immediate_addressing.cc b/subx/013immediate_addressing.cc
index 8fe39279..396c1bfd 100644
--- a/subx/013immediate_addressing.cc
+++ b/subx/013immediate_addressing.cc
@@ -134,3 +134,53 @@ case 4: {
   BINARY_BITWISE_OP(&, *arg1, arg2);
   break;
 }
+
+//:: or
+
+:(scenario or_imm32_with_eax)
+% Reg[EAX].i = 0xd0c0b0a0;
+# op  ModR/M  SIB   displacement  immediate
+  0d                              0a 0b 0c 0d  # or 0x0d0c0b0a with EAX (reg 0)
++run: or imm32 0x0d0c0b0a with reg EAX
++run: storing 0xddccbbaa
+
+:(before "End Single-Byte Opcodes")
+case 0x0d: {  // or imm32 with EAX
+  int32_t arg2 = imm32();
+  trace(2, "run") << "or imm32 0x" << HEXWORD << arg2 << " with reg EAX" << end();
+  BINARY_BITWISE_OP(|, Reg[EAX].i, arg2);
+  break;
+}
+
+//:
+
+:(scenario or_imm32_with_mem_at_r32)
+% Reg[3].i = 0x60;
+% Mem.at(0x60) = 0xa0;
+% Mem.at(0x61) = 0xb0;
+% Mem.at(0x62) = 0xc0;
+% Mem.at(0x63) = 0xd0;
+# op  ModRM   SIB   displacement  immediate
+  81  0b                          0a 0b 0c 0d  # or 0x0d0c0b0a with *EBX (reg 3)
++run: combine imm32 0x0d0c0b0a with effective address
++run: effective address is mem at address 0x60 (reg 3)
++run: subop or
++run: storing 0xddccbbaa
+
+//:
+
+:(scenario or_imm32_with_r32)
+% Reg[3].i = 0xd0c0b0a0;
+# op  ModRM   SIB   displacement  immediate
+  81  cb                          0a 0b 0c 0d  # or 0x0d0c0b0a with EBX (reg 3)
++run: combine imm32 0x0d0c0b0a with effective address
++run: effective address is reg 3
++run: subop or
++run: storing 0xddccbbaa
+
+:(before "End Op 81 Subops")
+case 1: {
+  trace(2, "run") << "subop or" << end();
+  BINARY_BITWISE_OP(|, *arg1, arg2);
+  break;
+}