diff --git a/html/mu_instructions.html b/html/mu_instructions.html
index 6f7f85f8..b12e3f12 100644
--- a/html/mu_instructions.html
+++ b/html/mu_instructions.html
@@ -10,20 +10,19 @@
@@ -48,7 +47,7 @@ the SubX instruction they're translated to.
These instructions use the general-purpose registers.
-var/eax <- increment => "40/increment-eax"
+var/eax <- increment => "40/increment-eax"
var/ecx <- increment => "41/increment-ecx"
var/edx <- increment => "42/increment-edx"
var/ebx <- increment => "43/increment-ebx"
@@ -57,7 +56,7 @@ var/edi <- increme
increment var => "ff 0/subop/increment *(ebp+" var.stack-offset ")"
increment *var/reg => "ff 0/subop/increment *" reg
-var/eax <- decrement => "48/decrement-eax"
+var/eax <- decrement => "48/decrement-eax"
var/ecx <- decrement => "49/decrement-ecx"
var/edx <- decrement => "4a/decrement-edx"
var/ebx <- decrement => "4b/decrement-ebx"
@@ -71,7 +70,7 @@ var/reg <- add var2 => <- add *var2/reg2 => "03/add *" reg2 " " reg "/r32"
add-to var1, var2/reg => "01/add-to *(ebp+" var1.stack-offset ") " reg "/r32"
add-to *var1/reg1, var2/reg2 => "01/add-to *" reg1 " " reg2 "/r32"
-var/eax <- add n => "05/add-to-eax " n "/imm32"
+var/eax <- add n => "05/add-to-eax " n "/imm32"
var/reg <- add n => "81 0/subop/add %" reg " " n "/imm32"
add-to var, n => "81 0/subop/add *(ebp+" var.stack-offset ") " n "/imm32"
add-to *var/reg, n => "81 0/subop/add *" reg " " n "/imm32"
@@ -81,7 +80,7 @@ var/reg <- subtract var2 => <- subtract *var2/reg2 => "2b/subtract *" reg2 " " reg1 "/r32"
subtract-from var1, var2/reg2 => "29/subtract-from *(ebp+" var1.stack-offset ") " reg2 "/r32"
subtract-from *var1/reg1, var2/reg2 => "29/subtract-from *" reg1 " " reg2 "/r32"
-var/eax <- subtract n => "2d/subtract-from-eax " n "/imm32"
+var/eax <- subtract n => "2d/subtract-from-eax " n "/imm32"
var/reg <- subtract n => "81 5/subop/subtract %" reg " " n "/imm32"
subtract-from var, n => "81 5/subop/subtract *(ebp+" var.stack-offset ") " n "/imm32"
subtract-from *var/reg, n => "81 5/subop/subtract *" reg " " n "/imm32"
@@ -91,7 +90,7 @@ var/reg <- and var2 => <- and *var2/reg2 => "23/and *" reg2 " " reg "/r32"
and-with var1, var2/reg => "21/and-with *(ebp+" var1.stack-offset ") " reg "/r32"
and-with *var1/reg1, var2/reg2 => "21/and-with *" reg1 " " reg2 "/r32"
-var/eax <- and n => "25/and-with-eax " n "/imm32"
+var/eax <- and n => "25/and-with-eax " n "/imm32"
var/reg <- and n => "81 4/subop/and %" reg " " n "/imm32"
and-with var, n => "81 4/subop/and *(ebp+" var.stack-offset ") " n "/imm32"
and-with *var/reg, n => "81 4/subop/and *" reg " " n "/imm32"
@@ -101,7 +100,7 @@ var/reg <- or var2 => <- or *var2/reg2 => "0b/or *" reg2 " " reg "/r32"
or-with var1, var2/reg2 => "09/or-with *(ebp+" var1.stack-offset " " reg2 "/r32"
or-with *var1/reg1, var2/reg2 => "09/or-with *" reg1 " " reg2 "/r32"
-var/eax <- or n => "0d/or-with-eax " n "/imm32"
+var/eax <- or n => "0d/or-with-eax " n "/imm32"
var/reg <- or n => "81 1/subop/or %" reg " " n "/imm32"
or-with var, n => "81 1/subop/or *(ebp+" var.stack-offset ") " n "/imm32"
or-with *var/reg, n => "81 1/subop/or *" reg " " n "/imm32"
@@ -115,7 +114,7 @@ var/reg <- xor var2 => <- xor *var2/reg2 => "33/xor *" reg2 " " reg "/r32"
xor-with var1, var2/reg => "31/xor-with *(ebp+" var1.stack-offset ") " reg "/r32"
xor-with *var1/reg1, var2/reg2 => "31/xor-with *" reg1 " " reg2 "/r32"
-var/eax <- xor n => "35/xor-with-eax " n "/imm32"
+var/eax <- xor n => "35/xor-with-eax " n "/imm32"
var/reg <- xor n => "81 6/subop/xor %" reg " " n "/imm32"
xor-with var, n => "81 6/subop/xor *(ebp+" var.stack-offset ") " n "/imm32"
xor-with *var/reg, n => "81 6/subop/xor *" reg " " n "/imm32"
@@ -134,7 +133,7 @@ shift-right *var/reg, n => "c1/shift 5/
shift-right-signed var, n => "c1/shift 7/subop/right-signed *(ebp+" var.stack-offset ") " n "/imm32"
shift-right-signed *var/reg, n => "c1/shift 7/subop/right-signed *" reg " " n "/imm32"
-var/eax <- copy n => "b8/copy-to-eax " n "/imm32"
+var/eax <- copy n => "b8/copy-to-eax " n "/imm32"
var/ecx <- copy n => "b9/copy-to-ecx " n "/imm32"
var/edx <- copy n => "ba/copy-to-edx " n "/imm32"
var/ebx <- copy n => "bb/copy-to-ebx " n "/imm32"
@@ -159,7 +158,7 @@ compare var1, var2/reg2 => "39/compare
compare *var1/reg1, var2/reg2 => "39/compare *" reg1 " " reg2 "/r32"
compare var1/reg1, var2 => "3b/compare<- *(ebp+" var2.stack-offset ") " reg1 "/r32"
compare var/reg, *var2/reg2 => "3b/compare<- *" reg " " n "/imm32"
-compare var/eax, n => "3d/compare-eax-with " n "/imm32"
+compare var/eax, n => "3d/compare-eax-with " n "/imm32"
compare var/reg, n => "81 7/subop/compare %" reg " " n "/imm32"
compare var, n => "81 7/subop/compare *(ebp+" var.stack-offset ") " n "/imm32"
compare *var/reg, n => "81 7/subop/compare *" reg " " n "/imm32"
@@ -414,8 +413,8 @@ var/reg: int <- length arr/reg2: (addr array T)
"c1/shift 5/subop/logic-right %" reg " " log2(size-of(T)) "/imm8"
| otherwise
x86 has no instruction to divide by a literal, so
- we need up to 3 extra registers! eax/edx for division and say ecx
- => if reg is not eax
+ we need up to 3 extra registers! eax/edx for division and say ecx
+ => if reg is not eax
"50/push-eax"
if reg is not ecx
"51/push-ecx"
@@ -425,13 +424,13 @@ var/reg: int <- length arr/reg2: (addr array T)
"31/xor %edx 2/r32/edx"
"b9/copy-to-ecx " size-of(T) "/imm32"
"f7 7/subop/idiv-eax-edx-by %ecx"
- if reg is not eax
+ if reg is not eax
"89/<- %" reg " 0/r32/eax"
if reg is not edx
"5a/pop-to-edx"
if reg is not ecx
"59/pop-to-ecx"
- if reg is not eax
+ if reg is not eax
"58/pop-to-eax"