795 lines
23 KiB
C++
795 lines
23 KiB
C++
//: operating directly on a register
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:(before "End Initialize Op Names")
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put_new(Name, "01", "add r32 to rm32 (add)");
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:(scenario add_r32_to_r32)
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% Reg[EAX].i = 0x10;
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% Reg[EBX].i = 1;
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== 0x1
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# op ModR/M SIB displacement immediate
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01 d8 # add EBX to EAX
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# ModR/M in binary: 11 (direct mode) 011 (src EBX) 000 (dest EAX)
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+run: add EBX to r/m32
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+run: r/m32 is EAX
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+run: storing 0x00000011
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:(before "End Single-Byte Opcodes")
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case 0x01: { // add r32 to r/m32
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uint8_t modrm = next();
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uint8_t arg2 = (modrm>>3)&0x7;
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trace(90, "run") << "add " << rname(arg2) << " to r/m32" << end();
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int32_t* arg1 = effective_address(modrm);
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BINARY_ARITHMETIC_OP(+, *arg1, Reg[arg2].i);
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break;
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}
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:(code)
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// Implement tables 2-2 and 2-3 in the Intel manual, Volume 2.
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// We return a pointer so that instructions can write to multiple bytes in
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// 'Mem' at once.
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int32_t* effective_address(uint8_t modrm) {
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const uint8_t mod = (modrm>>6);
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// ignore middle 3 'reg opcode' bits
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const uint8_t rm = modrm & 0x7;
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if (mod == 3) {
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// mod 3 is just register direct addressing
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trace(90, "run") << "r/m32 is " << rname(rm) << end();
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return &Reg[rm].i;
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}
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return mem_addr_i32(effective_address_number(modrm));
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}
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uint32_t effective_address_number(uint8_t modrm) {
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const uint8_t mod = (modrm>>6);
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// ignore middle 3 'reg opcode' bits
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const uint8_t rm = modrm & 0x7;
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uint32_t addr = 0;
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switch (mod) {
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case 3:
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// mod 3 is just register direct addressing
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raise << "unexpected direct addressing mode\n" << end();
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return 0;
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// End Mod Special-cases(addr)
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default:
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cerr << "unrecognized mod bits: " << NUM(mod) << '\n';
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exit(1);
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}
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//: other mods are indirect, and they'll set addr appropriately
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return addr;
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}
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string rname(uint8_t r) {
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switch (r) {
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case 0: return "EAX";
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case 1: return "ECX";
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case 2: return "EDX";
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case 3: return "EBX";
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case 4: return "ESP";
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case 5: return "EBP";
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case 6: return "ESI";
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case 7: return "EDI";
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default: raise << "invalid register " << r << '\n' << end(); return "";
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}
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}
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//:: subtract
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:(before "End Initialize Op Names")
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put_new(Name, "29", "subtract r32 from rm32 (sub)");
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:(scenario subtract_r32_from_r32)
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% Reg[EAX].i = 10;
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% Reg[EBX].i = 1;
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== 0x1
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# op ModR/M SIB displacement immediate
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29 d8 # subtract EBX from EAX
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# ModR/M in binary: 11 (direct mode) 011 (src EBX) 000 (dest EAX)
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+run: subtract EBX from r/m32
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+run: r/m32 is EAX
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+run: storing 0x00000009
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:(before "End Single-Byte Opcodes")
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case 0x29: { // subtract r32 from r/m32
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const uint8_t modrm = next();
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const uint8_t arg2 = (modrm>>3)&0x7;
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trace(90, "run") << "subtract " << rname(arg2) << " from r/m32" << end();
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int32_t* arg1 = effective_address(modrm);
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BINARY_ARITHMETIC_OP(-, *arg1, Reg[arg2].i);
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break;
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}
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//:: multiply
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:(before "End Initialize Op Names")
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put_new(Name, "f7", "negate/multiply rm32 (with EAX if necessary) depending on subop (neg/mul)");
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:(scenario multiply_eax_by_r32)
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% Reg[EAX].i = 4;
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% Reg[ECX].i = 3;
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== 0x1
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# op ModR/M SIB displacement immediate
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f7 e1 # multiply EAX by ECX
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# ModR/M in binary: 11 (direct mode) 100 (subop mul) 001 (src ECX)
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+run: operate on r/m32
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+run: r/m32 is ECX
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+run: subop: multiply EAX by r/m32
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+run: storing 0x0000000c
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:(before "End Single-Byte Opcodes")
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case 0xf7: {
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const uint8_t modrm = next();
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trace(90, "run") << "operate on r/m32" << end();
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int32_t* arg1 = effective_address(modrm);
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const uint8_t subop = (modrm>>3)&0x7; // middle 3 'reg opcode' bits
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switch (subop) {
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case 4: { // mul unsigned EAX by r/m32
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trace(90, "run") << "subop: multiply EAX by r/m32" << end();
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const uint64_t result = Reg[EAX].u * static_cast<uint32_t>(*arg1);
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Reg[EAX].u = result & 0xffffffff;
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Reg[EDX].u = result >> 32;
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OF = (Reg[EDX].u != 0);
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trace(90, "run") << "storing 0x" << HEXWORD << Reg[EAX].u << end();
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break;
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}
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// End Op f7 Subops
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default:
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cerr << "unrecognized subop for opcode f7: " << NUM(subop) << '\n';
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exit(1);
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}
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break;
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}
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//:
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:(before "End Initialize Op Names")
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put_new(Name_0f, "af", "multiply rm32 into r32 (imul)");
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:(scenario multiply_r32_into_r32)
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% Reg[EAX].i = 4;
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% Reg[EBX].i = 2;
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== 0x1
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# op ModR/M SIB displacement immediate
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0f af d8 # subtract EBX into EAX
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# ModR/M in binary: 11 (direct mode) 011 (src EBX) 000 (dest EAX)
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+run: multiply r/m32 into EBX
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+run: r/m32 is EAX
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+run: storing 0x00000008
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:(before "End Two-Byte Opcodes Starting With 0f")
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case 0xaf: { // multiply r32 into r/m32
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const uint8_t modrm = next();
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const uint8_t arg2 = (modrm>>3)&0x7;
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trace(90, "run") << "multiply r/m32 into " << rname(arg2) << end();
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const int32_t* arg1 = effective_address(modrm);
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BINARY_ARITHMETIC_OP(*, Reg[arg2].i, *arg1);
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break;
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}
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//:: negate
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:(scenario negate_r32)
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% Reg[EBX].i = 1;
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== 0x1
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# op ModR/M SIB displacement immediate
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f7 db # negate EBX
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# ModR/M in binary: 11 (direct mode) 011 (subop negate) 011 (dest EBX)
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+run: operate on r/m32
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+run: r/m32 is EBX
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+run: subop: negate
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+run: storing 0xffffffff
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:(before "End Op f7 Subops")
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case 3: { // negate r/m32
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trace(90, "run") << "subop: negate" << end();
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// one case that can overflow
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if (static_cast<uint32_t>(*arg1) == 0x80000000) {
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trace(90, "run") << "overflow" << end();
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SF = true;
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ZF = false;
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OF = true;
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break;
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}
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*arg1 = -(*arg1);
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trace(90, "run") << "storing 0x" << HEXWORD << *arg1 << end();
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SF = (*arg1 >> 31);
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ZF = (*arg1 == 0);
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OF = false;
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break;
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}
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:(scenario negate_can_overflow) // in exactly one situation
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% Reg[EBX].i = 0x80000000; // INT_MIN
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== 0x1
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# op ModR/M SIB displacement immediate
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f7 db # negate EBX
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# ModR/M in binary: 11 (direct mode) 011 (subop negate) 011 (dest EBX)
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+run: operate on r/m32
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+run: r/m32 is EBX
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+run: subop: negate
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+run: overflow
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//:: shift left
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:(before "End Initialize Op Names")
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put_new(Name, "d3", "shift rm32 by CL bits depending on subop (sal/sar/shl/shr)");
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:(scenario shift_left_r32_with_cl)
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% Reg[EBX].i = 13;
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% Reg[ECX].i = 1;
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== 0x1
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# op ModR/M SIB displacement immediate
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d3 e3 # negate EBX
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# ModR/M in binary: 11 (direct mode) 100 (subop shift left) 011 (dest EBX)
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+run: operate on r/m32
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+run: r/m32 is EBX
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+run: subop: shift left by CL bits
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+run: storing 0x0000001a
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:(before "End Single-Byte Opcodes")
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case 0xd3: {
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const uint8_t modrm = next();
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trace(90, "run") << "operate on r/m32" << end();
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int32_t* arg1 = effective_address(modrm);
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const uint8_t subop = (modrm>>3)&0x7; // middle 3 'reg opcode' bits
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switch (subop) {
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case 4: { // shift left r/m32 by CL
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trace(90, "run") << "subop: shift left by CL bits" << end();
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uint8_t count = Reg[ECX].u & 0x1f;
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// OF is only defined if count is 1
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if (count == 1) {
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bool msb = (*arg1 & 0x80000000) >> 1;
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bool pnsb = (*arg1 & 0x40000000);
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OF = (msb != pnsb);
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}
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*arg1 = (*arg1 << count);
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ZF = (*arg1 == 0);
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SF = (*arg1 < 0);
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trace(90, "run") << "storing 0x" << HEXWORD << *arg1 << end();
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break;
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}
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// End Op d3 Subops
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default:
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cerr << "unrecognized subop for opcode d3: " << NUM(subop) << '\n';
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exit(1);
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}
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break;
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}
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//:: shift right arithmetic
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:(scenario shift_right_arithmetic_r32_with_cl)
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% Reg[EBX].i = 26;
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% Reg[ECX].i = 1;
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== 0x1
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# op ModR/M SIB displacement immediate
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d3 fb # negate EBX
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# ModR/M in binary: 11 (direct mode) 111 (subop shift right arithmetic) 011 (dest EBX)
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+run: operate on r/m32
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+run: r/m32 is EBX
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+run: subop: shift right by CL bits, while preserving sign
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+run: storing 0x0000000d
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:(before "End Op d3 Subops")
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case 7: { // shift right r/m32 by CL, preserving sign
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trace(90, "run") << "subop: shift right by CL bits, while preserving sign" << end();
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uint8_t count = Reg[ECX].u & 0x1f;
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*arg1 = (*arg1 >> count);
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ZF = (*arg1 == 0);
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SF = (*arg1 < 0);
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// OF is only defined if count is 1
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if (count == 1) OF = false;
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trace(90, "run") << "storing 0x" << HEXWORD << *arg1 << end();
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break;
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}
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:(scenario shift_right_arithmetic_odd_r32_with_cl)
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% Reg[EBX].i = 27;
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% Reg[ECX].i = 1;
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== 0x1
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# op ModR/M SIB displacement immediate
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d3 fb # negate EBX
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# ModR/M in binary: 11 (direct mode) 111 (subop shift right arithmetic) 011 (dest EBX)
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+run: operate on r/m32
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+run: r/m32 is EBX
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+run: subop: shift right by CL bits, while preserving sign
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# result: 13
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+run: storing 0x0000000d
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:(scenario shift_right_arithmetic_negative_r32_with_cl)
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% Reg[EBX].i = 0xfffffffd; // -3
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% Reg[ECX].i = 1;
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== 0x1
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# op ModR/M SIB displacement immediate
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d3 fb # negate EBX
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# ModR/M in binary: 11 (direct mode) 111 (subop shift right arithmetic) 011 (dest EBX)
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+run: operate on r/m32
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+run: r/m32 is EBX
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+run: subop: shift right by CL bits, while preserving sign
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# result: -2
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+run: storing 0xfffffffe
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//:: shift right logical
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:(scenario shift_right_logical_r32_with_cl)
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% Reg[EBX].i = 26;
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% Reg[ECX].i = 1;
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== 0x1
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# op ModR/M SIB displacement immediate
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d3 eb # negate EBX
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# ModR/M in binary: 11 (direct mode) 101 (subop shift right logical) 011 (dest EBX)
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+run: operate on r/m32
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+run: r/m32 is EBX
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+run: subop: shift right by CL bits, while padding zeroes
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+run: storing 0x0000000d
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:(before "End Op d3 Subops")
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case 5: { // shift right r/m32 by CL, preserving sign
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trace(90, "run") << "subop: shift right by CL bits, while padding zeroes" << end();
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uint8_t count = Reg[ECX].u & 0x1f;
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// OF is only defined if count is 1
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if (count == 1) {
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bool msb = (*arg1 & 0x80000000) >> 1;
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bool pnsb = (*arg1 & 0x40000000);
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OF = (msb != pnsb);
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}
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uint32_t* uarg1 = reinterpret_cast<uint32_t*>(arg1);
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*uarg1 = (*uarg1 >> count);
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ZF = (*uarg1 == 0);
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// result is always positive by definition
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SF = false;
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trace(90, "run") << "storing 0x" << HEXWORD << *arg1 << end();
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break;
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}
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:(scenario shift_right_logical_odd_r32_with_cl)
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% Reg[EBX].i = 27;
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% Reg[ECX].i = 1;
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== 0x1
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# op ModR/M SIB displacement immediate
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d3 eb # negate EBX
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# ModR/M in binary: 11 (direct mode) 101 (subop shift right logical) 011 (dest EBX)
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+run: operate on r/m32
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+run: r/m32 is EBX
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+run: subop: shift right by CL bits, while padding zeroes
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# result: 13
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+run: storing 0x0000000d
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:(scenario shift_right_logical_negative_r32_with_cl)
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% Reg[EBX].i = 0xfffffffd;
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% Reg[ECX].i = 1;
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== 0x1
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# op ModR/M SIB displacement immediate
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d3 eb # negate EBX
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# ModR/M in binary: 11 (direct mode) 101 (subop shift right logical) 011 (dest EBX)
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+run: operate on r/m32
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+run: r/m32 is EBX
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+run: subop: shift right by CL bits, while padding zeroes
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+run: storing 0x7ffffffe
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//:: and
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:(before "End Initialize Op Names")
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put_new(Name, "21", "rm32 = bitwise AND of r32 with rm32 (and)");
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:(scenario and_r32_with_r32)
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% Reg[EAX].i = 0x0a0b0c0d;
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% Reg[EBX].i = 0x000000ff;
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== 0x1
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# op ModR/M SIB displacement immediate
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21 d8 # and EBX with destination EAX
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# ModR/M in binary: 11 (direct mode) 011 (src EBX) 000 (dest EAX)
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+run: and EBX with r/m32
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+run: r/m32 is EAX
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+run: storing 0x0000000d
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:(before "End Single-Byte Opcodes")
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case 0x21: { // and r32 with r/m32
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const uint8_t modrm = next();
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const uint8_t arg2 = (modrm>>3)&0x7;
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trace(90, "run") << "and " << rname(arg2) << " with r/m32" << end();
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int32_t* arg1 = effective_address(modrm);
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BINARY_BITWISE_OP(&, *arg1, Reg[arg2].u);
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break;
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}
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//:: or
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:(before "End Initialize Op Names")
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put_new(Name, "09", "rm32 = bitwise OR of r32 with rm32 (or)");
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:(scenario or_r32_with_r32)
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% Reg[EAX].i = 0x0a0b0c0d;
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% Reg[EBX].i = 0xa0b0c0d0;
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== 0x1
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# op ModR/M SIB displacement immediate
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09 d8 # or EBX with destination EAX
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# ModR/M in binary: 11 (direct mode) 011 (src EBX) 000 (dest EAX)
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+run: or EBX with r/m32
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+run: r/m32 is EAX
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+run: storing 0xaabbccdd
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:(before "End Single-Byte Opcodes")
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case 0x09: { // or r32 with r/m32
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const uint8_t modrm = next();
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const uint8_t arg2 = (modrm>>3)&0x7;
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trace(90, "run") << "or " << rname(arg2) << " with r/m32" << end();
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int32_t* arg1 = effective_address(modrm);
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BINARY_BITWISE_OP(|, *arg1, Reg[arg2].u);
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break;
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}
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//:: xor
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:(before "End Initialize Op Names")
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put_new(Name, "31", "rm32 = bitwise XOR of r32 with rm32 (xor)");
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:(scenario xor_r32_with_r32)
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% Reg[EAX].i = 0x0a0b0c0d;
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% Reg[EBX].i = 0xaabbc0d0;
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== 0x1
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# op ModR/M SIB displacement immediate
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31 d8 # xor EBX with destination EAX
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# ModR/M in binary: 11 (direct mode) 011 (src EBX) 000 (dest EAX)
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+run: xor EBX with r/m32
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+run: r/m32 is EAX
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+run: storing 0xa0b0ccdd
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:(before "End Single-Byte Opcodes")
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case 0x31: { // xor r32 with r/m32
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const uint8_t modrm = next();
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const uint8_t arg2 = (modrm>>3)&0x7;
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trace(90, "run") << "xor " << rname(arg2) << " with r/m32" << end();
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int32_t* arg1 = effective_address(modrm);
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BINARY_BITWISE_OP(^, *arg1, Reg[arg2].u);
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break;
|
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}
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//:: not
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|
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:(scenario not_r32)
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% Reg[EBX].i = 0x0f0f00ff;
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== 0x1
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# op ModR/M SIB displacement immediate
|
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f7 d3 # not EBX
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# ModR/M in binary: 11 (direct mode) 010 (subop not) 011 (dest EBX)
|
|
+run: operate on r/m32
|
|
+run: r/m32 is EBX
|
|
+run: subop: not
|
|
+run: storing 0xf0f0ff00
|
|
|
|
:(before "End Op f7 Subops")
|
|
case 2: { // not r/m32
|
|
trace(90, "run") << "subop: not" << end();
|
|
*arg1 = ~(*arg1);
|
|
trace(90, "run") << "storing 0x" << HEXWORD << *arg1 << end();
|
|
SF = (*arg1 >> 31);
|
|
ZF = (*arg1 == 0);
|
|
OF = false;
|
|
break;
|
|
}
|
|
|
|
//:: compare (cmp)
|
|
|
|
:(before "End Initialize Op Names")
|
|
put_new(Name, "39", "compare: set SF if rm32 < r32 (cmp)");
|
|
|
|
:(scenario compare_r32_with_r32_greater)
|
|
% Reg[EAX].i = 0x0a0b0c0d;
|
|
% Reg[EBX].i = 0x0a0b0c07;
|
|
== 0x1
|
|
# op ModR/M SIB displacement immediate
|
|
39 d8 # compare EBX with EAX
|
|
# ModR/M in binary: 11 (direct mode) 011 (src EBX) 000 (dest EAX)
|
|
+run: compare EBX with r/m32
|
|
+run: r/m32 is EAX
|
|
+run: SF=0; ZF=0; OF=0
|
|
|
|
:(before "End Single-Byte Opcodes")
|
|
case 0x39: { // set SF if r/m32 < r32
|
|
const uint8_t modrm = next();
|
|
const uint8_t reg2 = (modrm>>3)&0x7;
|
|
trace(90, "run") << "compare " << rname(reg2) << " with r/m32" << end();
|
|
const int32_t* arg1 = effective_address(modrm);
|
|
const int32_t arg2 = Reg[reg2].i;
|
|
const int32_t tmp1 = *arg1 - arg2;
|
|
SF = (tmp1 < 0);
|
|
ZF = (tmp1 == 0);
|
|
const int64_t tmp2 = *arg1 - arg2;
|
|
OF = (tmp1 != tmp2);
|
|
trace(90, "run") << "SF=" << SF << "; ZF=" << ZF << "; OF=" << OF << end();
|
|
break;
|
|
}
|
|
|
|
:(scenario compare_r32_with_r32_lesser)
|
|
% Reg[EAX].i = 0x0a0b0c07;
|
|
% Reg[EBX].i = 0x0a0b0c0d;
|
|
== 0x1
|
|
# op ModR/M SIB displacement immediate
|
|
39 d8 # compare EBX with EAX
|
|
# ModR/M in binary: 11 (direct mode) 011 (src EBX) 000 (dest EAX)
|
|
+run: compare EBX with r/m32
|
|
+run: r/m32 is EAX
|
|
+run: SF=1; ZF=0; OF=0
|
|
|
|
:(scenario compare_r32_with_r32_equal)
|
|
% Reg[EAX].i = 0x0a0b0c0d;
|
|
% Reg[EBX].i = 0x0a0b0c0d;
|
|
== 0x1
|
|
# op ModR/M SIB displacement immediate
|
|
39 d8 # compare EBX with EAX
|
|
# ModR/M in binary: 11 (direct mode) 011 (src EBX) 000 (dest EAX)
|
|
+run: compare EBX with r/m32
|
|
+run: r/m32 is EAX
|
|
+run: SF=0; ZF=1; OF=0
|
|
|
|
//:: copy (mov)
|
|
|
|
:(before "End Initialize Op Names")
|
|
put_new(Name, "89", "copy r32 to rm32 (mov)");
|
|
|
|
:(scenario copy_r32_to_r32)
|
|
% Reg[EBX].i = 0xaf;
|
|
== 0x1
|
|
# op ModR/M SIB displacement immediate
|
|
89 d8 # copy EBX to EAX
|
|
# ModR/M in binary: 11 (direct mode) 011 (src EBX) 000 (dest EAX)
|
|
+run: copy EBX to r/m32
|
|
+run: r/m32 is EAX
|
|
+run: storing 0x000000af
|
|
|
|
:(before "End Single-Byte Opcodes")
|
|
case 0x89: { // copy r32 to r/m32
|
|
const uint8_t modrm = next();
|
|
const uint8_t rsrc = (modrm>>3)&0x7;
|
|
trace(90, "run") << "copy " << rname(rsrc) << " to r/m32" << end();
|
|
int32_t* dest = effective_address(modrm);
|
|
*dest = Reg[rsrc].i;
|
|
trace(90, "run") << "storing 0x" << HEXWORD << *dest << end();
|
|
break;
|
|
}
|
|
|
|
//:: xchg
|
|
|
|
:(before "End Initialize Op Names")
|
|
put_new(Name, "87", "swap the contents of r32 and rm32 (xchg)");
|
|
|
|
:(scenario xchg_r32_with_r32)
|
|
% Reg[EBX].i = 0xaf;
|
|
% Reg[EAX].i = 0x2e;
|
|
== 0x1
|
|
# op ModR/M SIB displacement immediate
|
|
87 d8 # exchange EBX with EAX
|
|
# ModR/M in binary: 11 (direct mode) 011 (src EBX) 000 (dest EAX)
|
|
+run: exchange EBX with r/m32
|
|
+run: r/m32 is EAX
|
|
+run: storing 0x000000af in r/m32
|
|
+run: storing 0x0000002e in EBX
|
|
|
|
:(before "End Single-Byte Opcodes")
|
|
case 0x87: { // exchange r32 with r/m32
|
|
const uint8_t modrm = next();
|
|
const uint8_t reg2 = (modrm>>3)&0x7;
|
|
trace(90, "run") << "exchange " << rname(reg2) << " with r/m32" << end();
|
|
int32_t* arg1 = effective_address(modrm);
|
|
const int32_t tmp = *arg1;
|
|
*arg1 = Reg[reg2].i;
|
|
Reg[reg2].i = tmp;
|
|
trace(90, "run") << "storing 0x" << HEXWORD << *arg1 << " in r/m32" << end();
|
|
trace(90, "run") << "storing 0x" << HEXWORD << Reg[reg2].i << " in " << rname(reg2) << end();
|
|
break;
|
|
}
|
|
|
|
//:: increment
|
|
|
|
:(before "End Initialize Op Names")
|
|
put_new(Name, "40", "increment EAX (inc)");
|
|
put_new(Name, "41", "increment ECX (inc)");
|
|
put_new(Name, "42", "increment EDX (inc)");
|
|
put_new(Name, "43", "increment EBX (inc)");
|
|
put_new(Name, "44", "increment ESP (inc)");
|
|
put_new(Name, "45", "increment EBP (inc)");
|
|
put_new(Name, "46", "increment ESI (inc)");
|
|
put_new(Name, "47", "increment EDI (inc)");
|
|
|
|
:(scenario increment_r32)
|
|
% Reg[ECX].u = 0x1f;
|
|
== 0x1 # code segment
|
|
# op ModR/M SIB displacement immediate
|
|
41 # increment ECX
|
|
+run: increment ECX
|
|
+run: storing value 0x00000020
|
|
|
|
:(before "End Single-Byte Opcodes")
|
|
case 0x40:
|
|
case 0x41:
|
|
case 0x42:
|
|
case 0x43:
|
|
case 0x44:
|
|
case 0x45:
|
|
case 0x46:
|
|
case 0x47: { // increment r32
|
|
const uint8_t reg = op & 0x7;
|
|
trace(90, "run") << "increment " << rname(reg) << end();
|
|
++Reg[reg].u;
|
|
trace(90, "run") << "storing value 0x" << HEXWORD << Reg[reg].u << end();
|
|
break;
|
|
}
|
|
|
|
:(before "End Initialize Op Names")
|
|
put_new(Name, "ff", "increment/decrement/jump/push/call rm32 based on subop (inc/dec/jmp/push/call)");
|
|
|
|
:(scenario increment_rm32)
|
|
% Reg[EAX].u = 0x20;
|
|
== 0x1 # code segment
|
|
# op ModR/M SIB displacement immediate
|
|
ff c0 # increment EAX
|
|
# ModR/M in binary: 11 (direct mode) 000 (subop inc) 000 (EAX)
|
|
+run: increment r/m32
|
|
+run: r/m32 is EAX
|
|
+run: storing value 0x00000021
|
|
|
|
:(before "End Single-Byte Opcodes")
|
|
case 0xff: {
|
|
const uint8_t modrm = next();
|
|
const uint8_t subop = (modrm>>3)&0x7; // middle 3 'reg opcode' bits
|
|
switch (subop) {
|
|
case 0: { // increment r/m32
|
|
trace(90, "run") << "increment r/m32" << end();
|
|
int32_t* arg = effective_address(modrm);
|
|
++*arg;
|
|
trace(90, "run") << "storing value 0x" << HEXWORD << *arg << end();
|
|
break;
|
|
}
|
|
default:
|
|
cerr << "unrecognized subop for ff: " << HEXBYTE << NUM(subop) << '\n';
|
|
DUMP("");
|
|
exit(1);
|
|
// End Op ff Subops
|
|
}
|
|
break;
|
|
}
|
|
|
|
//:: decrement
|
|
|
|
:(before "End Initialize Op Names")
|
|
put_new(Name, "48", "decrement EAX (dec)");
|
|
put_new(Name, "49", "decrement ECX (dec)");
|
|
put_new(Name, "4a", "decrement EDX (dec)");
|
|
put_new(Name, "4b", "decrement EBX (dec)");
|
|
put_new(Name, "4c", "decrement ESP (dec)");
|
|
put_new(Name, "4d", "decrement EBP (dec)");
|
|
put_new(Name, "4e", "decrement ESI (dec)");
|
|
put_new(Name, "4f", "decrement EDI (dec)");
|
|
|
|
:(scenario decrement_r32)
|
|
% Reg[ECX].u = 0x1f;
|
|
== 0x1 # code segment
|
|
# op ModR/M SIB displacement immediate
|
|
49 # decrement ECX
|
|
+run: decrement ECX
|
|
+run: storing value 0x0000001e
|
|
|
|
:(before "End Single-Byte Opcodes")
|
|
case 0x48:
|
|
case 0x49:
|
|
case 0x4a:
|
|
case 0x4b:
|
|
case 0x4c:
|
|
case 0x4d:
|
|
case 0x4e:
|
|
case 0x4f: { // decrement r32
|
|
const uint8_t reg = op & 0x7;
|
|
trace(90, "run") << "decrement " << rname(reg) << end();
|
|
--Reg[reg].u;
|
|
trace(90, "run") << "storing value 0x" << HEXWORD << Reg[reg].u << end();
|
|
break;
|
|
}
|
|
|
|
:(scenario decrement_rm32)
|
|
% Reg[EAX].u = 0x20;
|
|
== 0x1 # code segment
|
|
# op ModR/M SIB displacement immediate
|
|
ff c8 # decrement EAX
|
|
# ModR/M in binary: 11 (direct mode) 001 (subop inc) 000 (EAX)
|
|
+run: decrement r/m32
|
|
+run: r/m32 is EAX
|
|
+run: storing value 0x0000001f
|
|
|
|
:(before "End Op ff Subops")
|
|
case 1: { // decrement r/m32
|
|
trace(90, "run") << "decrement r/m32" << end();
|
|
int32_t* arg = effective_address(modrm);
|
|
--*arg;
|
|
trace(90, "run") << "storing value 0x" << HEXWORD << *arg << end();
|
|
break;
|
|
}
|
|
|
|
//:: push
|
|
|
|
:(before "End Initialize Op Names")
|
|
put_new(Name, "50", "push EAX to stack (push)");
|
|
put_new(Name, "51", "push ECX to stack (push)");
|
|
put_new(Name, "52", "push EDX to stack (push)");
|
|
put_new(Name, "53", "push EBX to stack (push)");
|
|
put_new(Name, "54", "push ESP to stack (push)");
|
|
put_new(Name, "55", "push EBP to stack (push)");
|
|
put_new(Name, "56", "push ESI to stack (push)");
|
|
put_new(Name, "57", "push EDI to stack (push)");
|
|
|
|
:(scenario push_r32)
|
|
% Reg[ESP].u = 0x64;
|
|
% Reg[EBX].i = 0x0000000a;
|
|
== 0x1
|
|
# op ModR/M SIB displacement immediate
|
|
53 # push EBX to stack
|
|
+run: push EBX
|
|
+run: decrementing ESP to 0x00000060
|
|
+run: pushing value 0x0000000a
|
|
|
|
:(before "End Single-Byte Opcodes")
|
|
case 0x50:
|
|
case 0x51:
|
|
case 0x52:
|
|
case 0x53:
|
|
case 0x54:
|
|
case 0x55:
|
|
case 0x56:
|
|
case 0x57: { // push r32 to stack
|
|
uint8_t reg = op & 0x7;
|
|
trace(90, "run") << "push " << rname(reg) << end();
|
|
//? cerr << "push: " << NUM(reg) << ": " << Reg[reg].u << " => " << Reg[ESP].u << '\n';
|
|
push(Reg[reg].u);
|
|
break;
|
|
}
|
|
|
|
//:: pop
|
|
|
|
:(before "End Initialize Op Names")
|
|
put_new(Name, "58", "pop top of stack to EAX (pop)");
|
|
put_new(Name, "59", "pop top of stack to ECX (pop)");
|
|
put_new(Name, "5a", "pop top of stack to EDX (pop)");
|
|
put_new(Name, "5b", "pop top of stack to EBX (pop)");
|
|
put_new(Name, "5c", "pop top of stack to ESP (pop)");
|
|
put_new(Name, "5d", "pop top of stack to EBP (pop)");
|
|
put_new(Name, "5e", "pop top of stack to ESI (pop)");
|
|
put_new(Name, "5f", "pop top of stack to EDI (pop)");
|
|
|
|
:(scenario pop_r32)
|
|
% Reg[ESP].u = 0x02000000;
|
|
% Mem.push_back(vma(0x02000000)); // manually allocate memory
|
|
% write_mem_i32(0x02000000, 0x0000000a); // ..before this write
|
|
== 0x1 # code segment
|
|
# op ModR/M SIB displacement immediate
|
|
5b # pop stack to EBX
|
|
== 0x2000 # data segment
|
|
0a 00 00 00 # 0x0a
|
|
+run: pop into EBX
|
|
+run: popping value 0x0000000a
|
|
+run: incrementing ESP to 0x02000004
|
|
|
|
:(before "End Single-Byte Opcodes")
|
|
case 0x58:
|
|
case 0x59:
|
|
case 0x5a:
|
|
case 0x5b:
|
|
case 0x5c:
|
|
case 0x5d:
|
|
case 0x5e:
|
|
case 0x5f: { // pop stack into r32
|
|
const uint8_t reg = op & 0x7;
|
|
trace(90, "run") << "pop into " << rname(reg) << end();
|
|
//? cerr << "pop from " << Reg[ESP].u << '\n';
|
|
Reg[reg].u = pop();
|
|
//? cerr << "=> " << NUM(reg) << ": " << Reg[reg].u << '\n';
|
|
break;
|
|
}
|
|
:(code)
|
|
uint32_t pop() {
|
|
const uint32_t result = read_mem_u32(Reg[ESP].u);
|
|
trace(90, "run") << "popping value 0x" << HEXWORD << result << end();
|
|
Reg[ESP].u += 4;
|
|
trace(90, "run") << "incrementing ESP to 0x" << HEXWORD << Reg[ESP].u << end();
|
|
return result;
|
|
}
|