various
This commit is contained in:
parent
c800042ddb
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MODULE main
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VAR
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x: boolean;
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r: boolean;
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-- The DEFINE block doesn't really matter?
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DEFINE
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y := !(x xor r);
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ASSIGN
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init(r) := FALSE;
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next(r) := x xor r;
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-- NuSMV -int five.smv
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-- go
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-- State of system depends only on the variables in the VAR block
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MODULE main
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VAR
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in1: boolean;
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in2: boolean;
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DEFINE
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-- no delay
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out := !(in1 & in2);
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-- no ASSIGN block => all possible transitions
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-- NuSMV > print_reachable_states -v
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-- ######################################################################
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-- system diameter: 1
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-- reachable states: 4 (2^2) out of 4 (2^2)
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-- ------- State 1 ------
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-- in1 = TRUE
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-- in2 = TRUE
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-- ------- State 2 ------
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-- in1 = TRUE
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-- in2 = FALSE
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-- ------- State 3 ------
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-- in1 = FALSE
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-- in2 = TRUE
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-- ------- State 4 ------
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-- in1 = FALSE
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-- in2 = FALSE
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-- -------------------------
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-- ######################################################################
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MODULE main
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VAR
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in1: boolean;
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in2: boolean;
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out: boolean;
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-- 8 total states now since there are 3 inputs
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ASSIGN
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-- a unit delay is there.
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init(out) := TRUE;
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next(out) := !(in1 & in2);
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MODULE main
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VAR
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main_in1: boolean;
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main_in2: boolean;
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q: nand2(main_in1, main_in2);
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MODULE nand2(nand_in1, nand_in2)
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VAR
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out: boolean;
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ASSIGN
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-- a unit delay is here
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init(out) := TRUE;
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next(out) := !(nand_in1 & nand_in2);
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MODULE main
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VAR
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main_x1: boolean;
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main_x2: boolean;
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main_y1: boolean;
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main_y2: boolean;
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main_q1: cust_nand(main_x1, main_x2);
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main_q2: cust_nand(main_y1, main_y2);
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DEFINE
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-- no delay
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main_out := main_q1.nand_out xor main_q2.nand_out;
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MODULE cust_nand(nand_in1, nand_in2)
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VAR
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nand_out: boolean;
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ASSIGN
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-- unit time delay
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init(nand_out) := TRUE;
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next(nand_out) := !(nand_in1 & nand_in2);
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-- There are 64 states because there are 6 states:
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- main_x1
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- main_x2
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- main_y1
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- main_y2
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- main_q1.out
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- main_q2.out
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MODULE main
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VAR
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location: {l1,l2};
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ASSIGN
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init(location) := l1;
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next(location) := case
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(location = l1) : l2;
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(location = l2) : l1;
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esac;
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MODULE main
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VAR
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request: boolean;
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status: {ready, busy}; -- an enum
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ASSIGN
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init(status) := ready;
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-- init of request not mentioned => 2 * states
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next(status) := case
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request: busy;
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TRUE: {ready, busy}; -- can go anywhere
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esac;
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-- NuSMV > check_ltlspec -p "G(request=FALSE)"
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-- -- specification G request = FALSE is false
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-- -- as demonstrated by the following execution sequence
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-- Trace Description: LTL Counterexample
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-- Trace Type: Counterexample
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-- -> State: 1.1 <-
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-- request = TRUE
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-- status = ready
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-- -- Loop starts here
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-- -> State: 1.2 <-
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-- request = FALSE
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-- status = busy
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-- -> State: 1.3 <-
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-- NuSMV > check_ltlspec -p "F(request=TRUE)"
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-- -- specification F request = TRUE is false
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-- -- as demonstrated by the following execution sequence
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-- Trace Description: LTL Counterexample
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-- Trace Type: Counterexample
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-- -- Loop starts here
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-- -> State: 1.1 <-
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-- request = FALSE
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-- status = ready
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-- -> State: 1.2 <-
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-- Combining G and F
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-- NuSMV > check_ltlspec -p "G(request=TRUE -> F(status=busy) )"
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-- -- specification G (request = TRUE -> F status = busy) is true
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MODULE main
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VAR
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location: {l1, l2};
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x: 0 .. 100; -- only bounded integers
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ASSIGN
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init(location) := l1;
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init(x) := 0;
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next(location) := case
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(location = l1) & (x < 10): l2;
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(location = l2): l1;
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TRUE: location; -- no change (like an else clause)
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esac;
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next(x) := case
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--(location = l1): x;
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(location = l2) & (x < 100): x + 1;
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TRUE: x;
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esac;
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-- NuSMV -int
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-- read_model -i <in.smv>
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-- flatten_hierarchy
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-- encode_variables
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-- build_model
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--
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-- pick_state -i
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-- simulate -i -k 15
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-- print_reachable_states -v
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-- NuSMV > check_ltlspec -p "G(x>=0)"
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-- -- specification G x >= 0 is true
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-- NuSMV > check_ltlspec -p "F(x>=5)"
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-- -- specification F x >= 5 is true
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/*
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Ripple carry adder.
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Carry out of previous fulladder is given as carry in of next fulladder
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*/
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// Behavioural
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module adder(S, Cy, A, B, C);
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input A, B, C;
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output S, Cy;
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assign S = A ^ B ^ C;
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assign Cy = (A & B) | (B & C) | (A & C);
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endmodule
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/* Structural definition. */
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// netlist.
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// Can be specified at different levels
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// Each successive level reveals more details
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// A 4-bit ripple carry adder
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// Consists of 4 full adders
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// Each full adder has circuits for sum and carry.
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module sum (sum, a, b, cy_in);
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input a, b, cy_in;
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output sum;
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wire t;
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xor x1 (t, a, b)
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xor x2 (sum, cy_in, t)
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endmodule
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module carry (cy_out, a, b, cy_in);
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input a, b, cy_in;
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output cy_out;
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wire t1, t2, t3;
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and g1 (t1, a, b) ;
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and g2 (t2, b, c) ;
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and g3 (t3, a, c) ;
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or g4 (cy_out, t1, t2, t3);
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endmodule
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module add (cy_out, sum, a, b, cy_in);
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input a, b, cy_in;
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output sum, cy_out;
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sum s1 (sum, a, b, cy_in);
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carry c1 (cy_out, a, b, cy_in);
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endmodule
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primitive add4 (s, cy4, cy_in, x, y);
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input [3:0] x, y; // a vector. A 4-bit number here.
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input cy_in;
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output s, cy4;
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// Instantiating the constituent full adders
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add
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/*
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primitive sum(S, A, B, C);
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input A, B, C;
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output S;
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table
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0 0 0 : 0;
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0 0 1 : 1;
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0 1 0 : 1;
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0 1 1 : 0;
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1 0 0 : 1;
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1 0 1 : 0;
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1 1 0 : 0;
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1 1 1 : 1;
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endtable
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endprimitive
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primitive carry(Cy, A, B, C);
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input A, B, C;
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output Cy;
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table
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1 1 ? : 1;
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1 ? 1 : 1;
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? 1 1 : 1;
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0 0 ? : 0;
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? 0 0 : 0;
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0 ? 0 : 0;
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endtable
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endprimitive
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*/
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module testbench;
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// Instantiating the 'args' of the module being tested
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reg A, B, C, D, E, F; // LHS vars
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wire Y; // RHS vars
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example DUT(A, B, C, D, E, F, Y);
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// initial block will be executed only once
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initial
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begin
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// Following two lines for gtkwave
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$dumpfile ("example.vcd"); // vcd: Value Change Dump
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$dumpvars (0, testbench); // 0 means all the variables in the
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// testbench module
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// Monitor these variables. When any of them changes, 'print'.
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// $time: simulation time
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// %b: bit
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$monitor ($time, "A=%b, B=%b, C=%b, D=%b, E=%b, F=%b, Y=%b",
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A, B, C, D, E, F, Y);
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#5 A=1; B=0; C=0; D=1; E=0; F=0; // wait time 5 units and apply these
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// values
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#5 A=0; B=0; C=1; D=1; E=0; F=0;
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#5 A=1; C=0;
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#5 F=1;
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#5 $finish;
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end
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endmodule
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/*
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As described in https://nptel.ac.in/courses/106/105/106105165/
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*/
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// A structural netlist
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module example (A, B, C, D, E, F, Y);
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input A, B, C, D, E, F;
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output Y;
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wire t1, t2, t3, Y; // Y here is not mandatory
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// # denotes delay in seconds
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nand #1 G1 (t1, A, B);
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and #2 G2 (t2, C, ~B, D); // ~ means NOT
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nor #1 G3 (t3, E, F);
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nand #1 G4 (Y, t1, t2, t3);
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// We used two NAND gates above. We could merge the two statements like:
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// nand #1 G1 (t1, A, B), // comma here
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// G4 (Y, t1, t2, t3);
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endmodule
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module simpleand (f, x, y);
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input x, y;
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output f;
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assign f = x & y;
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endmodule
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module testbench;
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reg f, x, y;
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simpleand DUT(f, x, y);
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initial
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begin
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$dumpfile ("simpleand.vcd");
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$dumpvars (0, testbench);
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$monitor ($time, "f=%b, x=%b, y=%b", f, x, y);
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#1 x=0; y=0;
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#3 x=0; y=1;
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#3 x=1; y=0;
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#3 x=1; y=1;
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#3 $finish;
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end
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endmodule
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/*
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-------\
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x -->-| |
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| |-----> f
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y -->-| |
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-------/
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*/
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module testbench;
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reg a, b, c, d, e, f;
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endmodule
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module two_level(a, b, c, d, e, f);
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input a, b, c, d, e;
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output f;
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wire t1, t2; // nets
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assign t1 = a & b;
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assign t2 = ~(c | d);
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assign f = ~(t1 & t2);
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endmodule
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/* Two level design
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|----\
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a ---| |
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| AND |--- t1 ---|----\
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b ---| | | |
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|----/ | |
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|NAND |--- f
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|----\ | |
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c ---| | | |
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| NOR |--- t2 ---| |
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| | |----/
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d ---|----/
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*/
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/*
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|----\
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a ------------------| |
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| & |--- t1 ---|----\
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b ------------------| | | |
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|----/ | | |---|
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| & |--- (t1 & t2) ---| ~ |--- ~(t1 & t2)
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|---| |----\ | | |---|
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c ---| ~ |--- ~c ---| | | |
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|---| | | |--- t2 ---| |
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| | |----/
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d ------------------|----/
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*/
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// Behavioural
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module carry(S, Cy, A, B, C);
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input A, B, C;
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output S, Cy;
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assign S = A ^ B ^ C;
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assign Cy = (A & B) | (B & C) | (A & C);
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endmodule
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/*
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primitive sum(S, A, B, C);
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input A, B, C;
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output S;
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table
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0 0 0 : 0;
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0 0 1 : 1;
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0 1 0 : 1;
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0 1 1 : 0;
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1 0 0 : 1;
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1 0 1 : 0;
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1 1 0 : 0;
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1 1 1 : 1;
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endtable
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endprimitive
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primitive carry(Cy, A, B, C);
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input A, B, C;
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output Cy;
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table
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1 1 ? : 1;
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1 ? 1 : 1;
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? 1 1 : 1;
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0 0 ? : 0;
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? 0 0 : 0;
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0 ? 0 : 0;
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endtable
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endprimitive
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*/
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// A partial version of the physical description of a 4 bit adder
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// polysilicon: a high-purity form of silicon. Used in solar cells as well.
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// Basically the components are some polygons (mostly rectangles??)
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module add4;
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input x[3:0], y[3:0], cy_in;
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output s[3:0], cy4;
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boundary [0, 0, 130, 500]; // coordinates
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port x[0] aluminium width=1 origin=[0, 35];
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port y[0] aluminium width=1 origin=[0, 85];
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port cy_in polysilicon width=2 origin=[70, 0];
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port s[0] aluminium width=1 origin=[120, 65];
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add a0 origin = [0, 0];
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add a1 origin = [0, 120];
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endmodule
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// Structural definition.
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// netlist.
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// Can be specified at different levels
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// Each successive level reveals more details
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// A 4-bit ripple carry adder
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// Consists of 4 full adders
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// Each full adder has circuits for sum and carry.
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module sum (sum, a, b, cy_in);
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input a, b, cy_in;
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output sum;
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wire t;
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xor x1 (t, a, b)
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xor x2 (sum, cy_in, t)
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endmodule
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module carry (cy_out, a, b, cy_in);
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input a, b, cy_in;
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output cy_out;
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wire t1, t2, t3;
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and g1 (t1, a, b) ;
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and g2 (t2, b, c) ;
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and g3 (t3, a, c) ;
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or g4 (cy_out, t1, t2, t3);
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endmodule
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module add (cy_out, sum, a, b, cy_in);
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input a, b, cy_in;
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output sum, cy_out;
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sum s1 (sum, a, b, cy_in);
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carry c1 (cy_out, a, b, cy_in);
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endmodule
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primitive add4 (s, cy4, cy_in, x, y);
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input [3:0] x, y; // a vector. A 4-bit number here.
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input cy_in;
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output s, cy4;
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// Instantiating the constituent full adders
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add
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