[vhdl] old files

pvs/README.org

@@ -0,0 +1,17 @@
+#+TITLE: PVS (theorem prover)
+
+ - socrates-mortal.pvs: 'Socrates is mortal'
+ - sum-n.pvs: Sum of first n natural numbers
+ - sum-n3.pvs: Sum of first n natural number squares
+
+#booleans.pvs
+#fadder.pvs
+#fnofix.pvs
+#mybaby.pvs
+#mybaby-re.pvs
+#mybabyv2.pvs
+#mybabyv3-nonnarcissist.pvs
+#one.pvs
+#prop_logic.pvs
+#sum-tut.pvs
+

vhdl/2b-down-counter/Makefile

@@ -0,0 +1,22 @@
+NAME = ctr
+
+build: $(NAME).vhdl $(NAME)-tb.vhdl
+	ghdl -a --std=08 $(NAME).vhdl
+	ghdl -a --std=08 $(NAME)-tb.vhdl
+	ghdl -e --std=08 ent_$(NAME)_tb
+#	/home/famubu/Downloads/ghdl-2.0.0/ghdl_mcode -a $(NAME).vhdl
+#	/home/famubu/Downloads/ghdl-2.0.0/ghdl_mcode -e ent_$(NAME)
+#	/home/famubu/Downloads/ghdl-2.0.0/ghdl_mcode -a $(NAME)-tb.vhdl
+#	/home/famubu/Downloads/ghdl-2.0.0/ghdl_mcode -e ent_$(NAME)_tb
+
+PHONY: sim clean
+
+clean:
+	rm -rf dump.vcd *.cf
+
+sim:
+	ghdl -r --std=08 ent_$(NAME)_tb --vcd=dump.vcd --stop-time=500ns
+	#/home/famubu/Downloads/ghdl-2.0.0/ghdl_mcode -r ent_$(NAME)_tb --vcd=dump.vcd --stop-time=100ns
+
+vcd: dump.vcd
+	~/Downloads/vcd-x86_64-linux-gnu-220131 < dump.vcd

vhdl/2b-down-counter/ctr-tb.vhdl

@@ -0,0 +1,91 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity ent_ctr_tb is
+end entity ent_ctr_tb;
+
+architecture arch_ent_ctr_tb of ent_ctr_tb is
+  signal t_clk  : std_logic := '0';
+  signal t_en   : std_logic := '0';
+  signal t_load : std_logic;
+  signal t_data : std_logic_vector(1 downto 0);
+  signal t_q    : std_logic_vector(1 downto 0);
+  constant CLOCK : integer := 20;
+begin
+  t_ctr: entity work.ent_ctr port map(
+    t_clk, t_en, t_load, t_data, t_q
+  );
+
+  t_clk <= not t_clk after 10 ns;
+
+  process
+  begin
+    -- Initialize
+    t_load <= '1';
+    t_data <= "11";
+    wait for 20 ns;
+
+    t_load <= '0';
+    t_en   <= '1';
+    assert t_q = "11"
+      report "Test Failed: " & to_string(t_q) & " != 11"
+      severity error;
+    --report to_string(t_q);
+    wait for 20 ns;
+
+    --report to_string(t_q);
+    assert t_q = "10"
+      report "Test Failed: " & to_string(t_q) & " != 10"
+      severity error;
+    wait for 20 ns;
+
+    --report to_string(t_q);
+    assert t_q = "01"
+      report "Test Failed: " & to_string(t_q) & " != 01"
+      severity error;
+    wait for 20 ns;
+
+    --report to_string(t_q);
+    assert t_q = "00"
+      report "Test Failed: " & to_string(t_q) & " != 00"
+      severity error;
+    wait for 20 ns;
+
+    report to_string(t_q);
+    wait for 20 ns;
+
+    wait;
+  end process;
+
+end arch_ent_ctr_tb;
+
+
+
+
+
+
+
+-- global:
+--   zoom: 2
+--   date: Thu Mar  3 10:05:58 2022
+--   total: 51
+--   skip: 0
+--   time:
+--     scale: 1.00
+--     unit:  fs
+--     line        : "0                   10
+-- channels:
+--   ent_ctr_tb:
+--     t_clk       : "▁▁╱▔╲▁╱▔╲▁╱▔╲▁╱▔╲▁╱▔╲▁
+--     t_en        : "▁▁▁▁╱▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
+--     t_load      : "▔▔▔▔╲▁▁▁▁▁▁▁▁▁▁▁▁▁▁▁▁▁
+--     t_data[1:0] : "3 3 3 3 3 3 3 3 3 3 3 
+--     t_q[1:0]    : "U 3 3 2 2 1 1 0 0 0 0 
+--   t_ctr:
+--     clk         : "▁▁╱▔╲▁╱▔╲▁╱▔╲▁╱▔╲▁╱▔╲▁
+--     en          : "▁▁▁▁╱▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
+--     load        : "▔▔▔▔╲▁▁▁▁▁▁▁▁▁▁▁▁▁▁▁▁▁
+--     data[1:0]   : "3 3 3 3 3 3 3 3 3 3 3 
+--     q[1:0]      : "U 3 3 2 2 1 1 0 0 0 0 
+--     nextq[1:0]  : "U 3 3 2 2 1 1 0 0 0 0 

vhdl/2b-down-counter/ctr.vhdl

@@ -0,0 +1,34 @@
+-- load and en won't have effect in the same clock.
+-- load has greater precedence.
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity ent_ctr is
+  port(
+    clk  : in  std_logic;
+    en   : in  std_logic;
+    load : in  std_logic;
+    data : in  std_logic_vector(1 downto 0);
+    q    : out std_logic_vector(1 downto 0)
+  );
+end entity ent_ctr;
+
+architecture arch_ctr of ent_ctr is
+  signal nextq : std_logic_vector(1 downto 0);
+begin
+  process(clk)
+  begin
+    if rising_edge(clk) then
+      if load = '1' then
+        -- set counter to new value
+        nextq <= data;
+      elsif en = '1' and nextq /= "00" then
+        -- keep counting
+        -- XXX: got to take care of counting down after "00"
+        nextq <= std_logic_vector(to_unsigned((to_integer(unsigned(nextq)) - 1), 2));
+      end if;
+    end if;
+  end process;
+  q <= nextq;
+end arch_ctr;

vhdl/2b-timer/Makefile

@@ -0,0 +1,17 @@
+NAME = ctr
+
+build: $(NAME).vhdl $(NAME)-tb.vhdl
+	ghdl -a --std=08 $(NAME).vhdl
+	ghdl -a --std=08 $(NAME)-tb.vhdl
+	ghdl -e --std=08 $(NAME)_tb
+
+PHONY: sim clean
+
+clean:
+	rm -rf dump.vcd *.cf
+
+sim:
+	ghdl -r --std=08 $(NAME)_tb --vcd=dump.vcd --stop-time=500ns
+
+vcd: dump.vcd
+	~/Downloads/vcd-x86_64-linux-gnu-220131 < dump.vcd

vhdl/2b-timer/ctr-tb.vhdl

@@ -0,0 +1,92 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity ctr_tb is
+end entity ctr_tb;
+
+architecture behav_tb of ctr_tb is
+  signal clk   : std_logic := '1';
+  signal load  : std_logic;
+  signal data  : std_logic_vector(1 downto 0);
+  signal count : std_logic_vector(1 downto 0);
+  signal fired : std_logic;
+
+  function status(
+      ld: std_logic;
+      d, cnt: std_logic_vector(1 downto 0);
+      frd : std_logic
+    ) return string is
+  begin
+    return "load=" & std_logic'image(ld) & ", " & 
+           "data=" & to_string(d) & ", " &
+           "count=" & to_string(cnt) & ", " &
+           "fired=" & std_logic'image(frd);
+  end function status;
+begin
+  uut: entity work.ctr port map(
+    clk, load, data, count, fired
+  );
+
+  -- clock period is 10 ns
+  clk <= not clk after 5 ns;
+  
+  process
+    type patt_t is record
+        c : std_logic_vector(1 downto 0);
+        f : std_logic;
+    end record;
+
+    type patt_arr is array (natural range <>) of patt_t;
+    constant patts : patt_arr := (
+    -- count fired
+      --("00", '0'),
+      ("11", '0'),
+      ("10", '0'),
+      ("01", '0'),
+      ("00", '1'),
+      ("00", '1')
+    );
+  begin
+    load <= '1';
+    data <= "11";
+    wait for 15 ns;
+
+    --report status(load, data, count, fired);
+    load <= '0';
+    wait for 10 ns;
+
+    for i in patts'range loop
+      assert count = patts(i).c and fired = patts(i).f
+        report "Error! " & status(load, data, count, fired)
+        severity error;
+      wait for 10 ns;
+    end loop;
+
+    wait;
+  end process;
+end architecture behav_tb;
+
+
+--global:
+--  zoom: 2
+--  date: Fri Mar  4 13:01:00 2022
+--  total: 101
+--  skip: 0
+--  time:
+--    scale: 1.00
+--    unit:  fs
+--    line       : "0                   10       
+--channels:
+--  ctr_tb:
+--    clk        : "▔▔╲▁╱▔╲▁╱▔╲▁╱▔╲▁╱▔╲▁╱▔╲▁╱▔╲▁╱
+--    load       : "▔▔▔▔▔▔╲▁▁▁▁▁▁▁▁▁▁▁▁▁▁▁▁▁▁▁▁▁▁
+--    data[1:0]  : "3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+--    count[1:0] : "U U 0 0 3 3 2 2 1 1 0 0 0 0 0
+--    fired      : "U U ▁▁▁▁▁▁▁▁▁▁▁▁▁▁▁▁╱▔▔▔▔▔▔▔▔
+--  uut:
+--    clk        : "▔▔╲▁╱▔╲▁╱▔╲▁╱▔╲▁╱▔╲▁╱▔╲▁╱▔╲▁╱
+--    load       : "▔▔▔▔▔▔╲▁▁▁▁▁▁▁▁▁▁▁▁▁▁▁▁▁▁▁▁▁▁
+--    data[1:0]  : "3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+--    count[1:0] : "U U 0 0 3 3 2 2 1 1 0 0 0 0 0
+--    fired      : "U U ▁▁▁▁▁▁▁▁▁▁▁▁▁▁▁▁╱▔▔▔▔▔▔▔▔
+--    nextq[1:0] : "0 0 3 3 2 2 1 1 0 0 0 0 0 0 0

vhdl/2b-timer/ctr.vhdl

@@ -0,0 +1,40 @@
+library ieee;
+use ieee.std_logic_1164.all;
+--use ieee.numeric_std.all;
+use ieee.numeric_std_unsigned.all;  -- for '-' operator on vectors
+
+entity ctr is
+  generic (n : natural := 2);
+  port (
+    -- fired is '1' means no counting happens
+    clk   : in  std_logic;
+    load  : in  std_logic;
+    data  : in  std_logic_vector(n-1 downto 0);
+    count : out std_logic_vector(n-1 downto 0);
+    fired : out std_logic
+  );
+end entity ctr;
+
+architecture behav of ctr is
+  constant zero  : std_logic_vector(n-1 downto 0) := (others => '0');
+  signal nextq   : std_logic_vector(n-1 downto 0) := zero;
+begin
+  process(clk)
+    variable en : std_logic := '1';
+  begin
+    if rising_edge(clk) then
+      if load = '1' then
+        nextq <= data;
+        fired <= '0';
+      elsif en = '1' then
+        if nextq = zero then
+          en := '0';
+          fired <= '1';
+        else
+          nextq <= nextq - 1;
+        end if;
+      end if;
+      count <= nextq;
+    end if;
+  end process;
+end architecture behav;

vhdl/2b-up-counter-gaisler/Makefile

@@ -0,0 +1,14 @@
+build: ctr.vhdl ctr_tb.vhdl
+	ghdl -a ctr.vhdl
+	ghdl -e counter
+	ghdl -a ctr_tb.vhdl
+	ghdl -e counter_tb
+
+wave: dump.vcd
+	vcd < dump.vcd
+	#gtkwave dump.vcd
+
+PHONY: sim
+
+sim:
+	ghdl -r counter_tb --stop-time=100ns --vcd=dump.vcd

vhdl/2b-up-counter-gaisler/ctr.vhdl

@@ -0,0 +1,61 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+package counter_comp is
+    type counter_in_t is record
+        reset: std_logic;
+        enable: std_logic;
+    end record;
+
+    type counter_out_t is record
+        q: std_logic_vector(1 downto 0);
+    end record;
+
+    component counter
+        port(
+            clk: in std_logic;
+            d: counter_in_t;
+            q: counter_out_t
+        );
+    end component;
+end package;
+
+----------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use work.counter_comp.all;
+
+entity counter is
+    port(
+        clk: in std_logic;
+        d: in counter_in_t;
+        q: out counter_out_t
+    );
+end counter;
+
+architecture counter_arch of counter is
+    signal r : std_logic_vector(1 downto 0);
+begin
+    seq: process(clk)
+    begin
+        if rising_edge(clk) then
+            q <= preq;
+        end if;
+    end process;
+
+    comb: process(enable, reset)
+        variable curq: Integer;
+    begin
+        if reset = '1' then
+            preq <= "00";
+        elsif enable = '1' then
+            if preq = "11" then
+                preq <= "00";
+            else
+                preq <= std_logic_vector(to_unsigned((to_integer(unsigned(preq)) + 1), 2));
+            end if;
+        end if;
+    end process;
+end counter_arch;

vhdl/2b-up-counter-gaisler/ctr_tb.vhdl

@@ -0,0 +1,63 @@
+-- http://esd.cs.ucr.edu/labs/tutorial/tb_counter.vhd
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity counter_tb is
+end counter_tb;
+
+architecture arch_counter_tb of counter_tb is
+    component counter
+        port (
+            clk: in std_logic;
+            reset: in std_logic;
+            enable: in std_logic;
+            q: out std_logic_vector(1 downto 0)
+        );
+    end component;
+    signal t_clk: std_logic;
+    signal t_reset: std_logic;
+    signal t_enable: std_logic;
+    signal t_q: std_logic_vector(1 downto 0);
+begin
+    t_counter: counter port map(
+        t_clk, t_reset, t_enable, t_q
+    );
+    process
+    begin
+        t_clk <= '0';
+        wait for 5 ns;
+        t_clk <= '1';
+        wait for 5 ns;
+    end process;
+
+    process
+        type outarray is array (natural range <>) of std_logic_vector(1 downto 0);
+        constant outvals : outarray := ("11", "00", "01", "10", "11");
+    begin
+        wait for 20 ns;
+        t_reset <= '0';   -- reset counter
+        t_enable <= '1';  --  start counter
+        wait for 10 ns;
+
+        assert t_q = "00"
+            report "Failed: expected '00' got " & integer'image(to_integer(unsigned(t_q)));
+        wait for 10 ns;
+        assert t_q = "01"
+            report "Failed: expected '01' got " & integer'image(to_integer(unsigned(t_q)));
+        wait for 10 ns;
+        assert t_q = "10"
+            report "Failed: expected '10' got " & integer'image(to_integer(unsigned(t_q)));
+
+--        for i in outvals'range loop
+--            wait for 10 ns;
+--            assert t_q = outvals(i)
+--                report "Failed: '" & std_logic_vector'image(t_q) &
+--                       "' instead of '" & std_logic_vector'image(outvals(i))
+--                       severity error;
+--        end loop;
+
+        wait;
+    end process;
+end arch_counter_tb;

vhdl/2b-up-counter/Makefile

@@ -0,0 +1,14 @@
+build: ctr.vhdl ctr_tb.vhdl
+	ghdl -a ctr.vhdl
+	ghdl -e counter
+	ghdl -a ctr_tb.vhdl
+	ghdl -e counter_tb
+
+wave: dump.vcd
+	vcd < dump.vcd
+	#gtkwave dump.vcd
+
+PHONY: sim
+
+sim:
+	ghdl -r counter_tb --stop-time=100ns --vcd=dump.vcd

vhdl/2b-up-counter/ctr.vhdl

@@ -0,0 +1,37 @@
+library ieee;
+use ieee.std_logic_1164.all;
+--use ieee.std_logic_unsigned.all;
+--use ieee.numeric_bit_unsigned.all;
+use ieee.numeric_std.all;
+--use ieee.std_logic_arith.all;
+
+entity counter is
+port(
+    clk: in std_logic;
+    reset: in std_logic;
+    enable: in std_logic;
+    q: out std_logic_vector(1 downto 0)
+);
+end counter;
+
+architecture counter_arch of counter is
+    signal preq : std_logic_vector(1 downto 0);
+begin
+    process(clk, enable, reset)
+        variable curq: Integer;
+    begin
+        if rising_edge(clk) then
+            if reset = '1' then
+                preq <= "00";
+            elsif enable = '1' then
+                if preq = "11" then
+                    preq <= "00";
+                else
+                    preq <= std_logic_vector(to_unsigned((to_integer(unsigned(preq)) + 1), 2));
+                end if;
+            end if;
+        end if;
+    end process;
+
+    q <= preq;
+end counter_arch;

vhdl/2b-up-counter/ctr_tb.vhdl

@@ -0,0 +1,59 @@
+-- http://esd.cs.ucr.edu/labs/tutorial/tb_counter.vhd
+library ieee;
+use ieee.std_logic_1164.all;
+--use ieee.std_logic_arith.all;
+use ieee.numeric_std.all;
+
+entity counter_tb is
+end counter_tb;
+
+architecture arch_counter_tb of counter_tb is
+    component counter
+        port (
+            clk: in std_logic;
+            reset: in std_logic;
+            enable: in std_logic;
+            q: out std_logic_vector(1 downto 0)
+        );
+    end component;
+    signal t_clk: std_logic;
+    signal t_reset: std_logic;
+    signal t_enable: std_logic;
+    signal t_q: std_logic_vector(1 downto 0);
+begin
+    t_counter: counter port map(
+        t_clk, t_reset, t_enable, t_q
+    );
+    process
+    begin
+        t_clk <= '0';
+        wait for 5 ns;
+        t_clk <= '1';
+        wait for 5 ns;
+    end process;
+
+    process
+    begin
+        t_enable <= '1';  --  start counter
+        wait for 20 ns;
+        t_reset <= '0';   -- reset counter
+
+        -- test case 1
+        wait for 10 ns;
+        assert t_q = "11"
+            report "Test case 1 failed" severity error;
+        wait for 10 ns;
+        assert t_q = "00"
+            report "Test case 2 failed" severity error;
+        wait for 10 ns;
+        assert t_q = "01"
+            report "Test case 3 failed" severity error;
+        wait for 10 ns;
+        assert t_q = "10"
+            report "Test case 4 failed" severity error;
+        wait for 10 ns;
+        assert t_q = "11"
+            report "Test case 5 failed" severity error;
+        wait;
+    end process;
+end arch_counter_tb;

vhdl/cla-adder/cla.vhdl

@@ -0,0 +1,52 @@
+------------------------
+-- adder for CLA
+------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity cla_e is
+  port (
+    a, b, cin : in  std_logic;
+    s, cout   : out std_logic
+  );
+end entity cla_e;
+
+architecture cla_a of cla_e is
+begin
+  s    <= a xor b xor cin;
+  cout <= (a and b) or (b and cin) or (a and cin);
+end architecture cla_a;
+
+------------------------------
+-- 4-bit carry-lookahead adder
+------------------------------
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity rca_e is
+  port (
+    a, b : in  std_logic_vector(3 downto 0);
+    cin  : in  std_logic;
+    s    : out std_logic_vector(3 downto 0);
+    cout : out  std_logic
+  );
+end entity rca_e;
+
+architecture rca_a of rca_e is
+  -- signals to store intermediate carry values
+  signal co0, co1, co2 : std_logic;
+begin
+  FA0: entity work.cla_e port map(
+    a(0), b(0), cin, s(0), co0
+--    a(0) => a,
+--    b(0) => b,
+--    cin  => cin,
+--    s(0) => s,
+--    co0  => cout
+  );
+
+  FA1: entity work.cla_e port map(a(1), b(1), co0, s(1), co1);
+  FA2: entity work.cla_e port map(a(2), b(2), co1, s(2), co2);
+  FA3: entity work.cla_e port map(a(3), b(3), co2, s(3), cout);
+end architecture rca_a;

vhdl/comparator/Makefile

@@ -0,0 +1,13 @@
+build: comparator.vhdl comparator-tb.vhdl
+	ghdl -a --std=08 comparator.vhdl
+	ghdl -a --std=08 comparator-tb.vhdl
+	ghdl -e --std=08 comparator_tb_e
+
+clean:
+	rm -rf dump.vcd *.cf
+
+sim:
+	ghdl -r --std=08 comparator_tb_e --vcd=dump.vcd --stop-time=100ns
+
+vcd: dump.vcd
+	~/Downloads/vcd-x86_64-linux-gnu-220131 < dump.vcd

vhdl/comparator/comparator-tb.vhdl

@@ -0,0 +1,39 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity comparator_tb_e is
+end entity comparator_tb_e;
+
+architecture comparator_tb_a of comparator_tb_e is
+  signal t_a : std_logic_vector(2 downto 0);
+  signal t_b : std_logic_vector(2 downto 0);
+  signal t_o : std_logic_vector(1 downto 0);
+begin
+  uut : entity work.comparator_e port map(
+    t_a, t_b, t_o
+  );
+  process
+  begin
+    t_a <= "100";
+    t_b <= "010";
+    wait for 1 ns;
+    assert t_o = "10"
+      report "Test failed!"
+      severity error;
+
+    t_a <= "010";
+    t_b <= "100";
+    wait for 1 ns;
+    assert t_o = "01"
+      report "Test failed!"
+      severity error;
+
+    t_a <= "010";
+    t_b <= "010";
+    wait for 1 ns;
+    assert t_o = "00"
+      report "Test failed!"
+      severity error;
+    wait;
+  end process;
+end architecture comparator_tb_a;

vhdl/comparator/comparator.vhdl

@@ -0,0 +1,24 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity comparator_e is
+  port(
+    a : in  std_logic_vector(2 downto 0);
+    b : in  std_logic_vector(2 downto 0);
+    o : out std_logic_vector(1 downto 0)
+ );
+end entity comparator_e;
+
+architecture comparator_a of comparator_e is
+begin
+  process(a, b)
+  begin
+    if a < b then
+      o <= "01";
+    elsif a > b then
+      o <= "10";
+    else
+      o <= "00";
+    end if;
+  end process;
+end architecture comparator_a;

vhdl/half-adder/Makefile

@@ -0,0 +1,13 @@
+build: hadder.vhdl hadder_tb.vhdl
+	ghdl -a hadder.vhdl
+	ghdl -e hadder
+	ghdl -a hadder_tb.vhdl
+	ghdl -e hadder_tb
+
+PHONY: run
+
+run:
+	ghdl -r hadder_tb --vcd=dump.vcd --stop-time=50ns
+
+sim: dump.vcd
+	vcd-x86_64-linux-gnu-220131 < dump.vcd

vhdl/half-adder/hadder.vhdl

@@ -0,0 +1,17 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity hadder is
+  port(
+    a: in std_logic;
+    b: in std_logic;
+    s: out std_logic;
+    c: out std_logic
+  );
+end hadder;
+
+architecture arch_hadder of hadder is
+begin
+    s <= a xor b;
+    c <= a and b;
+end arch_hadder;

vhdl/half-adder/hadder_tb.vhdl

@@ -0,0 +1,64 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity hadder_tb is
+end hadder_tb;
+
+architecture arch_hadder_tb of hadder_tb is
+    component hadder
+        port(
+            a, b: in std_logic;
+            s, c: out std_logic
+        );
+    end component;
+
+    -- mention which entity is bound with the component
+    --for hadder_0: hadder use entity work.hadder;
+
+    signal tb_a, tb_b, tb_s, tb_c: std_logic;
+begin
+    hadder_0: hadder port map(
+        a => tb_a,
+        b => tb_b,
+        s => tb_s,
+        c => tb_c
+    );
+    process
+        type pattern_type is record
+            a, b, s, c: std_logic;
+        end record;
+
+        type pattern_array is array (natural range <>) of pattern_type;
+        constant patterns: pattern_array := (
+    --    a    b    s    c  
+        ('0', '0', '0', '0'),
+        ('0', '1', '1', '0'),
+        ('1', '0', '1', '0'),
+        ('1', '1', '0', '1')
+        );
+    begin
+        for i in patterns'range loop
+            -- Feed input
+            tb_a <= patterns(i).a;
+            tb_b <= patterns(i).b;
+
+            -- Wait for output to form
+            wait for 1 ns;
+
+            -- Check output
+            assert tb_s = patterns(i).s
+                report "Bad sum '" & std_logic'image(tb_s)  &
+                       "' for a=" & std_logic'image(tb_a) &
+                       ", b=" & std_logic'image(tb_b) severity error;
+            assert tb_c = patterns(i).c
+                report "Bad carry '" & std_logic'image(tb_c)  &
+                       "' for a=" & std_logic'image(tb_a) & ", b=" &
+                       std_logic'image(tb_b)
+                       severity error;
+        end loop;
+        assert false report "End of tests" severity note;
+
+        -- wait forever
+        wait;
+    end process;
+end arch_hadder_tb;

vhdl/mux/Makefile

@@ -0,0 +1,17 @@
+NAME = alu
+
+build: $(NAME).vhdl#$(NAME)-tb.vhdl
+	ghdl -a --std=08 $(NAME).vhdl
+	ghdl -a --std=08 $(NAME)-tb.vhdl
+	ghdl -e --std=08 testbench
+
+PHONY: sim clean
+
+clean:
+	rm -rf dump.vcd *.cf
+
+sim:
+	ghdl -r --std=08 testbench --vcd=dump.vcd --stop-time=100ns
+
+vcd: dump.vcd
+	~/Downloads/vcd-x86_64-linux-gnu-220131 < dump.vcd

vhdl/mux/alu-tb.vhdl

@@ -0,0 +1,30 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity testbench is
+end entity testbench;
+
+architecture behavioral of testbench is
+  signal a, b : std_logic;
+  signal sel  : std_logic;
+  signal o    : std_logic;
+begin
+  uut: entity work.alu port map(
+    a, b, sel, o
+  );
+
+  process
+  begin
+    a <= '1';
+    b <= '1';
+    sel <= '0';
+    wait for 10 ns;
+    assert o = '1';
+
+    sel <= '1';
+    wait for 10 ns;
+    assert o = '0';
+
+    wait;
+  end process;
+end architecture;

vhdl/mux/alu.vhdl

@@ -0,0 +1,75 @@
+---------------
+-- DESIGN
+---------------
+---------------
+
+---------------
+-- AND
+---------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity andop is
+  port(
+    a, b    : in  std_logic;
+    and_out : out std_logic
+  );
+end entity andop;
+
+architecture behavioral of andop  is
+begin
+  and_out <= a and b;
+end architecture;
+
+
+---------------
+-- XOR
+---------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity xorop is
+  port(
+    a, b : in  std_logic;
+    xor_out : out std_logic
+  );
+end entity xorop;
+
+architecture behavioral of xorop is
+begin
+  xor_out <= a xor b;
+end architecture;
+
+
+---------------
+-- ALU
+---------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity alu is
+  port(
+    a, b : in  std_logic;
+    sel  : in  std_logic;
+    o    : out std_logic
+  );
+end entity alu;
+
+architecture behavioral of alu is
+  signal xor_out : std_logic;
+  signal and_out : std_logic;
+begin
+  xorcomp : entity work.xorop port map(
+    a, b, xor_out 
+  );
+  andcomp : entity work.andop port map(
+    a, b, and_out
+  );
+
+  with sel select o <=
+    and_out when '0',
+    xor_out when others;
+end architecture;

vhdl/record_inputs/Makefile

@@ -0,0 +1,14 @@
+build: recinps.vhdl recinps-tb.vhdl
+	ghdl -a recinps.vhdl
+	ghdl -e recinps
+	ghdl -a recinps-tb.vhdl
+	ghdl -e recinps_tb
+
+clean:
+	rm -rf dump.vcd *.cf
+
+sim:
+	ghdl -r recinps_tb --vcd=dump.vcd --stop-time=100ns
+
+vcd: dump.vcd
+	~/Downloads/vcd-x86_64-linux-gnu-220131 < dump.vcd

vhdl/record_inputs/recinps-tb.vhdl

@@ -0,0 +1,39 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use work.toppack.all;
+
+entity recinps_tb is
+end recinps_tb;
+
+architecture behavioral of recinps_tb is
+  signal a : rec_type;
+  signal q : std_logic;
+begin
+  uut: entity work.recinps port map(
+    a, q
+  );
+
+  process
+    type patt_type is record
+      a : rec_type;
+      o : std_logic;
+    end record;
+
+    type patt_array is array (natural range <>) of patt_type;
+    constant patterns : patt_array := (
+    -- a.vec  a.bt    q
+      (("00",  '1'),  '0'),
+      (("10",  '1'),  '0')
+    );
+  begin
+    report "hi..";
+    for i in patterns'range loop
+      a <= patterns(i).a;
+      wait for 10 ns;
+      assert q = patterns(i).o
+        report "Failed!"
+        severity error;
+    end loop;
+    wait;
+  end process;
+end architecture behavioral;

vhdl/record_inputs/recinps.vhdl

@@ -0,0 +1,37 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+package toppack is
+  type rec_type is record 
+    vec : std_logic_vector(1 downto 0);
+    bt  : std_logic;
+  end record;
+end toppack;
+
+-----
+
+library ieee;
+use ieee.std_logic_1164.all;
+use work.toppack.all;
+
+entity recinps is
+  port(
+    a: in  rec_type;
+    q: out std_logic
+  );
+end recinps;
+
+architecture behavioral of recinps is
+begin
+  process
+    constant all1s : std_logic_vector(1 downto 0) := "11";
+    variable temp : std_logic_vector(1 downto 0);
+  begin
+    temp := a.vec xor all1s;
+    if temp = all1s then
+      q <= '1' xor a.bt;
+    else
+      q <= '0' xor a.bt;
+    end if;
+  end process;
+end architecture behavioral;

vhdl/ripple-ca/Makefile

@@ -0,0 +1,17 @@
+NAME = ripple-ca
+
+build: $(NAME).vhdl $(NAME)-tb.vhdl
+	ghdl -a --std=08 $(NAME).vhdl
+	ghdl -a --std=08 $(NAME)-tb.vhdl
+	ghdl -e --std=08 rca_tb_e
+
+PHONY: sim clean
+
+clean:
+	rm -rf dump.vcd *.cf
+
+sim:
+	ghdl -r --std=08 rca_tb_e --vcd=dump.vcd --stop-time=100ns
+
+vcd: dump.vcd
+	~/Downloads/vcd-x86_64-linux-gnu-220131 < dump.vcd

vhdl/ripple-ca/ripple-ca-tb.vhdl

@@ -0,0 +1,29 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity rca_tb_e is
+end rca_tb_e;
+
+architecture rca_tb_a of rca_tb_e is
+  signal t_a, t_b : std_logic_vector(3 downto 0);
+  signal t_cin    : std_logic;
+  signal t_s      : std_logic_vector(3 downto 0);
+  signal t_cout   : std_logic;
+begin
+  t_rca_e: entity work.rca_e port map(
+    t_a, t_b, t_cin, t_s, t_cout
+  );
+
+  process
+  begin
+    t_a <= "0100";
+    t_b <= "0101";
+    t_cin <= '0';
+    wait for 10 ns;
+    assert t_s = "1001"
+      report "Expected 1001, got " & to_string(t_s)
+      severity error;
+    wait;
+  end process;
+end architecture rca_tb_a;

vhdl/ripple-ca/ripple-ca.vhdl

@@ -0,0 +1,54 @@
+------------------------
+-- Full adder
+------------------------
+--
+-- no (explicit) clock
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity fa_e is
+  port (
+    a, b, cin : in  std_logic;
+    s, cout   : out std_logic
+  );
+end entity fa_e;
+
+architecture fa_a of fa_e is
+begin
+  s    <= a xor b xor cin;
+  cout <= (a and b) or (b and cin) or (a and cin);
+end architecture fa_a;
+
+---------------------------
+-- 4-bit ripple carry adder
+---------------------------
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity rca_e is
+  port (
+    a, b : in  std_logic_vector(3 downto 0);
+    cin  : in  std_logic;
+    s    : out std_logic_vector(3 downto 0);
+    cout : out  std_logic
+  );
+end entity rca_e;
+
+architecture rca_a of rca_e is
+  -- signals to store intermediate carry values
+  signal co0, co1, co2 : std_logic;
+begin
+  FA0: entity work.fa_e port map(
+    a(0), b(0), cin, s(0), co0
+--    a(0) => a,
+--    b(0) => b,
+--    cin  => cin,
+--    s(0) => s,
+--    co0  => cout
+  );
+
+  FA1: entity work.fa_e port map(a(1), b(1), co0, s(1), co1);
+  FA2: entity work.fa_e port map(a(2), b(2), co1, s(2), co2);
+  FA3: entity work.fa_e port map(a(3), b(3), co2, s(3), cout);
+end architecture rca_a;