# Tool for simulating verilog
EXEFILE_VSIM ?= iverilog

# Path to bsim
EXEFILE_VSIM ?= bsim


all: compile link sim

compile:
	@echo Compiling for Bluesim ...
	bsc -u -sim $(BSCDIRS_BSIM)  $(BSCFLAGS)  -p $(BSCPATH_BSIM)  $(TOPFILE)
	@echo Compilation for Bluesim finished

link:
	@echo Linking for Bluesim ...
	bsc  -sim  -parallel-sim-link 8\
		$(BSCDIRS_BSIM)  -p $(BSCPATH_BSIM) \
		-e $(TOPMODULE) -o ./$(EXEFILE_BSIM) \
		-keep-fires \
		$(BSC_C_FLAGS)
	@echo Linking for Bluesim finished

sim:
	@echo Simulation in Bluesim...
	./$(EXEFILE_BSIM)
	@echo Simulation in Bluesim finished

vall: v_compile v_link v_sim

v_compile: build_v verilog
	@echo "Compiling for Verilog (Verilog generation) ..."
	bsc -u -elab -verilog  $(BSCDIRS_V)  $(BSCFLAGS)  -p $(BSCPATH_V)  $(TOPFILE)
	@echo Verilog generation finished

v_link:
	@echo Linking for Verilog simulation ...
	bsc -verilog  -vsim $(VSIM)  $(BSCDIRS_V) \
		-e $(TOPMODULE) -o ./$(EXEFILE_VSIM) \
		-keep-fires
	@echo Linking for Verilog simulation finished

v_sim:
	@echo Verilog simulation ...
	./$(EXEFILE_VSIM)
	@echo Verilog simulation finished