module TimeReg where

import Clash.Prelude

time
  :: Maybe a    -- ^ signal value
  -> Int        -- ^ time value present in register
  -> Maybe Int  -- ^ output
time Nothing _ = Nothing
time _ t = Just t

timeS
  :: HiddenClockResetEnable dom
  => Signal dom (Maybe a)
  -> Signal dom (Maybe Int)
timeS x = time <$> x <*> r
 where
  r = register 0 (r + 1)


topEntity
  :: Clock System
  -> Reset System
  -> Enable System
  -> Signal System (Maybe (Signed 8))
  -> Signal System (Maybe Int)
topEntity = exposeClockResetEnable timeS




-- import qualified Data.List as L
-- *TimeReg L> L.take 5 $ simulate @System timeS [Just 0, Just 1, Nothing, Just 3, Nothing]
-- [Just 0,Just 1,Nothing,Just 3,Nothing]








-- old output
-- import qualified Data.List as L
-- *TimeReg L> L.take 4 $ simulate @System timeS [Just 1::Maybe (Signed 8), Just 2, Nothing, Just 3, Just 4]
-- *TimeReg L> L.take 4 $ simulate @System timeS [Just 1, Just 2, Nothing, Just 3, Just 4]
-- [Just 0,Just 1,Nothing,Just 3]
-- [Just 1, Just 2, Nothing, Just 3, Just 4]
--         [Just 0,Just 1,Nothing,Just 3]