53 lines
1.1 KiB
Haskell
53 lines
1.1 KiB
Haskell
module TimeReg where
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import Clash.Prelude
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time
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:: Maybe a -- ^ signal value
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-> Int -- ^ time value present in register
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-> Maybe Int -- ^ output
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time Nothing _ = Nothing
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time _ t = Just t
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timeS
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:: HiddenClockResetEnable dom
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=> Signal dom (Maybe a)
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-> Signal dom (Maybe Int)
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timeS x = time <$> x <*> r
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where
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r = register 0 (r + 1)
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topEntity
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:: Clock System
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-> Reset System
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-> Enable System
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-> Signal System (Maybe (Signed 8))
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-> Signal System (Maybe Int)
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topEntity = exposeClockResetEnable timeS
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-- import qualified Data.List as L
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-- *TimeReg L> L.take 5 $ simulate @System timeS [Just 0, Just 1, Nothing, Just 3, Nothing]
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-- [Just 0,Just 1,Nothing,Just 3,Nothing]
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-- old output
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-- import qualified Data.List as L
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-- *TimeReg L> L.take 4 $ simulate @System timeS [Just 1::Maybe (Signed 8), Just 2, Nothing, Just 3, Just 4]
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-- *TimeReg L> L.take 4 $ simulate @System timeS [Just 1, Just 2, Nothing, Just 3, Just 4]
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-- [Just 0,Just 1,Nothing,Just 3]
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-- [Just 1, Just 2, Nothing, Just 3, Just 4]
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-- [Just 0,Just 1,Nothing,Just 3]
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