24 lines
427 B
Verilog
24 lines
427 B
Verilog
module testbench;
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reg f, x, y;
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simpleand DUT(f, x, y);
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initial
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begin
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$dumpfile ("simpleand.vcd");
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$dumpvars (0, testbench);
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$monitor ($time, "f=%b, x=%b, y=%b", f, x, y);
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#1 x=0; y=0;
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#3 x=0; y=1;
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#3 x=1; y=0;
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#3 x=1; y=1;
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#3 $finish;
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end
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endmodule
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/*
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-------\
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x -->-| |
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| |-----> f
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y -->-| |
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-------/
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*/
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