46 lines
952 B
Verilog
46 lines
952 B
Verilog
// Structural definition.
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// netlist.
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// Can be specified at different levels
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// Each successive level reveals more details
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// A 4-bit ripple carry adder
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// Consists of 4 full adders
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// Each full adder has circuits for sum and carry.
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module sum (sum, a, b, cy_in);
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input a, b, cy_in;
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output sum;
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wire t;
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xor x1 (t, a, b)
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xor x2 (sum, cy_in, t)
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endmodule
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module carry (cy_out, a, b, cy_in);
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input a, b, cy_in;
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output cy_out;
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wire t1, t2, t3;
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and g1 (t1, a, b) ;
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and g2 (t2, b, c) ;
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and g3 (t3, a, c) ;
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or g4 (cy_out, t1, t2, t3);
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endmodule
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module add (cy_out, sum, a, b, cy_in);
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input a, b, cy_in;
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output sum, cy_out;
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sum s1 (sum, a, b, cy_in);
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carry c1 (cy_out, a, b, cy_in);
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endmodule
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primitive add4 (s, cy4, cy_in, x, y);
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input [3:0] x, y; // a vector. A 4-bit number here.
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input cy_in;
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output s, cy4;
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// Instantiating the constituent full adders
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add
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