41 lines
918 B
VHDL
41 lines
918 B
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity rca_tb_e is
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port(
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t_clk : std_logic
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);
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end rca_tb_e;
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architecture rca_tb_a of rca_tb_e is
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signal t_a, t_b : std_logic_vector(3 downto 0);
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signal t_cin : std_logic;
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signal t_s : std_logic_vector(3 downto 0);
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signal t_cout : std_logic;
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begin
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t_rca_e: entity work.rca_e port map(
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t_a, t_b, t_cin, t_s, t_cout
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);
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-- clock for PSL directive
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default clock is rising_edge(t_clk);
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PROP1: assert always (
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(t_a xor (t_b xor t_cin)) = "00"
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);
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--PROP2: assert always (((t_cin and (t_a xor t_b)) or (t_a and t_b)) = t_cout);
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-- process
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-- begin
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-- t_a <= "0100";
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-- t_b <= "0101";
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-- t_cin <= '0';
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-- wait for 10 ns;
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-- assert t_s = "1001"
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-- report "Expected 1001, got " & to_string(t_s)
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-- severity error;
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-- wait;
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-- end process;
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end architecture rca_tb_a;
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