55 lines
1.2 KiB
VHDL
55 lines
1.2 KiB
VHDL
------------------------
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-- Full adder
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------------------------
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--
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-- no (explicit) clock
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library ieee;
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use ieee.std_logic_1164.all;
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entity fa_e is
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port (
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a, b, cin : in std_logic;
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s, cout : out std_logic
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);
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end entity fa_e;
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architecture fa_a of fa_e is
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begin
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s <= a xor b xor cin;
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cout <= (a and b) or (b and cin) or (a and cin);
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end architecture fa_a;
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---------------------------
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-- 4-bit ripple carry adder
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---------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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entity rca_e is
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port (
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a, b : in std_logic_vector(3 downto 0);
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cin : in std_logic;
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s : out std_logic_vector(3 downto 0);
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cout : out std_logic
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);
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end entity rca_e;
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architecture rca_a of rca_e is
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-- signals to store intermediate carry values
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signal co0, co1, co2 : std_logic;
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begin
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FA0: entity work.fa_e port map(
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a(0), b(0), cin, s(0), co0
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-- a(0) => a,
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-- b(0) => b,
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-- cin => cin,
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-- s(0) => s,
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-- co0 => cout
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);
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FA1: entity work.fa_e port map(a(1), b(1), co0, s(1), co1);
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FA2: entity work.fa_e port map(a(2), b(2), co1, s(2), co2);
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FA3: entity work.fa_e port map(a(3), b(3), co2, s(3), cout);
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end architecture rca_a;
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