diff --git a/README.md b/README.md deleted file mode 100644 index 8b62cca..0000000 --- a/README.md +++ /dev/null @@ -1 +0,0 @@ -# CN_RISC_V diff --git a/RISC_V.cache/wt/gui_handlers.wdf b/RISC_V.cache/wt/gui_handlers.wdf deleted file mode 100644 index 9aa752c..0000000 --- a/RISC_V.cache/wt/gui_handlers.wdf +++ /dev/null @@ -1,69 +0,0 @@ -version:1 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f6170706c79:35:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f6f6b:3639:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636d646d73676469616c6f675f6f70656e5f6d657373616765735f76696577:37:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636f6e6669726d736176657465787465646974736469616c6f675f796573:3130:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:63726561746573726366696c656469616c6f675f66696c655f6e616d65:3132:00:00 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b/RISC_V.cache/wt/java_command_handlers.wdf deleted file mode 100644 index 6766068..0000000 --- a/RISC_V.cache/wt/java_command_handlers.wdf +++ /dev/null @@ -1,12 +0,0 @@ -version:1 -70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:616464736f7572636573:3132:00:00 -70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6564697464656c657465:31:00:00 -70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6e657770726f6a656374:31:00:00 -70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:72756e73796e746865736973:31:00:00 -70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:736574746f706e6f6465:31:00:00 -70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:73686f7776696577:37:00:00 -70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:73696d756c6174696f6e636c6f7365:35:00:00 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- - -
-
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - diff --git a/RISC_V.cache/wt/xsim.wdf b/RISC_V.cache/wt/xsim.wdf deleted file mode 100644 index 50afb2c..0000000 --- a/RISC_V.cache/wt/xsim.wdf +++ /dev/null @@ -1,4 +0,0 @@ -version:1 -7873696d:7873696d5c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73696d5f6d6f6465:64656661756c743a3a6265686176696f72616c:00:00 -7873696d:7873696d5c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73696d5f74797065:64656661756c743a3a:00:00 -eof:241934075 diff --git a/RISC_V.hw/RISC_V.lpr b/RISC_V.hw/RISC_V.lpr deleted file mode 100644 index adee5c1..0000000 --- a/RISC_V.hw/RISC_V.lpr +++ /dev/null @@ -1,6 +0,0 @@ - - - - - - diff --git a/RISC_V.ip_user_files/README.txt b/RISC_V.ip_user_files/README.txt deleted file mode 100644 index 023052c..0000000 --- a/RISC_V.ip_user_files/README.txt +++ /dev/null @@ -1 +0,0 @@ -The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended. diff --git a/RISC_V.ip_user_files/mem_init_files/code.mem b/RISC_V.ip_user_files/mem_init_files/code.mem deleted file mode 100644 index 1874a70..0000000 --- a/RISC_V.ip_user_files/mem_init_files/code.mem +++ /dev/null @@ -1,18 +0,0 @@ -00008133 00108093 0020F1B3 0010E213 0042A223 00802603 04090E63 - -add x2, x1, x0 - 0000000 00000 00001 000 00010 0110011 - 00008133 - -addi x1, x1, 1 - 000000000001 00001 000 00001 0010011 - 00108093 - -and x3, x1, x2 - 0000000 00010 00001 111 00011 0110011 - 0020F1B3 - -ori x4, x1, 1 - 000000000001 00001 110 00100 0010011 - 0010E213 - -sw x4, 4(x5) - 0000000 00100 00101 010 00100 0100011 - 0042A223 - -lw x12, 8(x0) - 000000001000 00000 010 01100 0000011 - 00802603 - -beq x18, x0, 5c - 0 0000010 00000 10010 000 1110 0 1100011 - 04090E63 - -5c = 0 0000 0101 1100 -18 = 16 + 2 = 10010 \ No newline at end of file diff --git a/RISC_V.sim/sim_1/behav/xsim/RISC_V_IF_ID_TB.tcl b/RISC_V.sim/sim_1/behav/xsim/RISC_V_IF_ID_TB.tcl deleted file mode 100644 index 1094e45..0000000 --- a/RISC_V.sim/sim_1/behav/xsim/RISC_V_IF_ID_TB.tcl +++ /dev/null @@ -1,11 +0,0 @@ -set curr_wave [current_wave_config] -if { [string length $curr_wave] == 0 } { - if { [llength [get_objects]] > 0} { - add_wave / - set_property needs_save false [current_wave_config] - } else { - send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." - } -} - -run 1000ns diff --git a/RISC_V.sim/sim_1/behav/xsim/RISC_V_IF_ID_TB_behav.wdb b/RISC_V.sim/sim_1/behav/xsim/RISC_V_IF_ID_TB_behav.wdb deleted file mode 100644 index fc92982..0000000 Binary files a/RISC_V.sim/sim_1/behav/xsim/RISC_V_IF_ID_TB_behav.wdb and /dev/null differ diff --git a/RISC_V.sim/sim_1/behav/xsim/RISC_V_IF_ID_TB_vlog.prj b/RISC_V.sim/sim_1/behav/xsim/RISC_V_IF_ID_TB_vlog.prj deleted file mode 100644 index 2890c6c..0000000 --- a/RISC_V.sim/sim_1/behav/xsim/RISC_V_IF_ID_TB_vlog.prj +++ /dev/null @@ -1,19 +0,0 @@ -# compile verilog/system verilog design source files -verilog xil_defaultlib \ -"../../../../RISC_V.srcs/sources_1/new/ID.v" \ -"../../../../RISC_V.srcs/sources_1/new/IF.v" \ -"../../../../RISC_V.srcs/sources_1/new/IF_ID_REG.v" \ -"../../../../RISC_V.srcs/sources_1/new/PC.v" \ -"../../../../RISC_V.srcs/sources_1/new/RISC_V_IF_ID.v" \ -"../../../../RISC_V.srcs/sources_1/new/adder.v" \ -"../../../../RISC_V.srcs/sources_1/new/imm_gen.v" \ -"../../../../RISC_V.srcs/sources_1/new/instruction_memory.v" \ -"../../../../RISC_V.srcs/sources_1/new/mux2_1.v" \ -"../../../../RISC_V.srcs/sources_1/new/registers.v" \ -"../../../../RISC_V.srcs/sources_1/new/RISC_V_IF_ID_TB.v" \ - -# compile glbl module -verilog xil_defaultlib "glbl.v" - -# Do not sort compile order -nosort diff --git a/RISC_V.sim/sim_1/behav/xsim/code.mem b/RISC_V.sim/sim_1/behav/xsim/code.mem deleted file mode 100644 index 1874a70..0000000 --- a/RISC_V.sim/sim_1/behav/xsim/code.mem +++ /dev/null @@ -1,18 +0,0 @@ -00008133 00108093 0020F1B3 0010E213 0042A223 00802603 04090E63 - -add x2, x1, x0 - 0000000 00000 00001 000 00010 0110011 - 00008133 - -addi x1, x1, 1 - 000000000001 00001 000 00001 0010011 - 00108093 - -and x3, x1, x2 - 0000000 00010 00001 111 00011 0110011 - 0020F1B3 - -ori x4, x1, 1 - 000000000001 00001 110 00100 0010011 - 0010E213 - -sw x4, 4(x5) - 0000000 00100 00101 010 00100 0100011 - 0042A223 - -lw x12, 8(x0) - 000000001000 00000 010 01100 0000011 - 00802603 - -beq x18, x0, 5c - 0 0000010 00000 10010 000 1110 0 1100011 - 04090E63 - -5c = 0 0000 0101 1100 -18 = 16 + 2 = 10010 \ No newline at end of file diff --git a/RISC_V.sim/sim_1/behav/xsim/compile.bat b/RISC_V.sim/sim_1/behav/xsim/compile.bat deleted file mode 100644 index 20552bd..0000000 --- a/RISC_V.sim/sim_1/behav/xsim/compile.bat +++ /dev/null @@ -1,25 +0,0 @@ -@echo off -REM **************************************************************************** -REM Vivado (TM) v2018.3 (64-bit) -REM -REM Filename : compile.bat -REM Simulator : Xilinx Vivado Simulator -REM Description : Script for compiling the simulation design source files -REM -REM Generated by Vivado on Sat Nov 21 18:32:22 +0200 2020 -REM SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 -REM -REM Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. -REM -REM usage: compile.bat -REM -REM **************************************************************************** -echo "xvlog --relax -prj RISC_V_IF_ID_TB_vlog.prj" -call xvlog --relax -prj RISC_V_IF_ID_TB_vlog.prj -log xvlog.log -call type xvlog.log > compile.log -if "%errorlevel%"=="1" goto END -if "%errorlevel%"=="0" goto SUCCESS -:END -exit 1 -:SUCCESS -exit 0 diff --git a/RISC_V.sim/sim_1/behav/xsim/compile.log b/RISC_V.sim/sim_1/behav/xsim/compile.log deleted file mode 100644 index 02f1fbe..0000000 --- a/RISC_V.sim/sim_1/behav/xsim/compile.log +++ /dev/null @@ -1,25 +0,0 @@ -INFO: [VRFC 10-2263] Analyzing Verilog file "D:/VivadoProjects/RISC_V/RISC_V.srcs/sources_1/new/ID.v" into library xil_defaultlib -INFO: [VRFC 10-311] analyzing module ID -INFO: [VRFC 10-2263] Analyzing Verilog file "D:/VivadoProjects/RISC_V/RISC_V.srcs/sources_1/new/IF.v" into library xil_defaultlib -INFO: [VRFC 10-311] analyzing module IF -INFO: [VRFC 10-2263] Analyzing Verilog file "D:/VivadoProjects/RISC_V/RISC_V.srcs/sources_1/new/IF_ID_REG.v" into library xil_defaultlib -INFO: [VRFC 10-311] analyzing module IF_ID_REG -INFO: [VRFC 10-2263] Analyzing Verilog file "D:/VivadoProjects/RISC_V/RISC_V.srcs/sources_1/new/PC.v" into library xil_defaultlib -INFO: [VRFC 10-311] analyzing module PC -INFO: [VRFC 10-2263] Analyzing Verilog file "D:/VivadoProjects/RISC_V/RISC_V.srcs/sources_1/new/RISC_V_IF_ID.v" into library xil_defaultlib -INFO: [VRFC 10-311] analyzing module RISC_V_IF_ID -WARNING: [VRFC 10-3676] redeclaration of ansi port 'PC_ID' is not allowed [D:/VivadoProjects/RISC_V/RISC_V.srcs/sources_1/new/RISC_V_IF_ID.v:44] -INFO: [VRFC 10-2263] Analyzing Verilog file "D:/VivadoProjects/RISC_V/RISC_V.srcs/sources_1/new/adder.v" into library xil_defaultlib -INFO: [VRFC 10-311] analyzing module adder -INFO: [VRFC 10-2263] Analyzing Verilog file "D:/VivadoProjects/RISC_V/RISC_V.srcs/sources_1/new/imm_gen.v" into library xil_defaultlib -INFO: [VRFC 10-311] analyzing module imm_gen -INFO: [VRFC 10-2263] Analyzing Verilog file "D:/VivadoProjects/RISC_V/RISC_V.srcs/sources_1/new/instruction_memory.v" into library xil_defaultlib -INFO: [VRFC 10-311] analyzing module instruction_memory -INFO: [VRFC 10-2263] Analyzing Verilog file "D:/VivadoProjects/RISC_V/RISC_V.srcs/sources_1/new/mux2_1.v" into library xil_defaultlib -INFO: [VRFC 10-311] analyzing module mux2_1 -INFO: [VRFC 10-2263] Analyzing Verilog file "D:/VivadoProjects/RISC_V/RISC_V.srcs/sources_1/new/registers.v" into library xil_defaultlib -INFO: [VRFC 10-311] analyzing module registers -INFO: [VRFC 10-2263] Analyzing Verilog file "D:/VivadoProjects/RISC_V/RISC_V.srcs/sources_1/new/RISC_V_IF_ID_TB.v" into library xil_defaultlib -INFO: [VRFC 10-311] analyzing module RISC_V_IF_ID_TB -INFO: [VRFC 10-2263] Analyzing Verilog file "D:/VivadoProjects/RISC_V/RISC_V.sim/sim_1/behav/xsim/glbl.v" into library xil_defaultlib -INFO: [VRFC 10-311] analyzing module glbl diff --git a/RISC_V.sim/sim_1/behav/xsim/elaborate.bat b/RISC_V.sim/sim_1/behav/xsim/elaborate.bat deleted file mode 100644 index 525642d..0000000 --- a/RISC_V.sim/sim_1/behav/xsim/elaborate.bat +++ /dev/null @@ -1,23 +0,0 @@ -@echo off -REM **************************************************************************** -REM Vivado (TM) v2018.3 (64-bit) -REM -REM Filename : elaborate.bat -REM Simulator : Xilinx Vivado Simulator -REM Description : Script for elaborating the compiled design -REM -REM Generated by Vivado on Sat Nov 21 18:32:30 +0200 2020 -REM SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 -REM -REM Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. -REM -REM usage: elaborate.bat -REM -REM **************************************************************************** -call xelab -wto ee467e506e3e426b91b11db7a6f036e4 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot RISC_V_IF_ID_TB_behav xil_defaultlib.RISC_V_IF_ID_TB xil_defaultlib.glbl -log elaborate.log -if "%errorlevel%"=="0" goto SUCCESS -if "%errorlevel%"=="1" goto END -:END -exit 1 -:SUCCESS -exit 0 diff --git a/RISC_V.sim/sim_1/behav/xsim/elaborate.log b/RISC_V.sim/sim_1/behav/xsim/elaborate.log deleted file mode 100644 index ed4d91c..0000000 --- a/RISC_V.sim/sim_1/behav/xsim/elaborate.log +++ /dev/null @@ -1,22 +0,0 @@ -Vivado Simulator 2018.3 -Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved. -Running: D:/Vivado/2018.3/bin/unwrapped/win64.o/xelab.exe -wto ee467e506e3e426b91b11db7a6f036e4 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot RISC_V_IF_ID_TB_behav xil_defaultlib.RISC_V_IF_ID_TB xil_defaultlib.glbl -log elaborate.log -Using 2 slave threads. -Starting static elaboration -Completed static elaboration -Starting simulation data flow analysis -Completed simulation data flow analysis -Time Resolution for simulation is 1ps -Compiling module xil_defaultlib.PC -Compiling module xil_defaultlib.instruction_memory -Compiling module xil_defaultlib.adder -Compiling module xil_defaultlib.mux2_1 -Compiling module xil_defaultlib.IF -Compiling module xil_defaultlib.IF_ID_REG -Compiling module xil_defaultlib.registers -Compiling module xil_defaultlib.imm_gen -Compiling module xil_defaultlib.ID -Compiling module xil_defaultlib.RISC_V_IF_ID -Compiling module xil_defaultlib.RISC_V_IF_ID_TB -Compiling module xil_defaultlib.glbl -Built simulation snapshot RISC_V_IF_ID_TB_behav diff --git a/RISC_V.sim/sim_1/behav/xsim/glbl.v b/RISC_V.sim/sim_1/behav/xsim/glbl.v deleted file mode 100644 index be64233..0000000 --- a/RISC_V.sim/sim_1/behav/xsim/glbl.v +++ /dev/null @@ -1,71 +0,0 @@ -// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ -`ifndef GLBL -`define GLBL -`timescale 1 ps / 1 ps - -module glbl (); - - parameter ROC_WIDTH = 100000; - parameter TOC_WIDTH = 0; - -//-------- STARTUP Globals -------------- - wire GSR; - wire GTS; - wire GWE; - wire PRLD; - tri1 p_up_tmp; - tri (weak1, strong0) PLL_LOCKG = p_up_tmp; - - wire PROGB_GLBL; - wire CCLKO_GLBL; - wire FCSBO_GLBL; - wire [3:0] DO_GLBL; - wire [3:0] DI_GLBL; - - reg GSR_int; - reg GTS_int; - reg PRLD_int; - -//-------- JTAG Globals -------------- - wire JTAG_TDO_GLBL; - wire JTAG_TCK_GLBL; - wire JTAG_TDI_GLBL; - wire JTAG_TMS_GLBL; - wire JTAG_TRST_GLBL; - - reg JTAG_CAPTURE_GLBL; - reg JTAG_RESET_GLBL; - reg JTAG_SHIFT_GLBL; - reg JTAG_UPDATE_GLBL; - reg JTAG_RUNTEST_GLBL; - - reg JTAG_SEL1_GLBL = 0; - reg JTAG_SEL2_GLBL = 0 ; - reg JTAG_SEL3_GLBL = 0; - reg JTAG_SEL4_GLBL = 0; - - reg JTAG_USER_TDO1_GLBL = 1'bz; - reg JTAG_USER_TDO2_GLBL = 1'bz; - reg JTAG_USER_TDO3_GLBL = 1'bz; - reg JTAG_USER_TDO4_GLBL = 1'bz; - - assign (strong1, weak0) GSR = GSR_int; - assign (strong1, weak0) GTS = GTS_int; - assign (weak1, weak0) PRLD = PRLD_int; - - initial begin - GSR_int = 1'b1; - PRLD_int = 1'b1; - #(ROC_WIDTH) - GSR_int = 1'b0; - PRLD_int = 1'b0; - end - - initial begin - GTS_int = 1'b1; - #(TOC_WIDTH) - GTS_int = 1'b0; - end - -endmodule -`endif diff --git a/RISC_V.sim/sim_1/behav/xsim/simulate.bat b/RISC_V.sim/sim_1/behav/xsim/simulate.bat deleted file mode 100644 index b4bb808..0000000 --- a/RISC_V.sim/sim_1/behav/xsim/simulate.bat +++ /dev/null @@ -1,23 +0,0 @@ -@echo off -REM **************************************************************************** -REM Vivado (TM) v2018.3 (64-bit) -REM -REM Filename : simulate.bat -REM Simulator : Xilinx Vivado Simulator -REM Description : Script for simulating the design by launching the simulator -REM -REM Generated by Vivado on Sat Nov 21 18:32:47 +0200 2020 -REM SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 -REM -REM Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. -REM -REM usage: simulate.bat -REM -REM **************************************************************************** -call xsim RISC_V_IF_ID_TB_behav -key {Behavioral:sim_1:Functional:RISC_V_IF_ID_TB} -tclbatch RISC_V_IF_ID_TB.tcl -log simulate.log -if "%errorlevel%"=="0" goto SUCCESS -if "%errorlevel%"=="1" goto END -:END -exit 1 -:SUCCESS -exit 0 diff --git a/RISC_V.sim/sim_1/behav/xsim/simulate.log b/RISC_V.sim/sim_1/behav/xsim/simulate.log deleted file mode 100644 index b250c4e..0000000 --- a/RISC_V.sim/sim_1/behav/xsim/simulate.log +++ /dev/null @@ -1,4 +0,0 @@ -Vivado Simulator 2018.3 -Time resolution is 1 ps -WARNING: Too many words specified in data file code.mem -$finish called at time : 210 ns : File "D:/VivadoProjects/RISC_V/RISC_V.srcs/sources_1/new/RISC_V_IF_ID_TB.v" Line 55 diff --git a/RISC_V.sim/sim_1/behav/xsim/webtalk.jou b/RISC_V.sim/sim_1/behav/xsim/webtalk.jou deleted file mode 100644 index 4ebc56f..0000000 --- a/RISC_V.sim/sim_1/behav/xsim/webtalk.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Webtalk v2018.3 (64-bit) -# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 -# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 -# Start of session at: Sat Nov 21 18:34:41 2020 -# Process ID: 16964 -# Current directory: D:/VivadoProjects/RISC_V/RISC_V.sim/sim_1/behav/xsim -# Command line: wbtcv.exe -mode batch -source D:/VivadoProjects/RISC_V/RISC_V.sim/sim_1/behav/xsim/xsim.dir/RISC_V_IF_ID_TB_behav/webtalk/xsim_webtalk.tcl -notrace -# Log file: D:/VivadoProjects/RISC_V/RISC_V.sim/sim_1/behav/xsim/webtalk.log -# Journal file: D:/VivadoProjects/RISC_V/RISC_V.sim/sim_1/behav/xsim\webtalk.jou -#----------------------------------------------------------- -source D:/VivadoProjects/RISC_V/RISC_V.sim/sim_1/behav/xsim/xsim.dir/RISC_V_IF_ID_TB_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/RISC_V.sim/sim_1/behav/xsim/webtalk.log b/RISC_V.sim/sim_1/behav/xsim/webtalk.log deleted file mode 100644 index 8a9d183..0000000 --- a/RISC_V.sim/sim_1/behav/xsim/webtalk.log +++ /dev/null @@ -1,13 +0,0 @@ -#----------------------------------------------------------- -# Webtalk v2018.3 (64-bit) -# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 -# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 -# Start of session at: Sat Nov 21 18:34:41 2020 -# Process ID: 16964 -# Current directory: D:/VivadoProjects/RISC_V/RISC_V.sim/sim_1/behav/xsim -# Command line: wbtcv.exe -mode batch -source D:/VivadoProjects/RISC_V/RISC_V.sim/sim_1/behav/xsim/xsim.dir/RISC_V_IF_ID_TB_behav/webtalk/xsim_webtalk.tcl -notrace -# Log file: D:/VivadoProjects/RISC_V/RISC_V.sim/sim_1/behav/xsim/webtalk.log -# Journal file: D:/VivadoProjects/RISC_V/RISC_V.sim/sim_1/behav/xsim\webtalk.jou -#----------------------------------------------------------- -source D:/VivadoProjects/RISC_V/RISC_V.sim/sim_1/behav/xsim/xsim.dir/RISC_V_IF_ID_TB_behav/webtalk/xsim_webtalk.tcl -notrace -INFO: [Common 17-206] Exiting Webtalk at Sat Nov 21 18:34:42 2020... diff --git a/RISC_V.sim/sim_1/behav/xsim/webtalk_15032.backup.jou b/RISC_V.sim/sim_1/behav/xsim/webtalk_15032.backup.jou deleted file mode 100644 index e7939e8..0000000 --- a/RISC_V.sim/sim_1/behav/xsim/webtalk_15032.backup.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Webtalk v2018.3 (64-bit) -# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 -# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 -# Start of session at: Sat Nov 21 18:32:45 2020 -# Process ID: 15032 -# Current directory: D:/VivadoProjects/RISC_V/RISC_V.sim/sim_1/behav/xsim -# Command line: wbtcv.exe -mode batch -source D:/VivadoProjects/RISC_V/RISC_V.sim/sim_1/behav/xsim/xsim.dir/RISC_V_IF_ID_TB_behav/webtalk/xsim_webtalk.tcl -notrace -# Log file: D:/VivadoProjects/RISC_V/RISC_V.sim/sim_1/behav/xsim/webtalk.log -# Journal file: D:/VivadoProjects/RISC_V/RISC_V.sim/sim_1/behav/xsim\webtalk.jou -#----------------------------------------------------------- -source D:/VivadoProjects/RISC_V/RISC_V.sim/sim_1/behav/xsim/xsim.dir/RISC_V_IF_ID_TB_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/RISC_V.sim/sim_1/behav/xsim/webtalk_15032.backup.log b/RISC_V.sim/sim_1/behav/xsim/webtalk_15032.backup.log deleted file mode 100644 index 7682e41..0000000 --- a/RISC_V.sim/sim_1/behav/xsim/webtalk_15032.backup.log +++ /dev/null @@ -1,13 +0,0 @@ -#----------------------------------------------------------- -# Webtalk v2018.3 (64-bit) -# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 -# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 -# Start of session at: Sat Nov 21 18:32:45 2020 -# Process ID: 15032 -# Current directory: D:/VivadoProjects/RISC_V/RISC_V.sim/sim_1/behav/xsim -# Command line: wbtcv.exe -mode batch -source D:/VivadoProjects/RISC_V/RISC_V.sim/sim_1/behav/xsim/xsim.dir/RISC_V_IF_ID_TB_behav/webtalk/xsim_webtalk.tcl -notrace -# Log file: D:/VivadoProjects/RISC_V/RISC_V.sim/sim_1/behav/xsim/webtalk.log -# Journal file: D:/VivadoProjects/RISC_V/RISC_V.sim/sim_1/behav/xsim\webtalk.jou -#----------------------------------------------------------- -source D:/VivadoProjects/RISC_V/RISC_V.sim/sim_1/behav/xsim/xsim.dir/RISC_V_IF_ID_TB_behav/webtalk/xsim_webtalk.tcl -notrace -INFO: [Common 17-206] Exiting Webtalk at Sat Nov 21 18:32:47 2020... diff --git a/RISC_V.sim/sim_1/behav/xsim/xelab.pb b/RISC_V.sim/sim_1/behav/xsim/xelab.pb deleted file mode 100644 index c70e36a..0000000 Binary files a/RISC_V.sim/sim_1/behav/xsim/xelab.pb and /dev/null differ diff --git a/RISC_V.sim/sim_1/behav/xsim/xsim.dir/RISC_V_IF_ID_TB_behav/Compile_Options.txt b/RISC_V.sim/sim_1/behav/xsim/xsim.dir/RISC_V_IF_ID_TB_behav/Compile_Options.txt deleted file mode 100644 index 374d302..0000000 --- a/RISC_V.sim/sim_1/behav/xsim/xsim.dir/RISC_V_IF_ID_TB_behav/Compile_Options.txt +++ /dev/null @@ -1 +0,0 @@ --wto "ee467e506e3e426b91b11db7a6f036e4" --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "unisims_ver" -L "unimacro_ver" -L "secureip" --snapshot "RISC_V_IF_ID_TB_behav" "xil_defaultlib.RISC_V_IF_ID_TB" "xil_defaultlib.glbl" -log "elaborate.log" diff --git a/RISC_V.sim/sim_1/behav/xsim/xsim.dir/RISC_V_IF_ID_TB_behav/TempBreakPointFile.txt b/RISC_V.sim/sim_1/behav/xsim/xsim.dir/RISC_V_IF_ID_TB_behav/TempBreakPointFile.txt deleted file mode 100644 index fdbc612..0000000 --- a/RISC_V.sim/sim_1/behav/xsim/xsim.dir/RISC_V_IF_ID_TB_behav/TempBreakPointFile.txt +++ /dev/null @@ -1 +0,0 @@ -Breakpoint File Version 1.0 diff --git a/RISC_V.sim/sim_1/behav/xsim/xsim.dir/RISC_V_IF_ID_TB_behav/webtalk/.xsim_webtallk.info b/RISC_V.sim/sim_1/behav/xsim/xsim.dir/RISC_V_IF_ID_TB_behav/webtalk/.xsim_webtallk.info deleted file mode 100644 index 05d1686..0000000 --- a/RISC_V.sim/sim_1/behav/xsim/xsim.dir/RISC_V_IF_ID_TB_behav/webtalk/.xsim_webtallk.info +++ /dev/null @@ -1,5 +0,0 @@ -1605976363 -1605976480 -3 -1 -ee467e506e3e426b91b11db7a6f036e4 diff --git a/RISC_V.sim/sim_1/behav/xsim/xsim.dir/RISC_V_IF_ID_TB_behav/webtalk/usage_statistics_ext_xsim.html b/RISC_V.sim/sim_1/behav/xsim/xsim.dir/RISC_V_IF_ID_TB_behav/webtalk/usage_statistics_ext_xsim.html deleted file mode 100644 index e63d88b..0000000 --- a/RISC_V.sim/sim_1/behav/xsim/xsim.dir/RISC_V_IF_ID_TB_behav/webtalk/usage_statistics_ext_xsim.html +++ /dev/null @@ -1,53 +0,0 @@ -Device Usage Statistics Report -

XSIM Usage Report


- - - - - - - - - - - - - - - - - -
software_version_and_target_device
betaFALSEbuild_version2405991
date_generatedSat Nov 21 18:34:40 2020os_platformWIN64
product_versionXSIM v2018.3 (64-bit)project_idee467e506e3e426b91b11db7a6f036e4
project_iteration2random_id601ffe88-8614-41e5-b20b-50cc1ca6fd12
registration_id601ffe88-8614-41e5-b20b-50cc1ca6fd12route_designFALSE
target_devicenot_applicabletarget_familynot_applicable
target_packagenot_applicabletarget_speednot_applicable
tool_flowxsim_vivado

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user_environment
cpu_nameIntel(R) Core(TM) i7-7700HQ CPU @ 2.80GHzcpu_speed2808 MHz
os_nameMicrosoft Windows 8 or later , 64-bitos_releasemajor release (build 9200)
system_ram8.000 GBtotal_processors1

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vivado_usage

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xsim
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command_line_options
command=xsim
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usage
iteration=0runtime=210 nssimulation_memory=6048_KBsimulation_time=0.03_sec
trace_waveform=true
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- - diff --git a/RISC_V.sim/sim_1/behav/xsim/xsim.dir/RISC_V_IF_ID_TB_behav/webtalk/usage_statistics_ext_xsim.xml b/RISC_V.sim/sim_1/behav/xsim/xsim.dir/RISC_V_IF_ID_TB_behav/webtalk/usage_statistics_ext_xsim.xml deleted file mode 100644 index f6aa74d..0000000 --- a/RISC_V.sim/sim_1/behav/xsim/xsim.dir/RISC_V_IF_ID_TB_behav/webtalk/usage_statistics_ext_xsim.xml +++ /dev/null @@ -1,44 +0,0 @@ - - -
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- diff --git a/RISC_V.sim/sim_1/behav/xsim/xsim.dir/RISC_V_IF_ID_TB_behav/xsim.dbg b/RISC_V.sim/sim_1/behav/xsim/xsim.dir/RISC_V_IF_ID_TB_behav/xsim.dbg deleted file mode 100644 index 56a3def..0000000 Binary files a/RISC_V.sim/sim_1/behav/xsim/xsim.dir/RISC_V_IF_ID_TB_behav/xsim.dbg and /dev/null differ diff --git a/RISC_V.sim/sim_1/behav/xsim/xsim.dir/RISC_V_IF_ID_TB_behav/xsim.mem b/RISC_V.sim/sim_1/behav/xsim/xsim.dir/RISC_V_IF_ID_TB_behav/xsim.mem deleted file mode 100644 index bb86557..0000000 Binary files a/RISC_V.sim/sim_1/behav/xsim/xsim.dir/RISC_V_IF_ID_TB_behav/xsim.mem and /dev/null differ diff --git a/RISC_V.sim/sim_1/behav/xsim/xsim.dir/RISC_V_IF_ID_TB_behav/xsim.reloc b/RISC_V.sim/sim_1/behav/xsim/xsim.dir/RISC_V_IF_ID_TB_behav/xsim.reloc deleted file mode 100644 index bce7836..0000000 Binary files a/RISC_V.sim/sim_1/behav/xsim/xsim.dir/RISC_V_IF_ID_TB_behav/xsim.reloc and /dev/null differ diff --git a/RISC_V.sim/sim_1/behav/xsim/xsim.dir/RISC_V_IF_ID_TB_behav/xsim.rtti b/RISC_V.sim/sim_1/behav/xsim/xsim.dir/RISC_V_IF_ID_TB_behav/xsim.rtti deleted file mode 100644 index 2c73c9c..0000000 Binary files a/RISC_V.sim/sim_1/behav/xsim/xsim.dir/RISC_V_IF_ID_TB_behav/xsim.rtti and /dev/null differ diff --git a/RISC_V.sim/sim_1/behav/xsim/xsim.dir/RISC_V_IF_ID_TB_behav/xsim.svtype b/RISC_V.sim/sim_1/behav/xsim/xsim.dir/RISC_V_IF_ID_TB_behav/xsim.svtype deleted file mode 100644 index d182fe1..0000000 Binary files a/RISC_V.sim/sim_1/behav/xsim/xsim.dir/RISC_V_IF_ID_TB_behav/xsim.svtype and /dev/null differ diff --git a/RISC_V.sim/sim_1/behav/xsim/xsim.dir/RISC_V_IF_ID_TB_behav/xsim.type b/RISC_V.sim/sim_1/behav/xsim/xsim.dir/RISC_V_IF_ID_TB_behav/xsim.type deleted file mode 100644 index 14a09a2..0000000 Binary files a/RISC_V.sim/sim_1/behav/xsim/xsim.dir/RISC_V_IF_ID_TB_behav/xsim.type and /dev/null differ diff --git a/RISC_V.sim/sim_1/behav/xsim/xsim.dir/RISC_V_IF_ID_TB_behav/xsim.xdbg b/RISC_V.sim/sim_1/behav/xsim/xsim.dir/RISC_V_IF_ID_TB_behav/xsim.xdbg deleted file mode 100644 index b981892..0000000 Binary files a/RISC_V.sim/sim_1/behav/xsim/xsim.dir/RISC_V_IF_ID_TB_behav/xsim.xdbg and /dev/null differ diff --git a/RISC_V.sim/sim_1/behav/xsim/xsim.dir/RISC_V_IF_ID_TB_behav/xsimSettings.ini b/RISC_V.sim/sim_1/behav/xsim/xsim.dir/RISC_V_IF_ID_TB_behav/xsimSettings.ini deleted file mode 100644 index be10843..0000000 --- a/RISC_V.sim/sim_1/behav/xsim/xsim.dir/RISC_V_IF_ID_TB_behav/xsimSettings.ini +++ /dev/null @@ -1,41 +0,0 @@ -[General] -ARRAY_DISPLAY_LIMIT=1024 -RADIX=hex -TIME_UNIT=ns -TRACE_LIMIT=65536 -VHDL_ENTITY_SCOPE_FILTER=true -VHDL_PACKAGE_SCOPE_FILTER=false -VHDL_BLOCK_SCOPE_FILTER=true -VHDL_PROCESS_SCOPE_FILTER=false -VHDL_PROCEDURE_SCOPE_FILTER=false -VERILOG_MODULE_SCOPE_FILTER=true -VERILOG_PACKAGE_SCOPE_FILTER=false -VERILOG_BLOCK_SCOPE_FILTER=false -VERILOG_TASK_SCOPE_FILTER=false -VERILOG_PROCESS_SCOPE_FILTER=false -INPUT_OBJECT_FILTER=true -OUTPUT_OBJECT_FILTER=true -INOUT_OBJECT_FILTER=true -INTERNAL_OBJECT_FILTER=true -CONSTANT_OBJECT_FILTER=true -VARIABLE_OBJECT_FILTER=true -SCOPE_NAME_COLUMN_WIDTH=75 -SCOPE_DESIGN_UNIT_COLUMN_WIDTH=75 -SCOPE_BLOCK_TYPE_COLUMN_WIDTH=75 -OBJECT_NAME_COLUMN_WIDTH=166 -OBJECT_VALUE_COLUMN_WIDTH=75 -OBJECT_DATA_TYPE_COLUMN_WIDTH=75 -PROCESS_NAME_COLUMN_WIDTH=75 -PROCESS_TYPE_COLUMN_WIDTH=75 -FRAME_INDEX_COLUMN_WIDTH=75 -FRAME_NAME_COLUMN_WIDTH=75 -FRAME_FILE_NAME_COLUMN_WIDTH=75 -FRAME_LINE_NUM_COLUMN_WIDTH=166 -LOCAL_NAME_COLUMN_WIDTH=75 -LOCAL_VALUE_COLUMN_WIDTH=75 -INPUT_LOCAL_FILTER=1 -OUTPUT_LOCAL_FILTER=1 -INOUT_LOCAL_FILTER=1 -INTERNAL_LOCAL_FILTER=1 -CONSTANT_LOCAL_FILTER=1 -VARIABLE_LOCAL_FILTER=1 diff --git a/RISC_V.sim/sim_1/behav/xsim/xsim.dir/RISC_V_IF_ID_TB_behav/xsimcrash.log b/RISC_V.sim/sim_1/behav/xsim/xsim.dir/RISC_V_IF_ID_TB_behav/xsimcrash.log deleted file mode 100644 index e69de29..0000000 diff --git a/RISC_V.sim/sim_1/behav/xsim/xsim.dir/RISC_V_IF_ID_TB_behav/xsimk.exe b/RISC_V.sim/sim_1/behav/xsim/xsim.dir/RISC_V_IF_ID_TB_behav/xsimk.exe deleted file mode 100644 index 59c6335..0000000 Binary files a/RISC_V.sim/sim_1/behav/xsim/xsim.dir/RISC_V_IF_ID_TB_behav/xsimk.exe and /dev/null differ diff --git a/RISC_V.sim/sim_1/behav/xsim/xsim.dir/RISC_V_IF_ID_TB_behav/xsimkernel.log b/RISC_V.sim/sim_1/behav/xsim/xsim.dir/RISC_V_IF_ID_TB_behav/xsimkernel.log deleted file mode 100644 index 3b04263..0000000 --- a/RISC_V.sim/sim_1/behav/xsim/xsim.dir/RISC_V_IF_ID_TB_behav/xsimkernel.log +++ /dev/null @@ -1,7 +0,0 @@ -Running: xsim.dir/RISC_V_IF_ID_TB_behav/xsimk.exe -simmode gui -wdb RISC_V_IF_ID_TB_behav.wdb -simrunnum 0 -socket 56344 -Design successfully loaded -Design Loading Memory Usage: 5248 KB (Peak: 5248 KB) -Design Loading CPU Usage: 15 ms -Simulation completed -Simulation Memory Usage: 6048 KB (Peak: 6048 KB) -Simulation CPU Usage: 30 ms diff --git a/RISC_V.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/@i@d.sdb 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a/RISC_V.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/adder.sdb and /dev/null differ diff --git a/RISC_V.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/glbl.sdb b/RISC_V.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/glbl.sdb deleted file mode 100644 index 6ab7b69..0000000 Binary files a/RISC_V.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/glbl.sdb and /dev/null differ diff --git a/RISC_V.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/imm_gen.sdb b/RISC_V.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/imm_gen.sdb deleted file mode 100644 index 15cabcf..0000000 Binary files a/RISC_V.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/imm_gen.sdb and /dev/null differ diff --git a/RISC_V.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/instruction_memory.sdb b/RISC_V.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/instruction_memory.sdb deleted file mode 100644 index 5b894e7..0000000 Binary files a/RISC_V.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/instruction_memory.sdb and /dev/null differ diff --git a/RISC_V.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/mux2_1.sdb b/RISC_V.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/mux2_1.sdb deleted file mode 100644 index d00a7a6..0000000 Binary files a/RISC_V.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/mux2_1.sdb and /dev/null differ diff --git a/RISC_V.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/registers.sdb b/RISC_V.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/registers.sdb deleted file mode 100644 index 03dd110..0000000 Binary files a/RISC_V.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/registers.sdb and /dev/null differ diff --git a/RISC_V.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx b/RISC_V.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx deleted file mode 100644 index cd5824e..0000000 --- a/RISC_V.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx +++ /dev/null @@ -1,16 +0,0 @@ -0.6 -2018.3 -Dec 7 2018 -00:33:28 -D:/VivadoProjects/RISC_V/RISC_V.sim/sim_1/behav/xsim/glbl.v,1544155481,verilog,,,,glbl,,,,,,,, -D:/VivadoProjects/RISC_V/RISC_V.srcs/sources_1/new/ID.v,1605529191,verilog,,D:/VivadoProjects/RISC_V/RISC_V.srcs/sources_1/new/IF.v,,ID,,,,,,,, -D:/VivadoProjects/RISC_V/RISC_V.srcs/sources_1/new/IF.v,1605531235,verilog,,D:/VivadoProjects/RISC_V/RISC_V.srcs/sources_1/new/IF_ID_REG.v,,IF,,,,,,,, -D:/VivadoProjects/RISC_V/RISC_V.srcs/sources_1/new/IF_ID_REG.v,1605531978,verilog,,D:/VivadoProjects/RISC_V/RISC_V.srcs/sources_1/new/PC.v,,IF_ID_REG,,,,,,,, -D:/VivadoProjects/RISC_V/RISC_V.srcs/sources_1/new/PC.v,1605531852,verilog,,D:/VivadoProjects/RISC_V/RISC_V.srcs/sources_1/new/RISC_V_IF_ID.v,,PC,,,,,,,, -D:/VivadoProjects/RISC_V/RISC_V.srcs/sources_1/new/RISC_V_IF_ID.v,1605529967,verilog,,D:/VivadoProjects/RISC_V/RISC_V.srcs/sources_1/new/adder.v,,RISC_V_IF_ID,,,,,,,, -D:/VivadoProjects/RISC_V/RISC_V.srcs/sources_1/new/RISC_V_IF_ID_TB.v,1605531978,verilog,,,,RISC_V_IF_ID_TB,,,,,,,, -D:/VivadoProjects/RISC_V/RISC_V.srcs/sources_1/new/adder.v,1605530932,verilog,,D:/VivadoProjects/RISC_V/RISC_V.srcs/sources_1/new/imm_gen.v,,adder,,,,,,,, -D:/VivadoProjects/RISC_V/RISC_V.srcs/sources_1/new/imm_gen.v,1605383352,verilog,,D:/VivadoProjects/RISC_V/RISC_V.srcs/sources_1/new/instruction_memory.v,,imm_gen,,,,,,,, -D:/VivadoProjects/RISC_V/RISC_V.srcs/sources_1/new/instruction_memory.v,1605475140,verilog,,D:/VivadoProjects/RISC_V/RISC_V.srcs/sources_1/new/mux2_1.v,,instruction_memory,,,,,,,, -D:/VivadoProjects/RISC_V/RISC_V.srcs/sources_1/new/mux2_1.v,1605535170,verilog,,D:/VivadoProjects/RISC_V/RISC_V.srcs/sources_1/new/registers.v,,mux2_1,,,,,,,, -D:/VivadoProjects/RISC_V/RISC_V.srcs/sources_1/new/registers.v,1605532387,verilog,,D:/VivadoProjects/RISC_V/RISC_V.srcs/sources_1/new/RISC_V_IF_ID_TB.v,,registers,,,,,,,, diff --git a/RISC_V.sim/sim_1/behav/xsim/xsim.ini b/RISC_V.sim/sim_1/behav/xsim/xsim.ini deleted file mode 100644 index e8199b2..0000000 --- a/RISC_V.sim/sim_1/behav/xsim/xsim.ini +++ /dev/null @@ -1 +0,0 @@ -xil_defaultlib=xsim.dir/xil_defaultlib diff --git a/RISC_V.sim/sim_1/behav/xsim/xvlog.log b/RISC_V.sim/sim_1/behav/xsim/xvlog.log deleted file mode 100644 index 02f1fbe..0000000 --- a/RISC_V.sim/sim_1/behav/xsim/xvlog.log +++ /dev/null @@ -1,25 +0,0 @@ -INFO: [VRFC 10-2263] Analyzing Verilog file "D:/VivadoProjects/RISC_V/RISC_V.srcs/sources_1/new/ID.v" into library xil_defaultlib -INFO: [VRFC 10-311] analyzing module ID -INFO: [VRFC 10-2263] Analyzing Verilog file "D:/VivadoProjects/RISC_V/RISC_V.srcs/sources_1/new/IF.v" into library xil_defaultlib -INFO: [VRFC 10-311] analyzing module IF -INFO: [VRFC 10-2263] Analyzing Verilog file "D:/VivadoProjects/RISC_V/RISC_V.srcs/sources_1/new/IF_ID_REG.v" into library xil_defaultlib -INFO: [VRFC 10-311] analyzing module IF_ID_REG -INFO: [VRFC 10-2263] Analyzing Verilog file "D:/VivadoProjects/RISC_V/RISC_V.srcs/sources_1/new/PC.v" into library xil_defaultlib -INFO: [VRFC 10-311] analyzing module PC -INFO: [VRFC 10-2263] Analyzing Verilog file "D:/VivadoProjects/RISC_V/RISC_V.srcs/sources_1/new/RISC_V_IF_ID.v" into library xil_defaultlib -INFO: [VRFC 10-311] analyzing module RISC_V_IF_ID -WARNING: [VRFC 10-3676] redeclaration of ansi port 'PC_ID' is not allowed [D:/VivadoProjects/RISC_V/RISC_V.srcs/sources_1/new/RISC_V_IF_ID.v:44] -INFO: [VRFC 10-2263] Analyzing Verilog file "D:/VivadoProjects/RISC_V/RISC_V.srcs/sources_1/new/adder.v" into library xil_defaultlib -INFO: [VRFC 10-311] analyzing module adder -INFO: [VRFC 10-2263] Analyzing Verilog file "D:/VivadoProjects/RISC_V/RISC_V.srcs/sources_1/new/imm_gen.v" into library xil_defaultlib -INFO: [VRFC 10-311] analyzing module imm_gen -INFO: [VRFC 10-2263] Analyzing Verilog file "D:/VivadoProjects/RISC_V/RISC_V.srcs/sources_1/new/instruction_memory.v" into library xil_defaultlib -INFO: [VRFC 10-311] analyzing module instruction_memory -INFO: [VRFC 10-2263] Analyzing Verilog file "D:/VivadoProjects/RISC_V/RISC_V.srcs/sources_1/new/mux2_1.v" into library xil_defaultlib -INFO: [VRFC 10-311] analyzing module mux2_1 -INFO: [VRFC 10-2263] Analyzing Verilog file "D:/VivadoProjects/RISC_V/RISC_V.srcs/sources_1/new/registers.v" into library xil_defaultlib -INFO: [VRFC 10-311] analyzing module registers -INFO: [VRFC 10-2263] Analyzing Verilog file "D:/VivadoProjects/RISC_V/RISC_V.srcs/sources_1/new/RISC_V_IF_ID_TB.v" into library xil_defaultlib -INFO: [VRFC 10-311] analyzing module RISC_V_IF_ID_TB -INFO: [VRFC 10-2263] Analyzing Verilog file "D:/VivadoProjects/RISC_V/RISC_V.sim/sim_1/behav/xsim/glbl.v" into library xil_defaultlib -INFO: [VRFC 10-311] analyzing module glbl diff --git a/RISC_V.sim/sim_1/behav/xsim/xvlog.pb b/RISC_V.sim/sim_1/behav/xsim/xvlog.pb deleted file mode 100644 index adec6b4..0000000 Binary files a/RISC_V.sim/sim_1/behav/xsim/xvlog.pb and /dev/null differ diff --git a/RISC_V.srcs/sources_1/new/.PC.v.swp b/RISC_V.srcs/sources_1/new/.PC.v.swp deleted file mode 100644 index 9290d31..0000000 Binary files a/RISC_V.srcs/sources_1/new/.PC.v.swp and /dev/null differ diff --git a/RISC_V.srcs/sources_1/new/.adder.v.swp b/RISC_V.srcs/sources_1/new/.adder.v.swp deleted file mode 100644 index 97e3cce..0000000 Binary files a/RISC_V.srcs/sources_1/new/.adder.v.swp and /dev/null differ diff --git a/RISC_V.srcs/sources_1/new/.imm_gen.v.swp b/RISC_V.srcs/sources_1/new/.imm_gen.v.swp deleted file mode 100644 index e68bcc4..0000000 Binary files a/RISC_V.srcs/sources_1/new/.imm_gen.v.swp and /dev/null differ diff --git a/RISC_V.srcs/sources_1/new/.mux2_1.v.swp b/RISC_V.srcs/sources_1/new/.mux2_1.v.swp deleted file mode 100644 index d79219a..0000000 Binary files a/RISC_V.srcs/sources_1/new/.mux2_1.v.swp and /dev/null differ diff --git a/RISC_V.srcs/sources_1/new/.registers.v.swp b/RISC_V.srcs/sources_1/new/.registers.v.swp deleted file mode 100644 index db7e03f..0000000 Binary files a/RISC_V.srcs/sources_1/new/.registers.v.swp and /dev/null differ diff --git a/RISC_V.srcs/sources_1/new/ID.v b/RISC_V.srcs/sources_1/new/ID.v deleted file mode 100644 index 48c73d6..0000000 --- a/RISC_V.srcs/sources_1/new/ID.v +++ /dev/null @@ -1,57 +0,0 @@ -`timescale 1ns / 1ps -////////////////////////////////////////////////////////////////////////////////// -// Company: -// Engineer: -// -// Create Date: 11/14/2020 08:22:59 PM -// Design Name: -// Module Name: ID -// Project Name: -// Target Devices: -// Tool Versions: -// Description: -// -// Dependencies: -// -// Revision: -// Revision 0.01 - File Created -// Additional Comments: -// -////////////////////////////////////////////////////////////////////////////////// - - -module ID(input clk, - input [31:0] PC_ID, INSTRUCTION_ID, // - input RegWrite_WB, // - input [31:0] ALU_DATA_WB, // - input [4:0] RD_WB, // - output [31:0] IMM_ID, // - output [31:0] REG_DATA1_ID, REG_DATA2_ID, // - output reg [2:0] FUNCT3_ID, // - output reg [6:0] FUNCT7_ID, // - output reg [6:0] OPCODE_ID, // - output reg [4:0] RD_ID, // - output reg [4:0] RS1_ID, // - output reg [4:0] RS2_ID); // - - always @(*) begin - OPCODE_ID <= INSTRUCTION_ID[6:0]; - RD_ID <= INSTRUCTION_ID[11:7]; - FUNCT3_ID <= INSTRUCTION_ID[14:12]; - RS1_ID <= INSTRUCTION_ID[19:15]; - RS2_ID <= INSTRUCTION_ID[24:20]; - FUNCT7_ID <= INSTRUCTION_ID[31:25]; - end - - registers reg0( - clk, - RegWrite_WB, - RS1_ID, - RS2_ID, - RD_WB, - ALU_DATA_WB, - REG_DATA1_ID, - REG_DATA2_ID - ); - imm_gen imm_gen0(INSTRUCTION_ID, IMM_ID); -endmodule diff --git a/RISC_V.srcs/sources_1/new/IF.v b/RISC_V.srcs/sources_1/new/IF.v deleted file mode 100644 index beca38d..0000000 --- a/RISC_V.srcs/sources_1/new/IF.v +++ /dev/null @@ -1,36 +0,0 @@ -`timescale 1ns / 1ps -////////////////////////////////////////////////////////////////////////////////// -// Company: -// Engineer: -// -// Create Date: 11/02/2020 02:02:33 PM -// Design Name: -// Module Name: IF -// Project Name: -// Target Devices: -// Tool Versions: -// Description: -// -// Dependencies: -// -// Revision: -// Revision 0.01 - File Created -// Additional Comments: -// -////////////////////////////////////////////////////////////////////////////////// - - -module IF(input clk, reset, - input PCSrc, PC_write, - input [31:0] PC_Branch, - output [31:0] PC_IF, INSTRUCTION_IF); - - wire [31:0] PC_4; - wire [31:0] PC_MUX; - - PC pc0(clk, reset, PC_write, PC_MUX, PC_IF); - instruction_memory instr_mem0(PC_IF[11:2], INSTRUCTION_IF); - adder adder0(PC_IF, 32'b0100, PC_4); - mux2_1 mux0(PC_4, PC_Branch, PCSrc, PC_MUX); - -endmodule diff --git a/RISC_V.srcs/sources_1/new/IF_ID_REG.v b/RISC_V.srcs/sources_1/new/IF_ID_REG.v deleted file mode 100644 index a6ba08b..0000000 --- a/RISC_V.srcs/sources_1/new/IF_ID_REG.v +++ /dev/null @@ -1,33 +0,0 @@ -`timescale 1ns / 1ps -////////////////////////////////////////////////////////////////////////////////// -// Company: -// Engineer: -// -// Create Date: 11/14/2020 09:49:56 PM -// Design Name: -// Module Name: IF_ID_REG -// Project Name: -// Target Devices: -// Tool Versions: -// Description: -// -// Dependencies: -// -// Revision: -// Revision 0.01 - File Created -// Additional Comments: -// -////////////////////////////////////////////////////////////////////////////////// - - -module IF_ID_REG(input clk, reset, write, - input [63:0] in, - output reg [63:0] out); - - always @(posedge clk) begin - if (write) - out <= in; - if (reset) - out <= 0; - end -endmodule diff --git a/RISC_V.srcs/sources_1/new/PC.v b/RISC_V.srcs/sources_1/new/PC.v deleted file mode 100644 index 40306e6..0000000 --- a/RISC_V.srcs/sources_1/new/PC.v +++ /dev/null @@ -1,34 +0,0 @@ -`timescale 1ns / 1ps -////////////////////////////////////////////////////////////////////////////////// -// Company: -// Engineer: -// -// Create Date: 11/02/2020 12:35:41 PM -// Design Name: -// Module Name: PC -// Project Name: -// Target Devices: -// Tool Versions: -// Description: -// -// Dependencies: -// -// Revision: -// Revision 0.01 - File Created -// Additional Comments: -// -////////////////////////////////////////////////////////////////////////////////// - - -module PC(input clk, res, write, - input [31:0] in, - output reg [31:0] out); - - always @(posedge clk) begin - if (write) - out <= in; - if (res) - out <= 32'b0; - end - -endmodule diff --git a/RISC_V.srcs/sources_1/new/RISC_V_IF_ID.v b/RISC_V.srcs/sources_1/new/RISC_V_IF_ID.v deleted file mode 100644 index a73349c..0000000 --- a/RISC_V.srcs/sources_1/new/RISC_V_IF_ID.v +++ /dev/null @@ -1,66 +0,0 @@ -`timescale 1ns / 1ps -////////////////////////////////////////////////////////////////////////////////// -// Company: -// Engineer: -// -// Create Date: 11/15/2020 01:26:31 PM -// Design Name: -// Module Name: RISC_V_IF_ID -// Project Name: -// Target Devices: -// Tool Versions: -// Description: -// -// Dependencies: -// -// Revision: -// Revision 0.01 - File Created -// Additional Comments: -// -////////////////////////////////////////////////////////////////////////////////// - - -module RISC_V_IF_ID(input clk, reset, - input IF_ID_write, - input PCSrc, PC_write, - input [31:0] PC_Branch, - input RegWrite_WB, - input [31:0] ALU_DATA_WB, - input [4:0] RD_WB, - output [31:0] PC_ID, - output [31:0] INSTRUCTION_ID, - output [31:0] IMM_ID, - output [31:0] REG_DATA1_ID, - output [31:0] REG_DATA2_ID, - output [2:0] FUNCT3_ID, - output [6:0] FUNCT7_ID, - output [6:0] OPCODE_ID, - output [4:0] RD_ID, - output [4:0] RS1_ID, - output [4:0] RS2_ID - ); - - wire [31:0] PC_IF, INSTRUCTION_IF; - wire [31:0] PC_ID, INSTRUCTION_ID; - - IF if0(clk, reset, PCSrc, PC_write, PC_Branch, PC_IF, INSTRUCTION_IF); - IF_ID_REG p0(clk, reset, IF_ID_write, {PC_IF, INSTRUCTION_IF}, {PC_ID, INSTRUCTION_ID}); - ID id0( - clk, - PC_ID, - INSTRUCTION_ID, - RegWrite_WB, - ALU_DATA_WB, - RD_WB, - IMM_ID, - REG_DATA1_ID, - REG_DATA2_ID, - FUNCT3_ID, - FUNCT7_ID, - OPCODE_ID, - RD_ID, - RS1_ID, - RS2_ID - ); - -endmodule diff --git a/RISC_V.srcs/sources_1/new/RISC_V_IF_ID_TB.v b/RISC_V.srcs/sources_1/new/RISC_V_IF_ID_TB.v deleted file mode 100644 index dc6a240..0000000 --- a/RISC_V.srcs/sources_1/new/RISC_V_IF_ID_TB.v +++ /dev/null @@ -1,57 +0,0 @@ -///////////////////////////////////////TESTBENCH////////////////////////////////////////////////////////////////// -module RISC_V_IF_ID_TB; - - reg clk,reset; - reg IF_ID_write; - reg PCSrc,PC_write; - reg [31:0] PC_Branch; - reg RegWrite_WB; - reg [31:0] ALU_DATA_WB; - reg [4:0] RD_WB; - wire [31:0] PC_ID; - wire [31:0] INSTRUCTION_ID; - wire [31:0] IMM_ID; - wire [31:0] REG_DATA1_ID,REG_DATA2_ID; - wire [2:0] FUNCT3_ID; - wire [6:0] FUNCT7_ID; - wire [6:0] OPCODE_ID; - wire [4:0] RD_ID; - wire [4:0] RS1_ID; - wire [4:0] RS2_ID; - - RISC_V_IF_ID procesor(clk,reset, - IF_ID_write, - PCSrc,PC_write, - PC_Branch, - RegWrite_WB, - ALU_DATA_WB, - RD_WB, - PC_ID, - INSTRUCTION_ID, - IMM_ID, - REG_DATA1_ID,REG_DATA2_ID, - FUNCT3_ID, - FUNCT7_ID, - OPCODE_ID, - RD_ID, - RS1_ID, - RS2_ID); - - always #5 clk=~clk; - - initial begin - #0 clk=1'b0; - reset=1'b1; - - IF_ID_write = 1'b1; - PCSrc = 1'b0; - PC_write = 1'b1; - PC_Branch = 32'b0; - RegWrite_WB = 1'b0; - ALU_DATA_WB = 32'b0; - RD_WB = 5'b0; - - #10 reset=1'b0; - #200 $finish; - end -endmodule \ No newline at end of file diff --git a/RISC_V.srcs/sources_1/new/imm_gen.v b/RISC_V.srcs/sources_1/new/imm_gen.v deleted file mode 100644 index 9372a16..0000000 --- a/RISC_V.srcs/sources_1/new/imm_gen.v +++ /dev/null @@ -1,35 +0,0 @@ -`timescale 1ns / 1ps -////////////////////////////////////////////////////////////////////////////////// -// Company: -// Engineer: -// -// Create Date: 11/09/2020 02:32:52 PM -// Design Name: -// Module Name: imm_gen -// Project Name: -// Target Devices: -// Tool Versions: -// Description: -// -// Dependencies: -// -// Revision: -// Revision 0.01 - File Created -// Additional Comments: -// -////////////////////////////////////////////////////////////////////////////////// - - -module imm_gen(input [31:0] in, output reg [31:0] out); - - always @(*) begin - casex ({in[14:12], in[6:0]}) - 10'bxxx0000011: out <= {{21{in[31]}}, in[30:20]}; // lw - 10'bxxx0010011: out <= {{21{in[31]}}, in[30:20]}; // addi, ori - 10'bxxx0100011: out <= {{21{in[31]}}, in[30:25], in[11:7]}; // sw - 10'bxxx1100011: out <= {{20{in[31]}}, in[7], in[30:25], in[11:8], 1'b0}; // beq - default: out <= 32'b0; - endcase - end - -endmodule diff --git a/RISC_V.srcs/sources_1/new/registers.v b/RISC_V.srcs/sources_1/new/registers.v deleted file mode 100644 index e21e054..0000000 --- a/RISC_V.srcs/sources_1/new/registers.v +++ /dev/null @@ -1,45 +0,0 @@ -`timescale 1ns / 1ps -////////////////////////////////////////////////////////////////////////////////// -// Company: -// Engineer: -// -// Create Date: 11/09/2020 02:10:45 PM -// Design Name: -// Module Name: registers -// Project Name: -// Target Devices: -// Tool Versions: -// Description: -// -// Dependencies: -// -// Revision: -// Revision 0.01 - File Created -// Additional Comments: -// -////////////////////////////////////////////////////////////////////////////////// - - -module registers(input clk, reg_write, - input [4:0] read_reg1, read_reg2, write_reg, - input [31:0] write_data, - output [31:0] read_data1, read_data2); - - reg [31:0] REG_FILE [0:31]; - integer i; - - initial begin - for (i = 0; i < 32; i = i + 1) begin - REG_FILE[i] <= i; - end - end - - always @(posedge clk) begin - if (reg_write && write_reg) - REG_FILE[write_reg] <= write_data; - end - - assign read_data1 = REG_FILE[read_reg1]; - assign read_data2 = REG_FILE[read_reg2]; - -endmodule diff --git a/RISC_V.xpr b/RISC_V.xpr deleted file mode 100644 index 975f789..0000000 --- a/RISC_V.xpr +++ /dev/null @@ -1,253 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - default_dashboard - - - - - - diff --git a/sim_1/new/code.mem b/sim_1/new/code.mem new file mode 100644 index 0000000..5c4571c --- /dev/null +++ b/sim_1/new/code.mem @@ -0,0 +1,7 @@ +00008133 //add x2,x1,x0 +00108093 //addi x1,x1,1 +0020F1B3 //and x3,x1,x2 +0010E213 //ori x4,x1,1 +0042A223 //sw x4,4(x5) +00802603 //lw x12,8(x0) +04090E63 //beq x18,x0,5c \ No newline at end of file diff --git a/sim_1/new/test_riscv.v b/sim_1/new/test_riscv.v new file mode 100644 index 0000000..03b2465 --- /dev/null +++ b/sim_1/new/test_riscv.v @@ -0,0 +1,27 @@ +///////////////////////////////////////TESTBENCH////////////////////////////////////////////////////////////////// +module RISC_V_TB; + reg clk,reset; + wire [31:0] PC_EX, ALU_OUT_EX, PC_MEM; + wire PCSrc; + wire [31:0] DATA_MEMORY_MEM; + wire [31:0] ALU_DATA_WB; + wire [1:0] forwardA, forwardB; + wire pipeline_stall; + + RISC_V_FINAL risc_v( + clk, reset, + + PC_EX,ALU_OUT_EX, PC_MEM, + PCSrc, DATA_MEMORY_MEM, ALU_DATA_WB, + forwardA, forwardB, pipeline_stall + ); + + always #5 clk=~clk; + + initial begin + #0 clk=1'b0; + reset=1'b1; + #10 reset=1'b0; + #105 $finish; + end +endmodule \ No newline at end of file diff --git a/sources_1/imports/IF_ID/PC.v b/sources_1/imports/IF_ID/PC.v new file mode 100644 index 0000000..26d8d87 --- /dev/null +++ b/sources_1/imports/IF_ID/PC.v @@ -0,0 +1,14 @@ +/////////////////////////////////////////PC_MODULE/////////////////////////////////////////////////////////////// +module PC(input clk,res,write, + input [31:0] in, + output reg [31:0] out); + + always@(posedge clk) begin + if(res) + out<=32'b0; + else if(write) + out<=in; + end + +endmodule +////////////////////////////////////////////////////////////////////////////////////////////////////////////// diff --git a/sources_1/imports/IF_ID/control_path.v b/sources_1/imports/IF_ID/control_path.v new file mode 100644 index 0000000..249851b --- /dev/null +++ b/sources_1/imports/IF_ID/control_path.v @@ -0,0 +1,23 @@ +////////////////////////////////////////CONTROL_PATH_MODULE/////////////////////////////////////////////////// +module control_path(input [6:0] opcode, + input control_sel, + output reg Branch, MemRead,MemtoReg,MemWrite,ALUSrc,RegWrite, + output reg [1:0] ALUop); + + always@(opcode) begin + if (control_sel) + {ALUSrc,MemtoReg,RegWrite,MemRead,MemWrite,Branch,ALUop} <= 8'b00000000; + else begin + casex(opcode) + 7'b0000000: {ALUSrc,MemtoReg,RegWrite,MemRead,MemWrite,Branch,ALUop} <= 8'b00000000; //nop from ISA + 7'b0000011: {ALUSrc,MemtoReg,RegWrite,MemRead,MemWrite,Branch,ALUop} <= 8'b11110000; //lw + 7'b0100011: {ALUSrc,MemtoReg,RegWrite,MemRead,MemWrite,Branch,ALUop} <= 8'b10001000; //sw + 7'b0110011: {ALUSrc,MemtoReg,RegWrite,MemRead,MemWrite,Branch,ALUop} <= 8'b00100010; //R32-format + 7'b0010011: {ALUSrc,MemtoReg,RegWrite,MemRead,MemWrite,Branch,ALUop} <= 8'b10100011; //Register32-Immediate Arithmetic Instructions + 7'b1100011: {ALUSrc,MemtoReg,RegWrite,MemRead,MemWrite,Branch,ALUop} <= 8'b00000101; //branch instructions + endcase + end + end + +endmodule +////////////////////////////////////////////////////////////////////////////////////////////////////////////// diff --git a/sources_1/imports/IF_ID/if_id_pipe.v b/sources_1/imports/IF_ID/if_id_pipe.v new file mode 100644 index 0000000..709f488 --- /dev/null +++ b/sources_1/imports/IF_ID/if_id_pipe.v @@ -0,0 +1,23 @@ +module IF_ID_reg(clk,reset,write,pc_in,instruction_in,pc_out,instruction_out); + + input clk,write,reset; + input [31:0] pc_in; + input [31:0] instruction_in; + + output reg [31:0] pc_out; + output reg [31:0] instruction_out; + + always@(posedge clk) begin + if (reset) begin + pc_out<=32'b0; + instruction_out<=32'b0; + end + else begin + if(write) begin + pc_out <= pc_in; + instruction_out <= instruction_in; + end + end + end + +endmodule diff --git a/sources_1/imports/IF_ID/imm_gen.v b/sources_1/imports/IF_ID/imm_gen.v new file mode 100644 index 0000000..c3c06a6 --- /dev/null +++ b/sources_1/imports/IF_ID/imm_gen.v @@ -0,0 +1,22 @@ +//////////////////////////////////////////IMM_GEN_MODULE///////////////////////////////////////////////////// +module imm_gen(input [31:0] in, + output reg [31:0] out); + + always@(*) begin + casex({in[14:12],in[6:0]}) + 10'bxxx0000011: out <= {{20{in[31]}},in[31:20]}; //load instructions + 10'b0000010011: out <= {{20{in[31]}},in[31:20]}; //addi + 10'b1110010011: out <= {{20{in[31]}},in[31:20]}; //andi + 10'b1100010011: out <= {{20{in[31]}},in[31:20]}; //ori + 10'b1000010011: out <= {{20{in[31]}},in[31:20]}; //xori + 10'b0100010011: out <= {{20{in[31]}},in[31:20]}; //slti + 10'b0110010011: out <= {{20{in[31]}},in[31:20]}; //sltiu + 10'b1010010011: out <= {27'b0,in[24:20]}; //srli,srai + 10'b0010010011: out <= {27'b0,in[24:20]}; //slli + 10'bxxx0100011: out <= {{20{in[31]}},in[31:25],in[11:7]}; //store instructions + 10'bxxx1100011: out <= {{19{in[31]}},in[31],in[7],in[30:25],in[11:8], 1'b0}; //beq,bne,blt,bge,bltu,bgeu + default: out <= 32'b0; + endcase + end +endmodule +////////////////////////////////////////////////////////////////////////////////////////////////////////////// diff --git a/sources_1/imports/IF_ID/instruction_memory.v b/sources_1/imports/IF_ID/instruction_memory.v new file mode 100644 index 0000000..a72cabc --- /dev/null +++ b/sources_1/imports/IF_ID/instruction_memory.v @@ -0,0 +1,14 @@ +///////////////////////////////////////INSTRUCTION_MEMORY///////////////////////////////////////////////////// +module instruction_memory(input [9:0] address, + output reg [31:0] instruction); + + reg [31:0] codeMemory [0:1023]; + + initial $readmemh("code.mem", codeMemory); + + always@(address) begin + instruction <= codeMemory[address]; + end + +endmodule +////////////////////////////////////////////////////////////////////////////////////////////////////////////// diff --git a/sources_1/imports/IF_ID/registers.v b/sources_1/imports/IF_ID/registers.v new file mode 100644 index 0000000..bb3b21e --- /dev/null +++ b/sources_1/imports/IF_ID/registers.v @@ -0,0 +1,30 @@ +///////////////////////////////////REGISTER_FILE_MODULE/////////////////////////////////////////////////////// +module registers(input clk,reg_write, + input [4:0] read_reg1,read_reg2,write_reg, + input [31:0] write_data, + output [31:0] read_data1,read_data2); + + reg [31:0] Registers [0:31]; + + integer i; + initial begin + for (i = 0; i < 32; i = i + 1) begin + Registers[i] = i; + end + end + + always@(posedge clk) begin + if(reg_write && write_reg) + Registers[write_reg] <= write_data; + end + + assign read_data1 = (read_reg1 != 5'b0) ? //it is different from x0 + (((reg_write == 1'b1)&&(read_reg1 == write_reg)) ? + write_data : Registers[read_reg1]) : 32'b0; + + assign read_data2 = (read_reg2 != 5'b0) ? //it is different from x0 + (((reg_write == 1'b1)&&(read_reg2 == write_reg)) ? + write_data : Registers[read_reg2]) : 32'b0; + +endmodule +////////////////////////////////////////////////////////////////////////////////////////////////////////////// diff --git a/sources_1/imports/IF_ID/risc_v.v b/sources_1/imports/IF_ID/risc_v.v new file mode 100644 index 0000000..d966f24 --- /dev/null +++ b/sources_1/imports/IF_ID/risc_v.v @@ -0,0 +1,77 @@ +//////////////////////////////////////////////RISC-V_MODULE/////////////////////////////////////////////////// +module RISC_V_IF_ID(input clk, + input reset, + input control_sel, + + input IF_ID_write, + input PCSrc,PC_write, + input [31:0] PC_Branch, + input RegWrite_WB, + input [31:0] ALU_DATA_WB, + input [4:0] RD_WB, + + output [31:0] PC_ID, + output [31:0] INSTRUCTION_ID, + output [31:0] IMM_ID, + output [31:0] REG_DATA1_ID, + output [31:0] REG_DATA2_ID, + + output [2:0] FUNCT3_ID, + output [6:0] FUNCT7_ID, + output [6:0] OPCODE_ID, + output [4:0] RD_ID, + output [4:0] RS1_ID, + output [4:0] RS2_ID, + + output RegWrite_ID, + output MemtoReg_ID, + output MemRead_ID, + output MemWrite_ID, + output [1:0] ALUop_ID, + output ALUSrc_ID, + output Branch_ID + ); + + //////////////////////////////////////////IF signals//////////////////////////////////////////////////////// + wire [31:0] PC_IF; + wire [31:0] INSTRUCTION_IF; + + + /////////////////////////////////////IF Module///////////////////////////////////// + IF instruction_fetch(clk, reset, + PCSrc, PC_write, + PC_Branch, + PC_IF,INSTRUCTION_IF); + + + //////////////////////////////////////pipeline registers//////////////////////////////////////////////////// + IF_ID_reg IF_ID_REGISTER(clk,reset, + IF_ID_write, + PC_IF,INSTRUCTION_IF, + PC_ID,INSTRUCTION_ID); + + + ////////////////////////////////////////ID Module////////////////////////////////// + ID instruction_decode(clk, + control_sel, + PC_ID,INSTRUCTION_ID, + RegWrite_WB, + ALU_DATA_WB, + RD_WB, + IMM_ID, + REG_DATA1_ID,REG_DATA2_ID, + FUNCT3_ID, + FUNCT7_ID, + OPCODE_ID, + RD_ID, + RS1_ID, + RS2_ID, + RegWrite_ID, + MemtoReg_ID, + MemRead_ID, + MemWrite_ID, + ALUop_ID, + ALUSrc_ID, + Branch_ID); +endmodule +/////////////////////////////////////////////////////////////////////////////////////////////////////////////////// diff --git a/sources_1/new/ALU.v b/sources_1/new/ALU.v new file mode 100644 index 0000000..5ed82ba --- /dev/null +++ b/sources_1/new/ALU.v @@ -0,0 +1,38 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 12/07/2020 01:33:07 PM +// Design Name: +// Module Name: ALU +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + +module ALU(input [3:0] ALUinput, + input [31:0] ina,inb, + output reg zero, + output reg [31:0] out); + + always @(ina or inb or ALUinput) begin + case(ALUinput) + 4'b0010: out = ina + inb; + 4'b0110: out = ina - inb; + 4'b0000: out = ina & inb; + 4'b0001: out = ina | inb; + default: out = 32'hFFFFFFFF; + endcase + zero <= (out == 0); + end +endmodule + diff --git a/sources_1/new/ALUcontrol.v b/sources_1/new/ALUcontrol.v new file mode 100644 index 0000000..5cbfaa8 --- /dev/null +++ b/sources_1/new/ALUcontrol.v @@ -0,0 +1,42 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 12/07/2020 12:38:23 PM +// Design Name: +// Module Name: ALUcontrol +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module ALUcontrol(input [1:0] ALUop, + input [6:0] funct7, + input [2:0] funct3, + output reg [3:0] ALUinput); + + always @(ALUop or funct7 or funct3) begin + casex({ALUop, funct7, funct3}) + 12'b00XXXXXXXXXX: ALUinput <= 4'b0010; // ld, sd + 12'b01XXXXXXXXXX: ALUinput <= 4'b0110; // beq + 12'b100000000000: ALUinput <= 4'b0010; // add + 12'b100100000000: ALUinput <= 4'b0110; // sub + 12'b100000000111: ALUinput <= 4'b0000; // and + 12'b100000000110: ALUinput <= 4'b0001; // or + 12'b11xxxxxxx000: ALUinput <= 4'b0010; // addi + 12'b11xxxxxxx110: ALUinput <= 4'b0001; // ori + default: ALUinput <= 4'b1111; + endcase + end + +endmodule diff --git a/sources_1/new/ALUop.v b/sources_1/new/ALUop.v new file mode 100644 index 0000000..ad4387b --- /dev/null +++ b/sources_1/new/ALUop.v @@ -0,0 +1,37 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 12/07/2020 12:54:36 PM +// Design Name: +// Module Name: ALUop +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module ALU(input [3:0] ALUop, + input [31:0] ina,inb, + output reg zero, + output reg [31:0] out); + + always @(ina or inb or ALUop) begin + case(ALUop) + 4'b0010: out <= ina + inb; + 4'b0110: out <= ina - inb; + 4'b0000: out <= ina & inb; + 4'b0001: out <= ina | inb; + endcase + zero <= (out == 0); + end +endmodule diff --git a/sources_1/new/EX.v b/sources_1/new/EX.v new file mode 100644 index 0000000..8d9c790 --- /dev/null +++ b/sources_1/new/EX.v @@ -0,0 +1,61 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 12/07/2020 01:02:51 PM +// Design Name: +// Module Name: EX +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module EX(input [31:0] IMM_EX, + input [31:0] REG_DATA1_EX, + input [31:0] REG_DATA2_EX, + input [31:0] PC_EX, + input [2:0] FUNCT3_EX, + input [6:0] FUNCT7_EX, + input [4:0] RD_EX, + input [4:0] RS1_EX, + input [4:0] RS2_EX, + input RegWrite_EX, + input MemtoReg_EX, + input MemRead_EX, + input MemWrite_EX, + input [1:0] ALUop_EX, + input ALUSrc_EX, + input Branch_EX, + input [1:0] forwardA,forwardB, + + input [31:0] ALU_DATA_WB, + input [31:0] ALU_OUT_MEM, + + output ZERO_EX, + output [31:0] ALU_OUT_EX, + output [31:0] PC_Branch_EX, + output [31:0] REG_DATA2_EX_FINAL + ); + + wire [3:0] ALUinput; + wire [31:0] ALU_OP_1, ALU_OP_2; + + mux4_1 mux0(REG_DATA1_EX, ALU_DATA_WB, ALU_OUT_MEM, 0, forwardA, ALU_OP_1); + mux4_1 mux1(REG_DATA2_EX, ALU_DATA_WB, ALU_OUT_MEM, 0, forwardB, REG_DATA2_EX_FINAL); + mux2_1 mux2(REG_DATA2_EX_FINAL, IMM_EX, ALUSrc_EX, ALU_OP_2); + + ALUcontrol control0(ALUop_EX, FUNCT7_EX, FUNCT3_EX, ALUinput); + ALU alu0(ALUinput, ALU_OP_1, ALU_OP_2, ZERO_EX, ALU_OUT_EX); + + adder adder0(PC_EX, IMM_EX, PC_Branch_EX); +endmodule diff --git a/sources_1/new/EX_MEM_REG.v b/sources_1/new/EX_MEM_REG.v new file mode 100644 index 0000000..ec79207 --- /dev/null +++ b/sources_1/new/EX_MEM_REG.v @@ -0,0 +1,68 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 01/03/2021 01:19:39 PM +// Design Name: +// Module Name: EX_MEM_REG +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module EX_MEM_REG( + output reg [4:0] RD_MEM, + output reg RegWrite_MEM, + output reg MemtoReg_MEM, + output reg MemRead_MEM, + output reg MemWrite_MEM, + output reg Branch_MEM, + output reg Zero_MEM, + output reg [31:0] ALU_OUT_MEM, + output reg [31:0] PC_Branch_MEM, + output reg [31:0] REG_DATA2_MEM_FINAL, + + input [4:0] RD_EX, + input RegWrite_EX, + input MemtoReg_EX, + input MemRead_EX, + input MemWrite_EX, + input Branch_EX, + input Zero_EX, + input [31:0] ALU_OUT_EX, + input [31:0] PC_Branch_EX, + input [31:0] REG_DATA2_EX_FINAL, + + input clk, + input reset +); + + always @(posedge clk) begin + if (reset) begin + {RD_MEM, RegWrite_MEM, MemtoReg_MEM, MemRead_MEM, MemWrite_MEM, + Branch_MEM, Zero_MEM, ALU_OUT_MEM, PC_Branch_MEM, REG_DATA2_MEM_FINAL} = 107'b0; + end + else begin + RD_MEM = RD_EX; + RegWrite_MEM = RegWrite_EX; + MemtoReg_MEM = MemtoReg_EX; + MemRead_MEM = MemRead_EX; + MemWrite_MEM = MemWrite_EX; + Branch_MEM = Branch_EX; + Zero_MEM = Zero_EX; + ALU_OUT_MEM = ALU_OUT_EX; + PC_Branch_MEM = PC_Branch_EX; + REG_DATA2_MEM_FINAL = REG_DATA2_EX_FINAL; + end + end +endmodule diff --git a/sources_1/new/ID.v b/sources_1/new/ID.v new file mode 100644 index 0000000..0dfb1eb --- /dev/null +++ b/sources_1/new/ID.v @@ -0,0 +1,43 @@ +module ID(input clk, + input control_sel, + input [31:0] PC_ID,INSTRUCTION_ID, + input RegWrite_WB, + input [31:0] ALU_DATA_WB, + input [4:0] RD_WB, + output [31:0] IMM_ID, + output [31:0] REG_DATA1_ID,REG_DATA2_ID, + output [2:0] FUNCT3_ID, + output [6:0] FUNCT7_ID, + output [6:0] OPCODE_ID, + output [4:0] RD_ID, + output [4:0] RS1_ID, + output [4:0] RS2_ID, + output RegWrite_ID,MemtoReg_ID,MemRead_ID,MemWrite_ID, + output [1:0] ALUop_ID, + output ALUSrc_ID, + output Branch_ID); + + + assign FUNCT3_ID = INSTRUCTION_ID[14:12]; + assign FUNCT7_ID = INSTRUCTION_ID[31:25]; + assign OPCODE_ID = INSTRUCTION_ID[6:0]; + assign RD_ID = INSTRUCTION_ID[11:7]; + assign RS1_ID = INSTRUCTION_ID[19:15]; + assign RS2_ID = INSTRUCTION_ID[24:20]; + + control_path CONTROL_PATH_MODULE(OPCODE_ID, + control_sel, + Branch_ID,MemRead_ID,MemtoReg_ID, + MemWrite_ID,ALUSrc_ID,RegWrite_ID, + ALUop_ID); + + registers REGISTER_FILE_MODULE(clk,RegWrite_WB, + RS1_ID, + RS2_ID, + RD_WB, + ALU_DATA_WB, + REG_DATA1_ID,REG_DATA2_ID); + + imm_gen IMM_GEN_MODULE(INSTRUCTION_ID,IMM_ID); + +endmodule \ No newline at end of file diff --git a/sources_1/new/ID_EX_REG.v b/sources_1/new/ID_EX_REG.v new file mode 100644 index 0000000..1603088 --- /dev/null +++ b/sources_1/new/ID_EX_REG.v @@ -0,0 +1,105 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 01/03/2021 03:09:26 PM +// Design Name: +// Module Name: ID_EX_REG +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module ID_EX_REG( + output reg [31:0] PC_EX, + output reg [31:0] IMM_EX, + output reg [31:0] REG_DATA1_EX, + output reg [31:0] REG_DATA2_EX, + output reg [2:0] FUNCT3_EX, + output reg [6:0] FUNCT7_EX, + output reg [6:0] OPCODE_EX, + output reg [4:0] RD_EX, + output reg [4:0] RS1_EX, + output reg [4:0] RS2_EX, + output reg RegWrite_EX, + output reg MemtoReg_EX, + output reg MemRead_EX, + output reg MemWrite_EX, + output reg [1:0] ALUop_EX, + output reg ALUSrc_EX, + output reg Branch_EX, + + input [31:0] PC_ID, + input [31:0] IMM_ID, + input [31:0] REG_DATA1_ID, + input [31:0] REG_DATA2_ID, + input [2:0] FUNCT3_ID, + input [6:0] FUNCT7_ID, + input [6:0] OPCODE_ID, + input [4:0] RD_ID, + input [4:0] RS1_ID, + input [4:0] RS2_ID, + input RegWrite_ID, + input MemtoReg_ID, + input MemRead_ID, + input MemWrite_ID, + input [1:0] ALUop_ID, + input ALUSrc_ID, + input Branch_ID, + + input clk, + input reset +); + + always @(posedge clk) begin + if (reset) begin + PC_EX = 0; + IMM_EX = 0; + REG_DATA1_EX = 0; + REG_DATA2_EX = 0; + FUNCT3_EX = 0; + FUNCT7_EX = 0; + OPCODE_EX = 0; + RD_EX = 0; + RS1_EX = 0; + RS2_EX = 0; + RegWrite_EX = 0; + MemtoReg_EX = 0; + MemRead_EX = 0; + MemWrite_EX = 0; + ALUop_EX = 0; + ALUSrc_EX = 0; + Branch_EX = 0; + end + else begin + PC_EX = PC_ID; + IMM_EX = IMM_ID; + REG_DATA1_EX = REG_DATA1_ID; + REG_DATA2_EX = REG_DATA2_ID; + FUNCT3_EX = FUNCT3_ID; + FUNCT7_EX = FUNCT7_ID; + OPCODE_EX = OPCODE_ID; + RD_EX = RD_ID; + RS1_EX = RS1_ID; + RS2_EX = RS2_ID; + RegWrite_EX = RegWrite_ID; + MemtoReg_EX = MemtoReg_ID; + MemRead_EX = MemRead_ID; + MemWrite_EX = MemWrite_ID; + ALUop_EX = ALUop_ID; + ALUSrc_EX = ALUSrc_ID; + Branch_EX = Branch_ID; + end + end + +endmodule diff --git a/sources_1/new/IF.v b/sources_1/new/IF.v new file mode 100644 index 0000000..747b65b --- /dev/null +++ b/sources_1/new/IF.v @@ -0,0 +1,22 @@ +module IF(input clk, reset, + input PCSrc, PC_write, + input [31:0] PC_Branch, + output [31:0] PC_IF,INSTRUCTION_IF); + + wire [9:0] instruction_address = PC_IF[11:2]; + wire [31:0] PC_MUX; + wire [31:0] PC_4_IF; + + PC PC_MODULE(clk,reset,PC_write,PC_MUX,PC_IF); + + instruction_memory INSTRUCTION_MEMORY_MODULE(instruction_address,INSTRUCTION_IF); + + adder ADDER_PC_4_IF(PC_IF,32'b0100,PC_4_IF); + + mux2_1 MUX_PC(PC_4_IF, + PC_Branch, + PCSrc, + PC_MUX); + + +endmodule diff --git a/sources_1/new/MEM.v b/sources_1/new/MEM.v new file mode 100644 index 0000000..4f7def3 --- /dev/null +++ b/sources_1/new/MEM.v @@ -0,0 +1,57 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 01/03/2021 01:51:54 PM +// Design Name: +// Module Name: MEM +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module MEM( + input clk, + input [4:0] RD_MEM, + input RegWrite_MEM, + input MemtoReg_MEM, + input MemRead_MEM, + input MemWrite_MEM, + input Branch_MEM, + + input Zero_MEM, + input [31:0] ALU_OUT_MEM, + input [31:0] PC_Branch_MEM, + input [31:0] REG_DATA2_MEM_FINAL, + + output reg PCSrc_IF, + output reg [31:0] PC_Branch_IF, + + output [31:0] READ_DATA +); + + data_memory data_memory0( + clk, + MemRead_MEM, + MemWrite_MEM, + ALU_OUT_MEM, + REG_DATA2_MEM_FINAL, + READ_DATA + ); + + always @(Zero_MEM or Branch_MEM or PC_Branch_MEM) begin + PCSrc_IF = Zero_MEM & Branch_MEM; + PC_Branch_IF = PC_Branch_MEM; + end + +endmodule diff --git a/sources_1/new/MEM_WB_REG.v b/sources_1/new/MEM_WB_REG.v new file mode 100644 index 0000000..ba1d896 --- /dev/null +++ b/sources_1/new/MEM_WB_REG.v @@ -0,0 +1,50 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 01/03/2021 02:22:35 PM +// Design Name: +// Module Name: MEM_WB_REG +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module MEM_WB_REG( + output reg MemtoReg_WB, + output reg RegWrite_WB, + output reg [31:0] READ_DATA_WB, + output reg [31:0] ALU_RESULT_WB, + output reg [4:0] RD_WB, + + input MemtoReg_MEM, + input RegWrite_MEM, + input [31:0] READ_DATA_MEM, + input [31:0] ALU_RESULT_MEM, + input [4:0] RD_MEM, + + input clk, + input reset +); + always @(posedge clk) begin + if (reset) + {MemtoReg_WB, RegWrite_WB, READ_DATA_WB, ALU_RESULT_WB, RD_WB} = 71'b0; + else begin + MemtoReg_WB = MemtoReg_MEM; + RegWrite_WB = RegWrite_MEM; + READ_DATA_WB = READ_DATA_MEM; + ALU_RESULT_WB = ALU_RESULT_MEM; + RD_WB = RD_MEM; + end + end +endmodule diff --git a/sources_1/new/RISC_V_FINAL.v b/sources_1/new/RISC_V_FINAL.v new file mode 100644 index 0000000..8831c78 --- /dev/null +++ b/sources_1/new/RISC_V_FINAL.v @@ -0,0 +1,215 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 01/03/2021 02:45:33 PM +// Design Name: +// Module Name: RISC_V_FINAL +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + +module RISC_V_FINAL( + input clk, + input reset, + + output [31:0] PC_EX, + output [31:0] ALU_OUT_EX, + output [31:0] PC_MEM, + output PCSrc, + output [31:0] DATA_MEMORY_MEM, + output [31:0] ALU_DATA_WB, + output [1:0] forwardA, forwardB, + output pipeline_stall + ); + + wire IF_ID_write; + wire PC_write; + + wire [31:0] PC_ID; + wire [31:0] INSTRUCTION_ID; + wire [31:0] IMM_ID; + wire [31:0] REG_DATA1_ID; + wire [31:0] REG_DATA2_ID; + wire [2:0] FUNCT3_ID; + wire [6:0] FUNCT7_ID; + wire [6:0] OPCODE_ID; + wire [4:0] RD_ID; + wire [4:0] RS1_ID; + wire [4:0] RS2_ID; + + wire RegWrite_ID; + wire MemtoReg_ID; + wire MemRead_ID; + wire MemWrite_ID; + wire [1:0] ALUop_ID; + wire ALUSrc_ID; + wire Branch_ID; + + wire [31:0] IMM_EX; + wire [31:0] REG_DATA1_EX; + wire [31:0] REG_DATA2_EX; + wire [2:0] FUNCT3_EX; + wire [6:0] FUNCT7_EX; + wire [6:0] OPCODE_EX; + wire [4:0] RD_EX; + wire [4:0] RS1_EX; + wire [4:0] RS2_EX; + + wire RegWrite_EX; + wire MemtoReg_EX; + wire MemRead_EX; + wire MemWrite_EX; + wire [1:0] ALUop_EX; + wire ALUSrc_EX; + wire Branch_EX; + + wire ZERO_EX; + wire [31:0] PC_Branch_EX; + wire [31:0] REG_DATA2_EX_FINAL; + + wire [4:0] RD_MEM; + wire RegWrite_MEM; + wire MemtoReg_MEM; + wire MemRead_MEM; + wire MemWrite_MEM; + wire Branch_MEM; + + wire ZERO_MEM; + wire [31:0] ALU_OUT_MEM; + wire [31:0] PC_Branch_MEM; + wire [31:0] REG_DATA2_MEM_FINAL; + + wire [4:0] RD_WB; + wire RegWrite_WB; + wire MemtoReg_WB; + wire [31:0] ALU_OUT_WB; + wire [31:0] DATA_MEMORY_WB; + + RISC_V_IF_ID if_id( + clk, reset, pipeline_stall, + IF_ID_write, PCSrc, PC_write, + PC_MEM, RegWrite_WB, ALU_DATA_WB, RD_WB, + + PC_ID, INSTRUCTION_ID, IMM_ID, + REG_DATA1_ID, REG_DATA2_ID, + + FUNCT3_ID, FUNCT7_ID, OPCODE_ID, + RD_ID, RS1_ID, RS2_ID, + + RegWrite_ID, + MemtoReg_ID, + MemRead_ID, + MemWrite_ID, + ALUop_ID, + ALUSrc_ID, + Branch_ID + ); + + hazard_detection hazard(RD_EX, RS1_ID, RS2_ID, MemRead_EX, PC_write, IF_ID_write, pipeline_stall); + + ID_EX_REG id_ex_reg( + PC_EX, IMM_EX, REG_DATA1_EX, + REG_DATA2_EX, FUNCT3_EX, FUNCT7_EX, + OPCODE_EX, RD_EX, RS1_EX, RS2_EX, + + RegWrite_EX, MemtoReg_EX, + MemRead_EX, MemWrite_EX, ALUop_EX, + ALUSrc_EX, Branch_EX, + + PC_ID, IMM_ID, REG_DATA1_ID, + REG_DATA2_ID, FUNCT3_ID, FUNCT7_ID, + OPCODE_ID, RD_ID, RS1_ID, RS2_ID, + + RegWrite_ID, MemtoReg_ID, + MemRead_ID, MemWrite_ID, ALUop_ID, + ALUSrc_ID, Branch_ID, + + clk, reset + ); + + forwarding forward( + RS1_EX, + RS2_EX, + RD_MEM, + RD_WB, + RegWrite_MEM, + RegWrite_WB, + forwardA, forwardB + ); + + EX ex( + IMM_EX, REG_DATA1_EX, REG_DATA2_EX, + PC_EX, FUNCT3_EX, FUNCT7_EX, + RD_EX, RS1_EX, RS2_EX, + + RegWrite_EX, MemtoReg_EX, MemRead_EX, + MemWrite_EX, ALUop_EX, ALUSrc_EX, + Branch_EX, + + forwardA, forwardB, + + ALU_DATA_WB, + ALU_OUT_MEM, + + ZERO_EX, + ALU_OUT_EX, + PC_Branch_EX, + REG_DATA2_EX_FINAL + ); + + EX_MEM_REG ex_mem_reg( + RD_MEM, RegWrite_MEM, MemtoReg_MEM, + MemRead_MEM, MemWrite_MEM, Branch_MEM, + + ZERO_MEM, ALU_OUT_MEM, PC_Branch_MEM, + REG_DATA2_MEM_FINAL, + + RD_EX, RegWrite_EX, MemtoReg_EX, + MemRead_EX, MemWrite_EX, Branch_EX, + + ZERO_EX, ALU_OUT_EX, PC_Branch_EX, + REG_DATA2_EX_FINAL, + + clk, reset + ); + + MEM mem(clk, + RD_MEM, RegWrite_MEM, MemtoReg_MEM, + MemRead_MEM, MemWrite_MEM, Branch_MEM, + + ZERO_MEM, ALU_OUT_MEM, PC_Branch_MEM, + REG_DATA2_MEM_FINAL, + + PCSrc, PC_MEM, + + DATA_MEMORY_MEM + ); + + MEM_WB_REG mem_wb_reg( + MemtoReg_WB, RegWrite_WB, DATA_MEMORY_WB, + ALU_OUT_WB, RD_WB, + + MemtoReg_MEM, RegWrite_MEM, DATA_MEMORY_MEM, + ALU_OUT_MEM, RD_MEM, + + clk, reset + ); + + WB wb( + MemtoReg_WB, DATA_MEMORY_WB, + ALU_OUT_WB, + + ALU_DATA_WB + ); +endmodule diff --git a/sources_1/new/WB.v b/sources_1/new/WB.v new file mode 100644 index 0000000..58eef70 --- /dev/null +++ b/sources_1/new/WB.v @@ -0,0 +1,11 @@ +module WB( + input MemtoReg_WB, + input [31:0] READ_DATA_WB, + input [31:0] ALU_RESULT_WB, + + output [31:0] ALU_DATA_WB +); + + mux2_1 mux0(ALU_RESULT_WB, READ_DATA_WB, MemtoReg_WB, ALU_DATA_WB); + +endmodule diff --git a/RISC_V.srcs/sources_1/new/adder.v b/sources_1/new/adder.v similarity index 74% rename from RISC_V.srcs/sources_1/new/adder.v rename to sources_1/new/adder.v index feccb26..1dc51e9 100644 --- a/RISC_V.srcs/sources_1/new/adder.v +++ b/sources_1/new/adder.v @@ -3,7 +3,7 @@ // Company: // Engineer: // -// Create Date: 11/02/2020 01:47:57 PM +// Create Date: 12/14/2020 02:13:52 PM // Design Name: // Module Name: adder // Project Name: @@ -20,9 +20,6 @@ ////////////////////////////////////////////////////////////////////////////////// -module adder(input [31:0] ina, inb, - output [31:0] out); - - assign out = ina + inb; - +module adder(input [31:0] ina, input [31:0] inb, output reg [31:0] out); + always @(ina or inb) out = ina + inb; endmodule diff --git a/sources_1/new/data_memory.v b/sources_1/new/data_memory.v new file mode 100644 index 0000000..e75767f --- /dev/null +++ b/sources_1/new/data_memory.v @@ -0,0 +1,49 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 12/14/2020 02:30:26 PM +// Design Name: +// Module Name: data_memory +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module data_memory(input clk, + input mem_read, + input mem_write, + input [31:0] address, + input [31:0] write_data, + output reg [31:0] read_data + ); + + reg [31:0] RAM [0:1023]; + integer i; + + initial begin + for (i = 0; i < 1024; i = i + 1) + RAM[i] = i; + end + + always @(posedge clk) begin + if (mem_write) + RAM[address] <= write_data; + end + + always @* begin + if (mem_read) + read_data <= RAM[address]; + end + +endmodule diff --git a/sources_1/new/forwarding.v b/sources_1/new/forwarding.v new file mode 100644 index 0000000..c0141db --- /dev/null +++ b/sources_1/new/forwarding.v @@ -0,0 +1,46 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 12/14/2020 03:02:08 PM +// Design Name: +// Module Name: forwarding +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module forwarding(input [4:0] rs1, + input [4:0] rs2, + input [4:0] ex_mem_rd, + input [4:0] mem_wb_rd, + input ex_mem_regwrite, + input mem_wb_regwrite, + output reg [1:0] forwardA,forwardB); + + always @(rs1 or rs2 or ex_mem_rd or mem_wb_rd or ex_mem_regwrite or mem_wb_regwrite) begin + forwardA <= 2'b00; + forwardB <= 2'b00; + + if (ex_mem_regwrite && ex_mem_rd != 0 && ex_mem_rd == rs1) + forwardA <= 2'b10; + if (ex_mem_regwrite && ex_mem_rd != 0 && ex_mem_rd == rs2) + forwardB <= 2'b10; + + if (mem_wb_regwrite && mem_wb_rd != 0 && !(ex_mem_regwrite && ex_mem_rd != 0 && ex_mem_rd == rs1) && mem_wb_rd == rs1) + forwardA <= 2'b01; + if (mem_wb_regwrite && mem_wb_rd != 0 && !(ex_mem_regwrite && ex_mem_rd != 0 && ex_mem_rd == rs2) && mem_wb_rd == rs2) + forwardB <= 2'b01; + end + +endmodule diff --git a/sources_1/new/hazard_detection.v b/sources_1/new/hazard_detection.v new file mode 100644 index 0000000..3890eb0 --- /dev/null +++ b/sources_1/new/hazard_detection.v @@ -0,0 +1,38 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 12/14/2020 02:40:31 PM +// Design Name: +// Module Name: hazard_detection +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module hazard_detection(input [4:0] rd, + input [4:0] rs1, + input [4:0] rs2, + input MemRead, + output reg PCwrite, + output reg IF_IDwrite, + output reg control_sel); + + always @(rd or rs1 or rs2 or MemRead) begin + if (MemRead && (rd == rs1 || rd == rs2)) + {PCwrite, IF_IDwrite, control_sel} <= 3'b001; + else + {PCwrite, IF_IDwrite, control_sel} <= 3'b110; + end + +endmodule diff --git a/RISC_V.srcs/sources_1/new/mux2_1.v b/sources_1/new/mux2_1.v similarity index 79% rename from RISC_V.srcs/sources_1/new/mux2_1.v rename to sources_1/new/mux2_1.v index df144f3..9e7ed93 100644 --- a/RISC_V.srcs/sources_1/new/mux2_1.v +++ b/sources_1/new/mux2_1.v @@ -3,7 +3,7 @@ // Company: // Engineer: // -// Create Date: 11/02/2020 12:32:59 PM +// Create Date: 12/14/2020 02:24:05 PM // Design Name: // Module Name: mux2_1 // Project Name: @@ -21,11 +21,9 @@ module mux2_1( - input [31:0] ina, - input [31:0] inb, + input [31:0] a, b, input sel, output [31:0] out - ); - - assign out = sel ? inb : ina; +); + assign out = (sel) ? b : a; endmodule diff --git a/RISC_V.srcs/sources_1/new/instruction_memory.v b/sources_1/new/mux4_1.v similarity index 51% rename from RISC_V.srcs/sources_1/new/instruction_memory.v rename to sources_1/new/mux4_1.v index ba0cf97..11691a9 100644 --- a/RISC_V.srcs/sources_1/new/instruction_memory.v +++ b/sources_1/new/mux4_1.v @@ -3,9 +3,9 @@ // Company: // Engineer: // -// Create Date: 11/02/2020 12:42:24 PM +// Create Date: 12/07/2020 01:25:06 PM // Design Name: -// Module Name: instruction_memory +// Module Name: mux4_1 // Project Name: // Target Devices: // Tool Versions: @@ -20,14 +20,17 @@ ////////////////////////////////////////////////////////////////////////////////// -module instruction_memory(input [9:0] address, - output reg [31:0] instruction); - - reg [31:0] memory[0:6]; - - initial $readmemh("code.mem", memory); - - always @(address) - instruction <= memory[address]; - +module mux4_1(input [31:0] a, b, c, d, + input [1:0] sel, + output reg [31:0] out); + + always @(a or b or c or d or sel) begin + case (sel) + 2'b00: out <= a; + 2'b01: out <= b; + 2'b10: out <= c; + 2'b11: out <= d; + endcase + end + endmodule