69 lines
1.8 KiB
Verilog
69 lines
1.8 KiB
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 01/03/2021 01:19:39 PM
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// Design Name:
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// Module Name: EX_MEM_REG
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module EX_MEM_REG(
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output reg [4:0] RD_MEM,
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output reg RegWrite_MEM,
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output reg MemtoReg_MEM,
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output reg MemRead_MEM,
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output reg MemWrite_MEM,
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output reg Branch_MEM,
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output reg Zero_MEM,
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output reg [31:0] ALU_OUT_MEM,
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output reg [31:0] PC_Branch_MEM,
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output reg [31:0] REG_DATA2_MEM_FINAL,
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input [4:0] RD_EX,
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input RegWrite_EX,
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input MemtoReg_EX,
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input MemRead_EX,
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input MemWrite_EX,
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input Branch_EX,
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input Zero_EX,
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input [31:0] ALU_OUT_EX,
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input [31:0] PC_Branch_EX,
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input [31:0] REG_DATA2_EX_FINAL,
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input clk,
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input reset
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);
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always @(posedge clk) begin
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if (reset) begin
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{RD_MEM, RegWrite_MEM, MemtoReg_MEM, MemRead_MEM, MemWrite_MEM,
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Branch_MEM, Zero_MEM, ALU_OUT_MEM, PC_Branch_MEM, REG_DATA2_MEM_FINAL} = 107'b0;
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end
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else begin
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RD_MEM = RD_EX;
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RegWrite_MEM = RegWrite_EX;
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MemtoReg_MEM = MemtoReg_EX;
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MemRead_MEM = MemRead_EX;
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MemWrite_MEM = MemWrite_EX;
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Branch_MEM = Branch_EX;
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Zero_MEM = Zero_EX;
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ALU_OUT_MEM = ALU_OUT_EX;
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PC_Branch_MEM = PC_Branch_EX;
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REG_DATA2_MEM_FINAL = REG_DATA2_EX_FINAL;
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end
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end
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endmodule
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