Initial fork
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## MINISC - Minimal Instruction Set Computing
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.3v data
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##########
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# minisc #
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##########
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gnd addr
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The MINISC architecture is an emulator written in C, of a fictional minimal Von Neumann Turing Machine. A MINISC CPU have:
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- 4 internal registers.
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- 8 data pins.
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- 8 address pins.
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- one pin for .3 Volts input.
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- ground pin.
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It can address up to 256 bytes, with no bank switching. The MINISC CPU don't have I/O ports, but it can interface with external devices via shared RAM.
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### Instruction Layout
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o s t
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0000.0000
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o = opcode
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t = target
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s = source
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The following table shows the encoding of the high nibble for each instruction.
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add sub mul div | 0 1 2 3
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mod inc dec lur | 4 5 6 7
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and or xor cmp | 8 9 A B
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biz bis biq big | C D E F
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### Registers
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op rg pc st
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op = instruction
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rg = accumulator, register
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pc = program counter
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st = status
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The MINISC architecture gives you full access to the status and program counter registers, both as source and target. You can manually clear the status registers, or jump by loading the address on the program counter.
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When the source and/or target of the current instruction is OP, it refers to the next instruction. That's how the CPU writes to RAM.
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The following table shows how the instruction is encoded for the target and source lower nibble.
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t\s op rg pc st
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op | 0 1 2 3
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rg | 4 5 6 7
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pc | 8 9 A B
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st | C D E F
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### Status bits
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zer sml eql gtr
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neg car skp? int?
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The skp flag tells the MINISC cpu that the next byte should not be interpreted as a instruction, but as data. The 'int' status flag sets the OP register to 0xf0, making the CPU jump to the last "page". But I'm not sure if they're really necessary yet. So let they be placeholders.
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Here's a list of all the operators and which bits they may set on the status register. The values marked with a question mark need to be checked.
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add -> zero | equal | carry
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sub -> zero | equal | negative
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mul -> zero | equal | carry
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div -> equal
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mod -> zero
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inc -> zero (overflow or carry)
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dec -> zero (underflow or negative)
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lur -> none
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and -> zero | equal | greater? | smaller?
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or -> zero | equal | greater? | smaller?
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xor -> zero | equal? | greater? | smaller?
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cmp -> smaller | equal | greater
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biz -> none
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bis -> none
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biq -> none
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big -> none
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### Macros
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The MINISC CPU don't have a jmp instruction, But who needs it? you can load the desired address directly into the PC register.
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jmp $AD = ldr PC
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$AD
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@ -0,0 +1,11 @@
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: ${CC=gcc}
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CFLAGS="-W -Wall -Werror -Wextra -O0 -s"
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contains tcc $@ && CC=tcc
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contains clang $@ && CC=clang
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contains clean $@ && rm -v bin/minisc && exit
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check bin/minisc src/minisc.c \
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&& $CC $CFLAGS -o bin/minisc $DEPS
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@ -0,0 +1,12 @@
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# Macro assembler
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[[ $# -eq 1 ]] && [[ -f $1 ]] && {
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cat $1 | sed -E -f sed.txt > $1.tmp
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while read line; do
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echo -en "\x`echo -n $line`";
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done < $1.tmp > $1.bin
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rm $1.tmp
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echo done
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exit 0
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} || echo -e "\tusage: $0 src.asm"
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@ -0,0 +1,36 @@
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s/[0-9]+:[ ]+//g
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s/jmp/78/g
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s/\$/\n/g
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s/add/0/g
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s/sub/1/g
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s/mul/2/g
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s/div/3/g
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s/mod/4/g
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s/inc/5/g
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s/dec/6/g
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s/lur/7/g
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s/and/8/g
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s/or/9/g
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s/xor/a/g
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s/cmp/b/g
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s/biz/c/g
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s/bis/d/g
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s/biq/e/g
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s/big/f/g
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s/op op/0/g
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s/op rg/1/g
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s/op pc/2/g
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s/op st/3/g
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s/rg op/4/g
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s/rg rg/5/g
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s/rg pc/6/g
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s/rg st/7/g
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s/pc op/8/g
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s/pc rg/9/g
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s/pc pc/a/g
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s/pc st/b/g
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s/st op/c/g
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s/st rg/d/g
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s/st pc/e/g
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s/st st/f/g
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s/ //g
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@ -0,0 +1,266 @@
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#include <stdio.h>
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#include <inttypes.h>
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#include <time.h>
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#define u8 uint8_t
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#define s32 int32_t
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#define O_MASK 0xF0 /* 1111.0000 */
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#define S_MASK 0x03 /* 0000.0011 */
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#define T_MASK 0x0C /* 0000.1100 */
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#define T_MSK2 0x0F /* 0000.1111 */
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#define OP (reg[0]) /* OP code */
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#define RG (reg[1]) /* Register (accumulator) */
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#define PC (reg[2]) /* Program Counter */
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#define ST (reg[3]) /* Status */
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/* If source == source, get the next word.
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Same goes for target */
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#define SOURCE ( OP & S_MASK ? \
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®[OP & S_MASK] : \
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&ram[PC + 1] )
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#define TARGET ( OP & T_MSK2 ?\
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®[(OP & T_MSK2)/4] :\
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&ram[PC + 1] )
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#ifdef GCC
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/* enums for the goto jump table */
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enum { add, sub, mul, div, /* 0 1 2 3 */
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mod, inc, dec, lur, /* 4 5 6 7 */
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and, or, xor, cmp, /* 8 9 a b */
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biz, bis, biq, big /* c d e f */
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};
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#endif
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/* Status flag masks */
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enum {
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zr=0x01, /* zero */
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lt=0x02, /* less than */
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eq=0x04, /* equal */
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gt=0x08, /* greater than */
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cr=0x10, /* carry, overflow */
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ng=0x20, /* negative */
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_x=0x40, /* unused... */
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_y=0x80 /* unused... */
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};
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int main(int argc, char ** argv){
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u8 reg[4] = {0, 0, 0, 0};
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u8 *s=0, *t=0, _t=0, ram[256];
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#ifndef GCC
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u8 _op=0;
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#endif
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s32 c;
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FILE *fp;
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struct timespec nap;
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/** 125.000.000 for 8hz
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** 3.906.250 for 256hz
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nap.tv_nsec = (long) 3906250;
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**/
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nap.tv_sec = 0;
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nap.tv_nsec = (long) 125000000;
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#ifdef GCC
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/* jump table for gotos */
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void * jmps[16] = {
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&&add, &&sub, &&mul, &&div,
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&&mod, &&inc, &&dec, &&lur,
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&&and, &&or, &&xor, &&cmp,
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&&biz, &&bis, &&biq, &&big
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};
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#endif
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/* exits if we don't have arguments */
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if(argc < 2) return 1;
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/* exits if we fail reading the file */
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fp = fopen(argv[1], "r");
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if (!fp) return 2;
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/* zeros the ram */
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PC=0;do{ram[PC]=0;PC++;}while(PC);
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/* reads file to ram */
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while((c = fgetc(fp)) != EOF){
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ram[PC] = c;
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printf("%02x ", ram[PC]);
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PC++;
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if(!(PC%16))puts("");
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/*nanosleep(&nap, NULL);*/
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}; puts("");
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PC=255;
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cycle: /* CPU cycle */
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PC++;
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OP = ram[PC];
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s = SOURCE;
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t = TARGET;
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_t = *t; /* set the latch target register */
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printf("OP=%02x, RG=%02x, PC=%02x, "
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"ST=%02x, s=%02x, t=%02x, ",
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OP, RG, PC,
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ST, *s, *t);
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nanosleep(&nap, NULL);
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#ifdef GCC
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/* gcc dynamic jump */
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goto *(jmps[(OP&O_MASK)>>4]);
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#endif
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#ifndef GCC
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_op = (OP&O_MASK)>>4;
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/* ternary operator binary search */
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_op < 8 ? ({goto lt8;}) : ({goto ge8;});
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lt8:
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_op < 4 ? ({goto lt4;}) : ({goto ge4;});
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lt4:
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_op < 2 ? ({goto lt2;}) : ({goto ge2;});
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lt2:
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_op ? ({goto sub;}) : ({goto add;});
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ge2:
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_op == 2 ? ({goto mul;}) : ({goto div;});
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ge4:
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_op < 6 ? ({goto lt6;}) : ({goto ge6;});
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lt6:
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_op == 4 ? ({goto mod;}) : ({goto inc;});
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ge6:
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_op == 6 ? ({goto dec;}) : ({goto lur;});
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ge8:
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_op < 12 ? ({goto ltc;}) : ({goto gec;});
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ltc:
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_op < 10 ? ({goto lta;}) : ({goto gea;});
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lta:
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_op == 8 ? ({goto and;}) : ({goto or;});
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gea:
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_op == 10 ? ({goto xor;}) : ({goto cmp;});
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gec:
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_op < 14 ? ({goto lte;}) : ({goto gee;});
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lte:
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_op == 12 ? ({goto biz;}) : ({goto bis;});
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gee:
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_op == 14 ? ({goto biq;}) : ({goto big;});
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#endif
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add: /* add */
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puts("add'ing");
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*t += *s;
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if(!*t) ST |= zr;
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if(*t == _t) ST |= eq;
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if(*t < _t) ST |= cr;
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goto cycle;
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sub: /* subtract */
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puts("sub'ing");
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*t -= *s;
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if (!*t) ST |= zr;
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if (*t == _t) ST |= eq;
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if(*t > _t) ST |= ng;
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goto cycle;
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mul: /* multiply */
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puts("mul'ing");
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*t *= *s;
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if (!*t) ST |= zr;
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if (*t < _t) ST |= cr;
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goto cycle;
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div: /* divide */
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puts("div'ing");
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/* avoid dividing by zero */
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if (*s != 0) *t /= *s;
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else ST |= zr;
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goto cycle;
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mod: /* modulus */
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puts("mod'ing");
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/* avoid dividing by zero */
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if (*s != 0) *t %= *s;
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else ST |= zr; /* ? */
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goto cycle;
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inc: /* increment */
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puts("inc'ing");
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(*t)++;
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if (!*t) ST |= cr;
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if (*t == 0) ST |= (zr & cr);
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goto cycle;
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dec: /* decrement */
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puts("dec'ing");
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(*t)--;
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if (!*t) ST |= zr;
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if (*t == 255) ST |= (zr & ng);
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goto cycle;
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lur: /* load/unload registers (LOAD/STORE) */
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puts("lur'ing");
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*t = *s;
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goto cycle;
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and: /* and */
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puts("and'ing");
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*t &= *s;
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if (!*t) ST |= zr;
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if (*t < _t) ST |= lt;
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if (*t > _t) ST |= gt;
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if (*t == _t) ST |= eq;
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else ST ^= eq;
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goto cycle;
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or: /* or */
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puts(" or'ing");
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*t |= *s;
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if (!*t) ST |= zr;
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if (*t < _t) ST |= lt;
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if (*t > _t) ST |= gt;
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if (*t == _t) ST |= eq;
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else ST ^= eq;
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goto cycle;
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xor: /* exclusive or */
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puts("xor'ing");
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*t ^= *s;
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if (!*t) ST |= zr;
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if (*t < _t) ST |= lt;
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if (*t > _t) ST |= gt;
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if (*t == _t) ST |= eq;
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else ST ^= eq;
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goto cycle;
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cmp: /* compare */
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puts("cmp'ing");
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if (*t < *s) ST |= lt;
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if (*t > *s) ST |= gt;
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if (*t == *s) ST |= eq;
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else ST ^= eq;
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goto cycle;
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biz: /* branch if zero */
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puts("biz'ing");
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/* OP+1 to get the next word,
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* -1 'cause the 1st thing the cycle does
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* is increment the OP */
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if (ST & zr) OP = ram[OP+1]-1;
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goto cycle;
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bis: /* branch if smaller */
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puts("bis'ing");
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if (ST & lt) OP = ram[OP+1]-1;
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goto cycle;
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biq: /* branch if eQual */
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puts("biq'ing");
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if (ST & eq) OP = ram[OP+1]-1;
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goto cycle;
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big: /* branch if greater */
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puts("big'ing");
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if (ST & gt) OP = ram[OP+1]-1;
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goto cycle;
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return 0; /* unreachable */
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}
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