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XduooX3 Tweak LCD drive strength and slew 

Change-Id: Ic5ee9e700a0c8acffc39b51cedc24ff44d230fd3
This commit is contained in:
William Wilgus 2020-08-30 17:22:19 -04:00
parent e06ab68166
commit 06e9abc428
2 changed files with 17 additions and 7 deletions
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6
firmware/export/jz4760b.h
View File

@ -275,9 +275,9 @@
#define REG_GPIO_PXDS2(n) REG32(GPIO_PXDS2(n))
#define REG_GPIO_PXDS2S(n) REG32(GPIO_PXDS2S(n))
#define REG_GPIO_PXDS2C(n) REG32(GPIO_PXDS2C(n))
#define REG_GPIO_PXSL(n) REG32(GPIO_PXSL(n))
#define REG_GPIO_PXSLS(n) REG32(GPIO_PXSLS(n))
#define REG_GPIO_PXSLC(n) REG32(GPIO_PXSLC(n))
#define REG_GPIO_PXSL(n) REG32(GPIO_PXSL(n)) /* Port Slew */
#define REG_GPIO_PXSLS(n) REG32(GPIO_PXSLS(n)) /* Port Slew -- Fast */
#define REG_GPIO_PXSLC(n) REG32(GPIO_PXSLC(n)) /* Port Slew -- Slow */
/*----------------------------------------------------------------
* p is the port number (0,1,2,3,4,5)

18
firmware/target/mips/ingenic_jz47xx/xduoo_x3/lcd-xduoo_x3.c
View File

@ -97,10 +97,20 @@ static inline void bitdelay(void)
void lcd_hw_init(void)
{
REG_GPIO_PXFUNC(2) = 0x000C73FC; /* D0-D7 RD DC CS RES WR */
REG_GPIO_PXSELC(2) = 0x000C73FC;
REG_GPIO_PXDIRS(2) = 0x000C73FC;
REG_GPIO_PXDATS(2) = 0x000C73FC;
REG_GPIO_PXFUNC(2) = 0x000C73FC; /* D0-D7 RD DC CS RES WR -- GPIO/INTERRUPT */
REG_GPIO_PXSELC(2) = 0x000C73FC; /* GPIO */
REG_GPIO_PXPEC(2) = 0x000C73FC; /* ENABLE PULLUP*/
REG_GPIO_PXDIRS(2) = 0x000C73FC; /* OUTPUT */
REG_GPIO_PXDATS(2) = 0x000C73FC; /* D0-D7 RD DC CS RES WR -- SET BIT */
REG_GPIO_PXSLC(2) = 0x000C73FC; /* slew -- slow rate */
REG_GPIO_PXDS0C(2) = 0x000C73FC; /* Low pin drive strength */
REG_GPIO_PXDS1C(2) = 0x000C73FC;
REG_GPIO_PXDS2C(2) = 0x000C73FC;
__gpio_clear_pin(PIN_BL_EN);
__gpio_as_output(PIN_BL_EN);
__gpio_clear_pin(PIN_LCD_RES);