Stabilize PP5020 targets - tested on H10 5/20GB and iPod Color. Use no interrupts on COP but pulse it through the control interface. Don't mess with LCD clocking during clock changes. Give a reset register a name (DEV_OFF_MASK).
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@14998 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Michael Sevakis
parent
c27ae40ca2
commit
18e87ff1c0
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@ -116,8 +116,9 @@
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#define RTC (*(volatile unsigned long *)(0x60005014))
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/* Device Controller */
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#define DEV_RS (*(volatile unsigned long *)(0x60006004))
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#define DEV_EN (*(volatile unsigned long *)(0x6000600c))
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#define DEV_RS (*(volatile unsigned long *)(0x60006004))
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#define DEV_OFF_MASK (*(volatile unsigned long *)(0x60006008))
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#define DEV_EN (*(volatile unsigned long *)(0x6000600c))
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#define DEV_SYSTEM 0x00000004
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#define DEV_SER0 0x00000040
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@ -44,22 +44,18 @@ static int num_queues NOCACHEBSS_ATTR;
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void kernel_init(void)
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{
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/* Init the threading API */
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#if NUM_CORES > 1
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if (CURRENT_CORE == COP)
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{
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/* This enables the interrupt but it won't be active until
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the timer is actually started and interrupts are unmasked */
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tick_start(1000/HZ);
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}
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#endif
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init_threads();
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/* No processor other than the CPU will proceed here */
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memset(tick_funcs, 0, sizeof(tick_funcs));
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num_queues = 0;
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memset(all_queues, 0, sizeof(all_queues));
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tick_start(1000/HZ);
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/* Other processors will not reach this point in a multicore build.
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* In a single-core build with multiple cores they fall-through and
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* sleep in cop_main without returning. */
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if (CURRENT_CORE == CPU)
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{
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memset(tick_funcs, 0, sizeof(tick_funcs));
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num_queues = 0;
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memset(all_queues, 0, sizeof(all_queues));
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tick_start(1000/HZ);
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}
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}
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void sleep(int ticks)
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@ -573,8 +569,8 @@ void TIMER1(void)
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TIMER1_VAL; /* Read value to ack IRQ */
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/* Run through the list of tick tasks (using main core -
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COP does not dispatch ticks to this subroutine) */
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/* Run through the list of tick tasks using main CPU core -
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wake up the COP through its control interface to provide pulse */
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for (i = 0;i < MAX_NUM_TICK_TASKS;i++)
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{
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if (tick_funcs[i])
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@ -583,6 +579,27 @@ void TIMER1(void)
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}
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}
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#if NUM_CORES > 1
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#ifdef CPU_PP502x
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{
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/* If COP is sleeping - give it a kick */
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/* TODO: Use a mailbox in addition to make sure it doesn't go to
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* sleep if kicked just as it's headed to rest to make sure its
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* tick checks won't be jittery. Don't bother at all if it owns no
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* threads. */
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unsigned int cop_ctl;
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cop_ctl = COP_CTL;
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if (cop_ctl & PROC_SLEEP)
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{
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COP_CTL = cop_ctl & ~PROC_SLEEP;
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}
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}
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#else
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/* TODO: PP5002 */
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#endif
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#endif /* NUM_CORES */
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current_tick++;
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}
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#endif
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@ -591,17 +608,12 @@ void TIMER1(void)
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void tick_start(unsigned int interval_in_ms)
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{
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#ifndef BOOTLOADER
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if(CURRENT_CORE == CPU)
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{
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TIMER1_CFG = 0x0;
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TIMER1_VAL;
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/* enable timer */
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TIMER1_CFG = 0xc0000000 | (interval_in_ms*1000 - 1);
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/* unmask interrupt source */
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CPU_INT_EN = TIMER1_MASK;
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} else {
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COP_INT_EN = TIMER1_MASK;
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}
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TIMER1_CFG = 0x0;
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TIMER1_VAL;
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/* enable timer */
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TIMER1_CFG = 0xc0000000 | (interval_in_ms*1000 - 1);
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/* unmask interrupt source */
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CPU_INT_EN = TIMER1_MASK;
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#else
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/* We don't enable interrupts in the bootloader */
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(void)interval_in_ms;
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@ -134,15 +134,12 @@ void set_cpu_frequency(long frequency)
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static void pp_set_cpu_frequency(long frequency)
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#endif
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{
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unsigned long clcd_clock_src;
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#if defined(HAVE_ADJUSTABLE_CPU_FREQ) && (NUM_CORES > 1)
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/* Using mutex or spinlock isn't safe here. */
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while (test_and_set(&boostctrl_mtx.locked, 1)) ;
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#endif
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cpu_frequency = frequency;
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clcd_clock_src = CLCD_CLOCK_SRC; /* save selected color LCD clock source */
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switch (frequency)
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{
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@ -152,7 +149,6 @@ static void pp_set_cpu_frequency(long frequency)
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* have this limitation (and the post divider?) */
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case CPUFREQ_MAX:
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CLOCK_SOURCE = 0x10007772; /* source #1: 24MHz, #2, #3, #4: PLL */
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CLCD_CLOCK_SRC &= ~0xc0000000; /* select 24MHz as color LCD clock source */
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DEV_TIMING1 = 0x00000808;
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#if CONFIG_CPU == PP5020
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PLL_CONTROL = 0x8a020a03; /* 10/3 * 24MHz */
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@ -168,7 +164,6 @@ static void pp_set_cpu_frequency(long frequency)
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case CPUFREQ_NORMAL:
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CLOCK_SOURCE = 0x10007772; /* source #1: 24MHz, #2, #3, #4: PLL */
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CLCD_CLOCK_SRC &= ~0xc0000000; /* select 24MHz as color LCD clock source */
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DEV_TIMING1 = 0x00000303;
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#if CONFIG_CPU == PP5020
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PLL_CONTROL = 0x8a020504; /* 5/4 * 24MHz */
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@ -182,14 +177,12 @@ static void pp_set_cpu_frequency(long frequency)
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case CPUFREQ_SLEEP:
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CLOCK_SOURCE = 0x10002202; /* source #2: 32kHz, #1, #3, #4: 24MHz */
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CLCD_CLOCK_SRC &= ~0xc0000000; /* select 24MHz as color LCD clock source */
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PLL_CONTROL &= ~0x80000000; /* disable PLL */
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udelay(10000); /* let 32kHz source stabilize? */
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break;
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default:
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CLOCK_SOURCE = 0x10002222; /* source #1, #2, #3, #4: 24MHz */
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CLCD_CLOCK_SRC &= ~0xc0000000; /* select 24MHz as color LCD clock source */
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DEV_TIMING1 = 0x00000303;
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PLL_CONTROL &= ~0x80000000; /* disable PLL */
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cpu_frequency = CPUFREQ_DEFAULT;
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@ -197,9 +190,6 @@ static void pp_set_cpu_frequency(long frequency)
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}
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CLOCK_SOURCE = (CLOCK_SOURCE & ~0xf0000000) | 0x20000000; /* select source #2 */
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CLCD_CLOCK_SRC; /* dummy read (to sync the write pipeline??) */
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CLCD_CLOCK_SRC = clcd_clock_src; /* restore saved value */
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#if defined(HAVE_ADJUSTABLE_CPU_FREQ) && (NUM_CORES > 1)
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boostctrl_mtx.locked = 0;
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#endif
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@ -213,17 +203,17 @@ void system_init(void)
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{
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#if defined(SANSA_E200) || defined(SANSA_C200)
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/* Reset all devices */
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outl(inl(0x60006008) | 0x20, 0x60006008);
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DEV_OFF_MASK |= 0x20;
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DEV_RS = 0x3bfffef8;
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outl(0xffffffff, 0x60006008);
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DEV_OFF_MASK = -1;
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DEV_RS = 0;
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outl(0x00000000, 0x60006008);
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#elif defined (IRIVER_H10)
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DEV_OFF_MASK = 0;
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#elif defined (IRIVER_H10)
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DEV_RS = 0x3ffffef8;
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outl(0xffffffff, 0x60006008);
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DEV_OFF_MASK = -1;
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outl(inl(0x70000024) | 0xc0, 0x70000024);
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DEV_RS = 0;
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outl(0x00000000, 0x60006008);
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DEV_OFF_MASK = 0;
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#endif
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#if !defined(SANSA_E200) && !defined(SANSA_C200)
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@ -1095,7 +1095,6 @@ void init_threads(void)
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/* Get COP safely primed inside switch_thread where it will remain
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* until a thread actually exists on it */
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CPU_CTL = PROC_WAKE;
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set_irq_level(0);
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remove_thread(NULL);
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#endif /* NUM_CORES */
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}
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