Fixed REG and REG_ADDR style macros
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@150 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Björn Stenberg
parent
45e9494a45
commit
191f4d22b9
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@ -22,49 +22,49 @@
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#include <led.h>
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#define turn_on() \
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set_bit (LEDB,PBDR+1)
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set_bit (LEDB,PBDR_ADDR+1)
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#define turn_off() \
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clear_bit (LEDB,PBDR+1)
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clear_bit (LEDB,PBDR_ADDR+1)
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#define start_timer() \
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set_bit (2,ITUTSTR)
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set_bit (2,TSTR_ADDR)
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#define stop_timer() \
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clear_bit (2,ITUTSTR)
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clear_bit (2,TSTR_ADDR)
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#define eoi(subinterrupt) \
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clear_bit (subinterrupt,ITUTSR2)
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clear_bit (subinterrupt,TSR2_ADDR)
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#define set_volume(volume) \
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HI(ITUGRA2) = volume & 0x7FFF
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GRA2 = volume & 0x7FFF
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void led_set_volume (unsigned short volume)
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{
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{
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volume <<= 10;
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if (volume == 0)
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led_turn_off ();
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led_turn_off ();
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else if (volume == 0x8000)
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led_turn_on ();
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led_turn_on ();
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else
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{
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set_volume (volume);
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{
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set_volume (volume);
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start_timer ();
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}
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}
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}
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}
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#pragma interrupt
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void IMIA2 (void)
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{
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{
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turn_off ();
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eoi (0);
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}
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}
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#pragma interrupt
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void OVI2 (void)
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{
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{
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turn_on ();
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eoi (2);
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}
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}
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@ -26,21 +26,21 @@
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#define LEDB 6 /* PB6 : red LED */
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static inline void led_turn_off (void)
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{
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{
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clear_bit (LEDB,PBDR+1);
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clear_bit (2,ITUTSTR);
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}
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clear_bit (2,TSTR_ADDR);
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}
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static inline void led_turn_on (void)
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{
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{
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set_bit (LEDB,PBDR+1);
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set_bit (2,ITUTSTR);
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}
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set_bit (2,TSTR_ADDR);
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}
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static inline void led_toggle (void)
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{
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{
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toggle_bit (LEDB,PBDR+1);
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}
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}
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extern void led_set_volume (unsigned short volume);
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extern void led_setup (void);
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@ -31,54 +31,52 @@
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static int serial_byte,serial_flag;
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void serial_putc (char byte)
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{
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static int i = 0;
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while (!(QI(SCISSR1) & (1<<TDRE)));
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QI(SCITDR1) = byte;
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clear_bit (TDRE,SCISSR1);
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lcd_goto ((i++)%11,1); lcd_putc (byte);
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}
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{
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while (!(SSR1 & (1<<TDRE)));
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TDR1 = byte;
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clear_bit(TDRE,SSR1_ADDR);
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}
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void serial_puts (char const *string)
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{
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{
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int byte;
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while ((byte = *string++))
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serial_putc (byte);
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}
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while ((byte = *string++))
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serial_putc (byte);
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}
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int serial_getc( void )
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{
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int byte;
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while (!serial_flag);
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{
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int byte;
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while (!serial_flag);
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byte = serial_byte;
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serial_flag = 0;
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serial_putc (byte);
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return byte;
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}
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serial_putc (byte);
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return byte;
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}
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void serial_setup (int baudrate)
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{
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QI(SCISCR1) =
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QI(SCISSR1) =
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QI(SCISMR1) = 0;
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QI(SCIBRR1) = (PHI/(32*baudrate))-1;
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QI(SCISCR1) = 0x70;
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}
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{
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SCR1 = 0;
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SSR1 = 0;
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SMR1 = 0;
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BRR1 = (FREQ/(32*baudrate))-1;
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SCR1 = 0x70;
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}
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#pragma interrupt
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void REI1 (void)
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{
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clear_bit (FER,SCISSR1);
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}
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{
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clear_bit (FER,SSR1_ADDR);
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}
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#pragma interrupt
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void RXI1 (void)
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{
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serial_byte = QI(SCIRDR1);
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{
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serial_byte = RDR1;
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serial_flag = 1;
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clear_bit (RDRF,SCISSR1);
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clear_bit(RDRF,SSR1_ADDR);
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if (serial_byte == '0')
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lcd_turn_off_backlight ();
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lcd_turn_off_backlight ();
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if (serial_byte == '1')
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lcd_turn_on_backlight ();
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}
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lcd_turn_on_backlight ();
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}
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@ -22,146 +22,275 @@
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#define GBR 0x00000000
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#define SCISMR0 0x05FFFEC0
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#define SCIBRR0 0x05FFFEC1
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#define SCISCR0 0x05FFFEC2
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#define SCITDR0 0x05FFFEC3
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#define SCISSR0 0x05FFFEC4
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#define SCIRDR0 0x05FFFEC5
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#define SCISMR1 0x05FFFEC8
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#define SCIBRR1 0x05FFFEC9
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#define SCISCR1 0x05FFFECA
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#define SCITDR1 0x05FFFECB
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#define SCISSR1 0x05FFFECC
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#define SCIRDR1 0x05FFFECD
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/* register address macros: */
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#define ADDRA 0x05FFFEE0
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#define ADDRAH 0x05FFFEE0
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#define ADDRAL 0x05FFFEE1
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#define ADDRB 0x05FFFEE2
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#define ADDRBH 0x05FFFEE2
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#define ADDRBL 0x05FFFEE3
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#define ADDRC 0x05FFFEE4
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#define ADDRCH 0x05FFFEE4
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#define ADDRCL 0x05FFFEE5
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#define ADDRD 0x05FFFEE6
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#define ADDRDH 0x05FFFEE6
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#define ADDRDL 0x05FFFEE6
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#define ADCSR 0x05FFFEE8
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#define ADCR 0x05FFFEE9
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#define SMR0_ADDR 0x05FFFEC0
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#define BRR0_ADDR 0x05FFFEC1
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#define SCR0_ADDR 0x05FFFEC2
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#define TDR0_ADDR 0x05FFFEC3
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#define SSR0_ADDR 0x05FFFEC4
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#define RDR0_ADDR 0x05FFFEC5
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#define SMR1_ADDR 0x05FFFEC8
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#define BRR1_ADDR 0x05FFFEC9
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#define SCR1_ADDR 0x05FFFECA
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#define TDR1_ADDR 0x05FFFECB
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#define SSR1_ADDR 0x05FFFECC
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#define RDR1_ADDR 0x05FFFECD
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#define ITUTSTR 0x05FFFF00
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#define ITUTSNC 0x05FFFF01
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#define ITUTMDR 0x05FFFF02
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#define ITUTFCR 0x05FFFF03
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#define ITUTCR0 0x05FFFF04
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#define ITUTIOR0 0x05FFFF05
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#define ITUTIER0 0x05FFFF06
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#define ITUTSR0 0x05FFFF07
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#define ITUTCNT0 0x05FFFF08
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#define ITUGRA0 0x05FFFF0A
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#define ITUGRB0 0x05FFFF0C
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#define ITUTCR1 0x05FFFF0E
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#define ITUTIOR1 0x05FFFF0F
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#define ITUTIER1 0x05FFFF10
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#define ITUTSR1 0x05FFFF11
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#define ITUTCNT1 0x05FFFF12
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#define ITUGRA1 0x05FFFF14
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#define ITUGRB1 0x05FFFF16
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#define ITUTCR2 0x05FFFF18
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#define ITUTIOR2 0x05FFFF19
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#define ITUTIER2 0x05FFFF1A
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#define ITUTSR2 0x05FFFF1B
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#define ITUTCNT2 0x05FFFF1C
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#define ITUGRA2 0x05FFFF1E
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#define ITUGRB2 0x05FFFF20
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#define ITUTCR3 0x05FFFF22
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#define ITUTIOR3 0x05FFFF23
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#define ITUTIER3 0x05FFFF24
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#define ITUTSR3 0x05FFFF25
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#define ITUTCNT3 0x05FFFF26
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#define ITUGRA3 0x05FFFF28
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#define ITUGRB3 0x05FFFF2A
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#define ITUBRA3 0x05FFFF2C
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#define ITUBRB3 0x05FFFF2E
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#define ITUTOCR 0x05FFFF31
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#define ITUTCR4 0x05FFFF32
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#define ITUTIOR4 0x05FFFF33
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#define ITUTIER4 0x05FFFF34
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#define ITUTSR4 0x05FFFF35
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#define ITUTCNT4 0x05FFFF36
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#define ITUGRA4 0x05FFFF38
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#define ITUGRB4 0x05FFFF3A
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#define ITUBRA4 0x05FFFF3C
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#define ITUBRB4 0x05FFFF3E
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#define ADDRA_ADDR 0x05FFFEE0
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#define ADDRAH_ADDR 0x05FFFEE0
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#define ADDRAL_ADDR 0x05FFFEE1
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#define ADDRB_ADDR 0x05FFFEE2
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#define ADDRBH_ADDR 0x05FFFEE2
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#define ADDRBL_ADDR 0x05FFFEE3
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#define ADDRC_ADDR 0x05FFFEE4
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#define ADDRCH_ADDR 0x05FFFEE4
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#define ADDRCL_ADDR 0x05FFFEE5
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#define ADDRD_ADDR 0x05FFFEE6
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#define ADDRDH_ADDR 0x05FFFEE6
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#define ADDRDL_ADDR 0x05FFFEE6
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#define ADCSR_ADDR 0x05FFFEE8
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#define ADCR_ADDR 0x05FFFEE9
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#define DMACSAR0 0x05FFFF40
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#define DMACDAR0 0x05FFFF44
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#define DMACOR 0x05FFFF48
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#define DMACTCR0 0x05FFFF4A
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#define DMACCHCR0 0x05FFFF4E
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#define DMACSAR1 0x05FFFF50
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#define DMACDAR1 0x05FFFF54
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#define DMACTCR1 0x05FFFF5A
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#define DMACCHCR1 0x05FFFF5E
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#define DMACSAR2 0x05FFFF60
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#define DMACDAR2 0x05FFFF64
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#define DMACTCR2 0x05FFFF6A
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#define DMACCHCR2 0x05FFFF6E
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#define DMACSAR3 0x05FFFF70
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#define DMACDAR3 0x05FFFF74
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#define DMACTCR3 0x05FFFF7A
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#define DMACCHCR3 0x05FFFF7E
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#define TSTR_ADDR 0x05FFFF00
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#define TSNC_ADDR 0x05FFFF01
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#define TMDR_ADDR 0x05FFFF02
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#define TFCR_ADDR 0x05FFFF03
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#define TCR0_ADDR 0x05FFFF04
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#define TIOR0_ADDR 0x05FFFF05
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#define TIER0_ADDR 0x05FFFF06
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#define TSR0_ADDR 0x05FFFF07
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#define TCNT0_ADDR 0x05FFFF08
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#define GRA0_ADDR 0x05FFFF0A
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#define GRB0_ADDR 0x05FFFF0C
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#define TCR1_ADDR 0x05FFFF0E
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#define TIOR1_ADDR 0x05FFFF0F
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#define TIER1_ADDR 0x05FFFF10
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#define TSR1_ADDR 0x05FFFF11
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#define TCNT1_ADDR 0x05FFFF12
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#define GRA_ADDR1 0x05FFFF14
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#define GRB1_ADDR 0x05FFFF16
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#define TCR2_ADDR 0x05FFFF18
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#define TIOR2_ADDR 0x05FFFF19
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#define TIER2_ADDR 0x05FFFF1A
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#define TSR2_ADDR 0x05FFFF1B
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#define TCNT2_ADDR 0x05FFFF1C
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#define GRA2_ADDR 0x05FFFF1E
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#define GRB2_ADDR 0x05FFFF20
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#define TCR3_ADDR 0x05FFFF22
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#define TIOR3_ADDR 0x05FFFF23
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#define TIER3_ADDR 0x05FFFF24
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#define TSR3_ADDR 0x05FFFF25
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#define TCNT3_ADDR 0x05FFFF26
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#define GRA3_ADDR 0x05FFFF28
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#define GRB3_ADDR 0x05FFFF2A
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#define BRA3_ADDR 0x05FFFF2C
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#define BRB3_ADDR 0x05FFFF2E
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#define TOCR_ADDR 0x05FFFF31
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#define TCR4_ADDR 0x05FFFF32
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#define TIOR4_ADDR 0x05FFFF33
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#define TIER4_ADDR 0x05FFFF34
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#define TSR4_ADDR 0x05FFFF35
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#define TCNT4_ADDR 0x05FFFF36
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#define GRA4_ADDR 0x05FFFF38
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#define GRB4_ADDR 0x05FFFF3A
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#define BRA4_ADDR 0x05FFFF3C
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#define BRB4_ADDR 0x05FFFF3E
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#define INTCIPRAB 0x05FFFF84
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#define INTCIPRA 0x05FFFF84
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#define INTCIPRB 0x05FFFF86
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#define INTCIPRCD 0x05FFFF88
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#define INTCIPRC 0x05FFFF88
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#define INTCIPRD 0x05FFFF8A
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#define INTCIPRE 0x05FFFF8C
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#define INTCICR 0x05FFFF8E
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#define SAR0_ADDR 0x05FFFF40
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#define DAR0_ADDR 0x05FFFF44
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#define OR_ADDR 0x05FFFF48
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#define TCR0_ADDR 0x05FFFF4A
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#define CHCR0_ADDR 0x05FFFF4E
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#define SAR1_ADDR 0x05FFFF50
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#define DAR1_ADDR 0x05FFFF54
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#define TCR1_ADDR 0x05FFFF5A
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#define CHCR1_ADDR 0x05FFFF5E
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#define SAR2_ADDR 0x05FFFF60
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#define DAR2_ADDR 0x05FFFF64
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#define TCR2_ADDR 0x05FFFF6A
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#define CHCR2_ADDR 0x05FFFF6E
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#define SAR3_ADDR 0x05FFFF70
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#define DAR3_ADDR 0x05FFFF74
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#define TCR3_ADDR 0x05FFFF7A
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#define CHCR3_ADDR 0x05FFFF7E
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#define UBCBAR 0x05FFFF90
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#define UBCBARH 0x05FFFF90
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#define UBCBARL 0x05FFFF92
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#define UBCBAMR 0x05FFFF94
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#define UBCBAMRH 0x05FFFF94
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#define UBCBAMRL 0x05FFFF96
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#define UBCBBR 0x05FFFF98
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#define IPRA_ADDR 0x05FFFF84
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#define IPRB_ADDR 0x05FFFF86
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#define IPRC_ADDR 0x05FFFF88
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#define IPRD_ADDR 0x05FFFF8A
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#define IPRE_ADDR 0x05FFFF8C
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#define ICR_ADDR 0x05FFFF8E
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#define BSCBCR 0x05FFFFA0
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#define BSCWCR1 0x05FFFFA2
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#define BSCWCR2 0x05FFFFA4
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#define BSCWCR3 0x05FFFFA6
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#define BSCDCR 0x05FFFFA8
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#define BSCPCR 0x05FFFFAA
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#define BSCRCR 0x05FFFFAC
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#define BSCRTCSR 0x05FFFFAE
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#define BSCRTCNT 0x05FFFFB0
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#define BSCRTCOR 0x05FFFFB2
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#define BARH_ADDR 0x05FFFF90
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#define BARL_ADDR 0x05FFFF92
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#define BAMRH_ADDR 0x05FFFF94
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#define BAMRL_ADDR 0x05FFFF96
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#define BBR_ADDR 0x05FFFF98
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#define WDTTCSR 0x05FFFFB8
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#define WDTTCNT 0x05FFFFB9
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#define WDTRSTCSR 0x05FFFFBB
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#define BCR_ADDR 0x05FFFFA0
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#define WCR1_ADDR 0x05FFFFA2
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#define WCR2_ADDR 0x05FFFFA4
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#define WCR3_ADDR 0x05FFFFA6
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#define DCR_ADDR 0x05FFFFA8
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#define PCR_ADDR 0x05FFFFAA
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#define RCR_ADDR 0x05FFFFAC
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#define RTCSR_ADDR 0x05FFFFAE
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#define RTCNT_ADDR 0x05FFFFB0
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#define RTCOR_ADDR 0x05FFFFB2
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#define SBYCR 0x05FFFFBC
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#define TCSR_ADDR 0x05FFFFB8
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#define TCNT_ADDR 0x05FFFFB9
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#define RSTCSR_ADDR 0x05FFFFBB
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#define PABDR 0x05FFFFC0
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#define PADR 0x05FFFFC0
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#define PBDR 0x05FFFFC2
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#define PABIOR 0x05FFFFC4
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#define PAIOR (*((volatile unsigned short *)0x05FFFFC4))
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#define PBIOR (*((volatile unsigned short *)0x05FFFFC6))
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#define PACR 0x05FFFFC8
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#define PACR1 0x05FFFFC8
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#define PACR2 0x05FFFFCA
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#define PBCR 0x05FFFFCC
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#define PBCR1 0x05FFFFCC
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#define PBCR2 0x05FFFFCE
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#define PCDR 0x05FFFFD1
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#define SBYCR_ADDR 0x05FFFFBC
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#define PADR_ADDR 0x05FFFFC0
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#define PBDR_ADDR 0x05FFFFC2
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#define PAIOR_ADDR 0x05FFFFC4
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#define PBIOR_ADDR 0x05FFFFC6
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#define PACR1_ADDR 0x05FFFFC8
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#define PACR2_ADDR 0x05FFFFCA
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#define PBCR1_ADDR 0x05FFFFCC
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#define PBCR2_ADDR 0x05FFFFCE
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#define PCDR_ADDR 0x05FFFFD0
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#define CASCR_ADDR 0x05FFFFEE
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#define CASCR 0x05FFFFEE
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|
||||
/* register macros for direct access: */
|
||||
|
||||
#define SMR0 (*((volatile unsigned char*)SMR0_ADDR))
|
||||
#define BRR0 (*((volatile unsigned char*)BRR0_ADDR))
|
||||
#define SCR0 (*((volatile unsigned char*)SCR0_ADDR))
|
||||
#define TDR0 (*((volatile unsigned char*)TDR0_ADDR))
|
||||
#define SSR0 (*((volatile unsigned char*)SSR0_ADDR))
|
||||
#define RDR0 (*((volatile unsigned char*)RDR0_ADDR))
|
||||
#define SMR1 (*((volatile unsigned char*)SMR1_ADDR))
|
||||
#define BRR1 (*((volatile unsigned char*)BRR1_ADDR))
|
||||
#define SCR1 (*((volatile unsigned char*)SCR1_ADDR))
|
||||
#define TDR1 (*((volatile unsigned char*)TDR1_ADDR))
|
||||
#define SSR1 (*((volatile unsigned char*)SSR1_ADDR))
|
||||
#define RDR1 (*((volatile unsigned char*)RDR1_ADDR))
|
||||
|
||||
#define ADDRA (*((volatile unsigned short*)ADDRA_ADDR))
|
||||
#define ADDRAH (*((volatile unsigned char*)ADDRAH_ADDR))
|
||||
#define ADDRAL (*((volatile unsigned char*)ADDRAL_ADDR))
|
||||
#define ADDRB (*((volatile unsigned short*)ADDRB_ADDR))
|
||||
#define ADDRBH (*((volatile unsigned char*)ADDRBH_ADDR))
|
||||
#define ADDRBL (*((volatile unsigned char*)ADDRBL_ADDR))
|
||||
#define ADDRC (*((volatile unsigned short*)ADDRC_ADDR))
|
||||
#define ADDRCH (*((volatile unsigned char*)ADDRCH_ADDR))
|
||||
#define ADDRCL (*((volatile unsigned char*)ADDRCL_ADDR))
|
||||
#define ADDRD (*((volatile unsigned short*)ADDRD_ADDR))
|
||||
#define ADDRDH (*((volatile unsigned char*)ADDRDH_ADDR))
|
||||
#define ADDRDL (*((volatile unsigned char*)ADDRDL_ADDR))
|
||||
#define ADCSR (*((volatile unsigned char*)ADCSR_ADDR))
|
||||
#define ADCR (*((volatile unsigned char*)ADCR_ADDR))
|
||||
|
||||
#define TSTR (*((volatile unsigned char*)TSTR_ADDR))
|
||||
#define TSNC (*((volatile unsigned char*)TSNC_ADDR))
|
||||
#define TMDR (*((volatile unsigned char*)TMDR_ADDR))
|
||||
#define TFCR (*((volatile unsigned char*)TFCR_ADDR))
|
||||
#define TCR0 (*((volatile unsigned char*)TCR0_ADDR))
|
||||
#define TIOR0 (*((volatile unsigned char*)TIOR0_ADDR))
|
||||
#define TIER0 (*((volatile unsigned char*)TIER0_ADDR))
|
||||
#define TSR0 (*((volatile unsigned char*)TSR0_ADDR))
|
||||
#define TCNT0 (*((volatile unsigned short*)TCNT0_ADDR))
|
||||
#define GRA0 (*((volatile unsigned short*)GRA0_ADDR))
|
||||
#define GRB0 (*((volatile unsigned short*)GRB0_ADDR))
|
||||
#define TCR1 (*((volatile unsigned char*)TCR1_ADDR))
|
||||
#define TIOR1 (*((volatile unsigned char*)TIOR1_ADDR))
|
||||
#define TIER1 (*((volatile unsigned char*)TIER1_ADDR))
|
||||
#define TSR1 (*((volatile unsigned char*)TSR1_ADDR))
|
||||
#define TCNT1 (*((volatile unsigned short*)TCNT1_ADDR))
|
||||
#define GRA1 (*((volatile unsigned short*)GRA_ADDR))1
|
||||
#define GRB1 (*((volatile unsigned short*)GRB1_ADDR))
|
||||
#define TCR2 (*((volatile unsigned char*)TCR2_ADDR))
|
||||
#define TIOR2 (*((volatile unsigned char*)TIOR2_ADDR))
|
||||
#define TIER2 (*((volatile unsigned char*)TIER2_ADDR))
|
||||
#define TSR2 (*((volatile unsigned char*)TSR2_ADDR))
|
||||
#define TCNT2 (*((volatile unsigned short*)TCNT2_ADDR))
|
||||
#define GRA2 (*((volatile unsigned short*)GRA2_ADDR))
|
||||
#define GRB2 (*((volatile unsigned short*)GRB2_ADDR))
|
||||
#define TCR3 (*((volatile unsigned char*)TCR3_ADDR))
|
||||
#define TIOR3 (*((volatile unsigned char*)TIOR3_ADDR))
|
||||
#define TIER3 (*((volatile unsigned char*)TIER3_ADDR))
|
||||
#define TSR3 (*((volatile unsigned char*)TSR3_ADDR))
|
||||
#define TCNT3 (*((volatile unsigned short*)TCNT3_ADDR))
|
||||
#define GRA3 (*((volatile unsigned short*)GRA3_ADDR))
|
||||
#define GRB3 (*((volatile unsigned short*)GRB3_ADDR))
|
||||
#define BRA3 (*((volatile unsigned short*)BRA3_ADDR))
|
||||
#define BRB3 (*((volatile unsigned short*)BRB3_ADDR))
|
||||
#define TOCR (*((volatile unsigned char*)TOCR_ADDR))
|
||||
#define TCR4 (*((volatile unsigned char*)TCR4_ADDR))
|
||||
#define TIOR4 (*((volatile unsigned char*)TIOR4_ADDR))
|
||||
#define TIER4 (*((volatile unsigned char*)TIER4_ADDR))
|
||||
#define TSR4 (*((volatile unsigned char*)TSR4_ADDR))
|
||||
#define TCNT4 (*((volatile unsigned short*)TCNT4_ADDR))
|
||||
#define GRA4 (*((volatile unsigned short*)GRA4_ADDR))
|
||||
#define GRB4 (*((volatile unsigned short*)GRB4_ADDR))
|
||||
#define BRA4 (*((volatile unsigned short*)BRA4_ADDR))
|
||||
#define BRB4 (*((volatile unsigned short*)BRB4_ADDR))
|
||||
|
||||
#define SAR0 (*((volatile unsigned long*)SAR0_ADDR))
|
||||
#define DAR0 (*((volatile unsigned long*)DAR0_ADDR))
|
||||
#define DMAOR (*((volatile unsigned long*)DMAOR_ADDR))
|
||||
#define TCR0 (*((volatile unsigned long*)TCR0_ADDR))
|
||||
#define CHCR0 (*((volatile unsigned short*)CHCR0_ADDR))
|
||||
#define SAR1 (*((volatile unsigned long*)SAR1_ADDR))
|
||||
#define DAR1 (*((volatile unsigned long*)DAR1_ADDR))
|
||||
#define TCR1 (*((volatile unsigned long*)TCR1_ADDR))
|
||||
#define CHCR1 (*((volatile unsigned short*)CHCR1_ADDR))
|
||||
#define SAR2 (*((volatile unsigned long*)SAR2_ADDR))
|
||||
#define DAR2 (*((volatile unsigned long*)DAR2_ADDR))
|
||||
#define TCR2 (*((volatile unsigned long*)TCR2_ADDR))
|
||||
#define HCR2 (*((volatile unsigned short*)CHCR2_ADDR))
|
||||
#define SAR3 (*((volatile unsigned long*)SAR3_ADDR))
|
||||
#define DAR3 (*((volatile unsigned long*)DAR3_ADDR))
|
||||
#define TCR3 (*((volatile unsigned long*)TCR3_ADDR))
|
||||
#define CHCR3 (*((volatile unsigned short*)CHCR3_ADDR))
|
||||
|
||||
#define IPRA (*((volatile unsigned short*)IPRA_ADDR))
|
||||
#define IPRB (*((volatile unsigned short*)IPRB_ADDR))
|
||||
#define IPRC (*((volatile unsigned short*)IPRC_ADDR))
|
||||
#define IPRD (*((volatile unsigned short*)IPRD_ADDR))
|
||||
#define IPRE (*((volatile unsigned short*)IPRE_ADDR))
|
||||
#define ICR (*((volatile unsigned short*)ICR_ADDR))
|
||||
|
||||
#define BARH (*((volatile unsigned short*)BARH_ADDR))
|
||||
#define BARL (*((volatile unsigned short*)BARL_ADDR))
|
||||
#define BAMRH (*((volatile unsigned short*)BAMRH_ADDR))
|
||||
#define BAMRL (*((volatile unsigned short*)BAMRL_ADDR))
|
||||
#define BBR (*((volatile unsigned short*)BBR_ADDR))
|
||||
|
||||
#define BCR (*((volatile unsigned short*)BCR_ADDR))
|
||||
#define WCR1 (*((volatile unsigned short*)WCR1_ADDR))
|
||||
#define WCR2 (*((volatile unsigned short*)WCR2_ADDR))
|
||||
#define WCR3 (*((volatile unsigned short*)WCR3_ADDR))
|
||||
#define DCR (*((volatile unsigned short*)DCR_ADDR))
|
||||
#define PCR (*((volatile unsigned short*)PCR_ADDR))
|
||||
#define RCR (*((volatile unsigned short*)RCR_ADDR))
|
||||
#define RTCSR (*((volatile unsigned short*)RTCSR_ADDR))
|
||||
#define RTCNT (*((volatile unsigned short*)RTCNT_ADDR))
|
||||
#define RTCOR (*((volatile unsigned short*)RTCOR_ADDR))
|
||||
|
||||
#define TCSR (*((volatile unsigned char*)TCSR_ADDR))
|
||||
#define TCNT (*((volatile unsigned char*)TCNT_ADDR))
|
||||
#define RSTCSR (*((volatile unsigned char*)RSTCSR_ADDR))
|
||||
|
||||
#define SBYCR (*((volatile unsigned char*)SBYCR_ADDR))
|
||||
|
||||
#define PADR (*((volatile unsigned short*)PADR_ADDR))
|
||||
#define PBDR (*((volatile unsigned short*)PBDR_ADDR))
|
||||
#define PAIOR (*((volatile unsigned short*)PAIOR_ADDR))
|
||||
#define PBIOR (*((volatile unsigned short*)PBIOR_ADDR))
|
||||
#define PACR1 (*((volatile unsigned short*)PACR1_ADDR))
|
||||
#define PACR2 (*((volatile unsigned short*)PACR2_ADDR))
|
||||
#define PBCR1 (*((volatile unsigned short*)PBCR1_ADDR))
|
||||
#define PBCR2 (*((volatile unsigned short*)PBCR2_ADDR))
|
||||
#define PCDR (*((volatile unsigned short*)PCDR_ADDR))
|
||||
|
||||
#define CASCR (*((volatile unsigned char*)CASCR_ADDR))
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -142,166 +142,169 @@ reserve_interrupt ( 108);
|
|||
default_interrupt (ADITI, 109);
|
||||
|
||||
void (*vbr[]) (void) __attribute__ ((section (".sram.vbr"))) =
|
||||
{
|
||||
/*** 0-1 Power-on Reset ***/
|
||||
{
|
||||
/*** 0-1 Power-on Reset ***/
|
||||
|
||||
reset_pc,reset_sp,
|
||||
|
||||
/*** 2-3 Manual Reset ***/
|
||||
/*** 2-3 Manual Reset ***/
|
||||
|
||||
reset_pc,reset_sp,
|
||||
|
||||
/*** 4 General Illegal Instruction ***/
|
||||
/*** 4 General Illegal Instruction ***/
|
||||
|
||||
GII,
|
||||
GII,
|
||||
|
||||
/*** 5 Reserved ***/
|
||||
/*** 5 Reserved ***/
|
||||
|
||||
UIE5,
|
||||
UIE5,
|
||||
|
||||
/*** 6 Illegal Slot Instruction ***/
|
||||
/*** 6 Illegal Slot Instruction ***/
|
||||
|
||||
ISI,
|
||||
ISI,
|
||||
|
||||
/*** 7-8 Reserved ***/
|
||||
/*** 7-8 Reserved ***/
|
||||
|
||||
UIE7,UIE8,
|
||||
UIE7,UIE8,
|
||||
|
||||
/*** 9 CPU Address Error ***/
|
||||
/*** 9 CPU Address Error ***/
|
||||
|
||||
CPUAE,
|
||||
CPUAE,
|
||||
|
||||
/*** 10 DMA Address Error ***/
|
||||
/*** 10 DMA Address Error ***/
|
||||
|
||||
DMAAE,
|
||||
DMAAE,
|
||||
|
||||
/*** 11 NMI ***/
|
||||
/*** 11 NMI ***/
|
||||
|
||||
NMI,
|
||||
NMI,
|
||||
|
||||
/*** 12 User Break ***/
|
||||
/*** 12 User Break ***/
|
||||
|
||||
UB,
|
||||
UB,
|
||||
|
||||
/*** 13-31 Reserved ***/
|
||||
/*** 13-31 Reserved ***/
|
||||
|
||||
UIE13,UIE14,UIE15,UIE16,UIE17,UIE18,UIE19,UIE20,UIE21,UIE22,UIE23,UIE24,UIE25,UIE26,UIE27,UIE28,UIE29,UIE30,UIE31,
|
||||
UIE13,UIE14,UIE15,UIE16,UIE17,UIE18,UIE19,UIE20,UIE21,UIE22,UIE23,UIE24,UIE25,UIE26,UIE27,UIE28,UIE29,UIE30,UIE31,
|
||||
|
||||
/*** 32-63 TRAPA #20...#3F ***/
|
||||
/*** 32-63 TRAPA #20...#3F ***/
|
||||
|
||||
TRAPA32,TRAPA33,TRAPA34,TRAPA35,TRAPA36,TRAPA37,TRAPA38,TRAPA39,TRAPA40,TRAPA41,TRAPA42,TRAPA43,TRAPA44,TRAPA45,TRAPA46,TRAPA47,TRAPA48,TRAPA49,TRAPA50,TRAPA51,TRAPA52,TRAPA53,TRAPA54,TRAPA55,TRAPA56,TRAPA57,TRAPA58,TRAPA59,TRAPA60,TRAPA61,TRAPA62,TRAPA63,
|
||||
|
||||
/*** 64-71 IRQ0-7 ***/
|
||||
/*** 64-71 IRQ0-7 ***/
|
||||
|
||||
IRQ0,IRQ1,IRQ2,IRQ3,IRQ4,IRQ5,IRQ6,IRQ7,
|
||||
|
||||
/*** 72 DMAC0 ***/
|
||||
/*** 72 DMAC0 ***/
|
||||
|
||||
DEI0,
|
||||
DEI0,
|
||||
|
||||
/*** 73 Reserved ***/
|
||||
/*** 73 Reserved ***/
|
||||
|
||||
UIE73,
|
||||
|
||||
/*** 74 DMAC1 ***/
|
||||
/*** 74 DMAC1 ***/
|
||||
|
||||
DEI1,
|
||||
|
||||
/*** 75 Reserved ***/
|
||||
/*** 75 Reserved ***/
|
||||
|
||||
UIE75,
|
||||
|
||||
/*** 76 DMAC2 ***/
|
||||
/*** 76 DMAC2 ***/
|
||||
|
||||
DEI2,
|
||||
|
||||
/*** 77 Reserved ***/
|
||||
/*** 77 Reserved ***/
|
||||
|
||||
UIE77,
|
||||
|
||||
/*** 78 DMAC3 ***/
|
||||
/*** 78 DMAC3 ***/
|
||||
|
||||
DEI3,
|
||||
DEI3,
|
||||
|
||||
/*** 79 Reserved ***/
|
||||
/*** 79 Reserved ***/
|
||||
|
||||
UIE79,
|
||||
|
||||
/*** 80-82 ITU0 ***/
|
||||
/*** 80-82 ITU0 ***/
|
||||
|
||||
IMIA0,IMIB0,OVI0,
|
||||
IMIA0,IMIB0,OVI0,
|
||||
|
||||
/*** 83 Reserved ***/
|
||||
/*** 83 Reserved ***/
|
||||
|
||||
UIE83,
|
||||
|
||||
/*** 84-86 ITU1 ***/
|
||||
/*** 84-86 ITU1 ***/
|
||||
|
||||
IMIA1,IMIB1,OVI1,
|
||||
IMIA1,IMIB1,OVI1,
|
||||
|
||||
/*** 87 Reserved ***/
|
||||
/*** 87 Reserved ***/
|
||||
|
||||
UIE87,
|
||||
|
||||
/*** 88-90 ITU2 ***/
|
||||
/*** 88-90 ITU2 ***/
|
||||
|
||||
IMIA2,IMIB2,OVI2,
|
||||
IMIA2,IMIB2,OVI2,
|
||||
|
||||
/*** 91 Reserved ***/
|
||||
/*** 91 Reserved ***/
|
||||
|
||||
UIE91,
|
||||
|
||||
/*** 92-94 ITU3 ***/
|
||||
/*** 92-94 ITU3 ***/
|
||||
|
||||
IMIA3,IMIB3,OVI3,
|
||||
IMIA3,IMIB3,OVI3,
|
||||
|
||||
/*** 95 Reserved ***/
|
||||
/*** 95 Reserved ***/
|
||||
|
||||
UIE95,
|
||||
|
||||
/*** 96-98 ITU4 ***/
|
||||
/*** 96-98 ITU4 ***/
|
||||
|
||||
IMIA4,IMIB4,OVI4,
|
||||
IMIA4,IMIB4,OVI4,
|
||||
|
||||
/*** 99 Reserved ***/
|
||||
/*** 99 Reserved ***/
|
||||
|
||||
UIE99,
|
||||
|
||||
/*** 100-103 SCI0 ***/
|
||||
/*** 100-103 SCI0 ***/
|
||||
|
||||
REI0,RXI0,TXI0,TEI0,
|
||||
REI0,RXI0,TXI0,TEI0,
|
||||
|
||||
/*** 104-107 SCI1 ***/
|
||||
/*** 104-107 SCI1 ***/
|
||||
|
||||
REI1,RXI1,TXI1,TEI1,
|
||||
REI1,RXI1,TXI1,TEI1,
|
||||
|
||||
/*** 108 Parity Control Unit ***/
|
||||
/*** 108 Parity Control Unit ***/
|
||||
|
||||
UIE108,
|
||||
UIE108,
|
||||
|
||||
/*** 109 AD Converter ***/
|
||||
/*** 109 AD Converter ***/
|
||||
|
||||
ADITI
|
||||
ADITI
|
||||
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
void system_reboot (void)
|
||||
{
|
||||
{
|
||||
cli ();
|
||||
|
||||
asm volatile ("ldc\t%0,vbr" : : "r"(0));
|
||||
|
||||
SI(INTCIPRAB) =
|
||||
SI(INTCIPRCD) = 0;
|
||||
HI(INTCIPRE) =
|
||||
HI(INTCICR) = 0;
|
||||
IPRA = 0;
|
||||
IPRB = 0;
|
||||
IPRC = 0;
|
||||
IPRD = 0;
|
||||
IPRE = 0;
|
||||
ICR = 0;
|
||||
|
||||
asm volatile ("jmp @%0; mov.l @%1,r15" : : "r"(SI(0)),"r"(4));
|
||||
}
|
||||
asm volatile ("jmp @%0; mov.l @%1,r15" : :
|
||||
"r"(*(char*)0),"r"(4));
|
||||
}
|
||||
|
||||
void UIE (unsigned int pc) /* Unexpected Interrupt or Exception */
|
||||
{
|
||||
{
|
||||
unsigned int i,n;
|
||||
lcd_stop ();
|
||||
asm volatile ("sts\tpr,%0" : "=r"(n));
|
||||
|
|
@ -314,121 +317,121 @@ void UIE (unsigned int pc) /* Unexpected Interrupt or Exception */
|
|||
lcd_stop ();
|
||||
|
||||
while (1)
|
||||
{
|
||||
{
|
||||
led_toggle ();
|
||||
|
||||
for (i = 0; i < 240000; ++i);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
asm (
|
||||
"_UIE0:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE1:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE2:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE3:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE4:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE5:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE6:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE7:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE8:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE9:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE10:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE11:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE12:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE13:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE14:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE15:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE16:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE17:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE18:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE19:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE20:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE21:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE22:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE23:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE24:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE25:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE26:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE27:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE28:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE29:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE30:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE31:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE32:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE33:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE34:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE35:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE36:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE37:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE38:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE39:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE40:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE41:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE42:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE43:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE44:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE45:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE46:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE47:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE48:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE49:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE50:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE51:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE52:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE53:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE54:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE55:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE56:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE57:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE58:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE59:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE60:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE61:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE62:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE63:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE64:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE65:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE66:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE67:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE68:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE69:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE70:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE71:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE72:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE73:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE74:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE75:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE76:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE77:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE78:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE79:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE80:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE81:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE82:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE83:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE84:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE85:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE86:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE87:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE88:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE89:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE90:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE91:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE92:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE93:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE94:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE95:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE96:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE97:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE98:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE99:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE100:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE101:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE102:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE103:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE104:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE105:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE106:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE107:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE108:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE109:\tbsr\t_UIE\n\tmov.l\t@r15+,r4");
|
||||
"_UIE0:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE1:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE2:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE3:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE4:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE5:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE6:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE7:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE8:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE9:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE10:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE11:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE12:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE13:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE14:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE15:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE16:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE17:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE18:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE19:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE20:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE21:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE22:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE23:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE24:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE25:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE26:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE27:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE28:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE29:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE30:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE31:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE32:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE33:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE34:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE35:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE36:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE37:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE38:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE39:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE40:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE41:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE42:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE43:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE44:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE45:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE46:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE47:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE48:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE49:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE50:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE51:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE52:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE53:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE54:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE55:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE56:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE57:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE58:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE59:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE60:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE61:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE62:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE63:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE64:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE65:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE66:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE67:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE68:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE69:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE70:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE71:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE72:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE73:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE74:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE75:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE76:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE77:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE78:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE79:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE80:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE81:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE82:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE83:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE84:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE85:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE86:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE87:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE88:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE89:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE90:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE91:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE92:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE93:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE94:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE95:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE96:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE97:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE98:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE99:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE100:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE101:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE102:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE103:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE104:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE105:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE106:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE107:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE108:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
|
||||
"_UIE109:\tbsr\t_UIE\n\tmov.l\t@r15+,r4");
|
||||
|
|
|
|||
|
|
@ -21,36 +21,17 @@
|
|||
#define __SYSTEM_H__
|
||||
#include <sh7034.h>
|
||||
|
||||
#define KB *1024
|
||||
#define MB *1024 KB
|
||||
#define GB *1024 MB
|
||||
|
||||
#define Hz *1
|
||||
#define KHz *1000 Hz
|
||||
#define MHz *1000 KHz
|
||||
|
||||
#define ns *1
|
||||
#define us *1000 ns
|
||||
#define ms *1000 us
|
||||
|
||||
/*
|
||||
* 11.059,200 MHz => 90.4224537037037037037037037037037... ns
|
||||
* 12.000,000 MHz => 83.3333333333333333333333333333333... ns
|
||||
*/
|
||||
|
||||
#define PHI ((int)(12.000000 MHz))
|
||||
#define FREQ 12000000
|
||||
#define BAUDRATE 9600
|
||||
|
||||
//#define PHI ((int)(11.059200 MHz))
|
||||
//#define BAUDRATE 115200 /* 115200 - 9600 */
|
||||
|
||||
#define SI(a) \
|
||||
(*((volatile int *)a)) /* single integer access - 32-bit */
|
||||
#define HI(a) \
|
||||
(*((volatile short *)a)) /* half integer access - 16-bit */
|
||||
#define QI(a) \
|
||||
(*((volatile char *)a)) /* quarter integer access - 8-bit */
|
||||
|
||||
#define nop \
|
||||
asm volatile ("nop")
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue