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jz4760: Use a #define for the timer id, not a raw number 

Change-Id: Ic31267a2ae82beede72100c1cc5ddf7211aa0abe
This commit is contained in:
Solomon Peachy 2020-09-05 20:15:23 -04:00
parent d015165bc5
commit 2dadb8c7d6
1 changed files with 17 additions and 15 deletions
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32
firmware/target/mips/ingenic_jz47xx/timer-jz4760.c
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@ -18,16 +18,18 @@
* KIND, either express or implied.
*
****************************************************************************/
#include "config.h"
#include "cpu.h"
#include "system.h"
#include "timer.h"
#define TIMER_ID 5
/* Interrupt handler */
void TCU1(void)
{
__tcu_clear_full_match_flag(5);
__tcu_clear_full_match_flag(TIMER_ID);
if (pfn_timer != NULL)
pfn_timer();
@ -56,24 +58,24 @@ bool timer_set(long cycles, bool start)
old_irq = disable_irq_save();
__tcu_stop_counter(5);
__tcu_stop_counter(TIMER_ID);
if(start)
{
__tcu_disable_pwm_output(5);
__tcu_disable_pwm_output(TIMER_ID);
__tcu_mask_half_match_irq(5);
__tcu_unmask_full_match_irq(5);
__tcu_mask_half_match_irq(TIMER_ID);
__tcu_unmask_full_match_irq(TIMER_ID);
/* EXTAL clock = CFG_EXTAL (12Mhz in most targets) */
__tcu_select_extalclk(5);
__tcu_select_extalclk(TIMER_ID);
}
REG_TCU_TCSR(5) = (REG_TCU_TCSR(5) & ~TCSR_PRESCALE_MASK) | (prescaler_bit << TCSR_PRESCALE_LSB);
REG_TCU_TCNT(5) = 0;
REG_TCU_TDHR(5) = 0;
REG_TCU_TDFR(5) = divider;
REG_TCU_TCSR(TIMER_ID) = (REG_TCU_TCSR(TIMER_ID) & ~TCSR_PRESCALE_MASK) | (prescaler_bit << TCSR_PRESCALE_LSB);
REG_TCU_TCNT(TIMER_ID) = 0;
REG_TCU_TDHR(TIMER_ID) = 0;
REG_TCU_TDFR(TIMER_ID) = divider;
__tcu_clear_full_match_flag(5);
__tcu_clear_full_match_flag(TIMER_ID);
if(start)
{
@ -81,14 +83,14 @@ bool timer_set(long cycles, bool start)
}
restore_irq(old_irq);
__tcu_start_counter(5);
__tcu_start_counter(TIMER_ID);
return true;
}
bool timer_start(void)
{
__tcu_start_counter(5);
__tcu_start_counter(TIMER_ID);
return true;
}
@ -96,6 +98,6 @@ bool timer_start(void)
void timer_stop(void)
{
unsigned int old_irq = disable_irq_save();
__tcu_stop_counter(5);
__tcu_stop_counter(TIMER_ID);
restore_irq(old_irq);
}