iPod Classic CE-ATA Support (Part 4 of 4: S5L8702 ATA driver)
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@29448 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Michael Sparmann
parent
59c5e791a1
commit
30fb680a4d
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@ -209,7 +209,7 @@ target/arm/ata-nand-telechips.c
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#if (CONFIG_STORAGE & STORAGE_NAND) && (CONFIG_NAND == NAND_SAMSUNG)
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target/arm/s5l8700/ata-nand-s5l8700.c
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#endif
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#if (CONFIG_STORAGE & STORAGE_ATA)
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#if (CONFIG_STORAGE & STORAGE_ATA) && !defined(IPOD_6G)
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drivers/ata.c
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#endif
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#if (CONFIG_STORAGE & STORAGE_SD)
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@ -1551,6 +1551,7 @@ target/arm/s5l8700/ipodnano2g/adc-nano2g.c
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#ifdef IPOD_6G
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#ifndef SIMULATOR
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target/arm/ipod/button-clickwheel.c
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target/arm/s5l8702/ipod6g/storage_ata-ipod6g.c
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target/arm/s5l8702/ipod6g/cscodec-ipod6g.c
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target/arm/s5l8702/ipod6g/backlight-ipod6g.c
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target/arm/s5l8702/ipod6g/powermgmt-ipod6g.c
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@ -1559,7 +1560,6 @@ target/arm/s5l8702/kernel-s5l8702.c
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target/arm/s5l8702/system-s5l8702.c
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target/arm/s5l8702/ipod6g/lcd-ipod6g.c
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target/arm/s5l8702/ipod6g/lcd-asm-ipod6g.S
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target/arm/s5l8702/ipod6g/ata-ipod6g.c
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#if 0 //TODO
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target/arm/s5l8702/postmortemstub.S
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#endif
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@ -185,13 +185,20 @@
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/* Define this if you can read an absolute wheel position */
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#define HAVE_WHEEL_POSITION
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//#define HAVE_ATA_BBT
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//#define ATA_BBT_PAGES 3072
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#define SECTOR_SIZE 4096
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#define STORAGE_NEEDS_ALIGN
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/* define this if the device has larger sectors when accessed via USB */
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/* (only relevant in disk.c, fat.c now always supports large virtual sectors) */
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#define MAX_LOG_SECTOR_SIZE 4096
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//#define MAX_LOG_SECTOR_SIZE 4096
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/* define this if the hard drive uses large physical sectors (ATA-7 feature) */
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/* and doesn't handle them in the drive firmware */
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#define MAX_PHYS_SECTOR_SIZE 4096
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//#define MAX_PHYS_SECTOR_SIZE 4096
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/* Define this if you have adjustable CPU frequency */
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#define HAVE_ADJUSTABLE_CPU_FREQ
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@ -568,9 +568,9 @@ struct dma_lli
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/////ATA/////
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#define ATA_CCONTROL (*((uint32_t volatile*)(0x38700000)))
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#define ATA_CSTATUS (*((uint32_t volatile*)(0x38700004)))
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#define ATA_CCOMMAND (*((uint32_t volatile*)(0x38700008)))
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#define ATA_CONTROL (*((uint32_t volatile*)(0x38700000)))
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#define ATA_STATUS (*((uint32_t volatile*)(0x38700004)))
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#define ATA_COMMAND (*((uint32_t volatile*)(0x38700008)))
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#define ATA_SWRST (*((uint32_t volatile*)(0x3870000c)))
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#define ATA_IRQ (*((uint32_t volatile*)(0x38700010)))
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#define ATA_IRQ_MASK (*((uint32_t volatile*)(0x38700014)))
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@ -586,15 +586,15 @@ struct dma_lli
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#define ATA_SBUF_SIZE (*((uint32_t volatile*)(0x38700048)))
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#define ATA_CADR_TBUF (*((void* volatile*)(0x3870004c)))
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#define ATA_CADR_SBUF (*((void* volatile*)(0x38700050)))
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#define ATA_DATA ((uint32_t volatile*)(0x38700054))
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#define ATA_ERROR ((uint32_t volatile*)(0x38700058))
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#define ATA_NSECTOR ((uint32_t volatile*)(0x3870005c))
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#define ATA_SECTOR ((uint32_t volatile*)(0x38700060))
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#define ATA_LCYL ((uint32_t volatile*)(0x38700064))
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#define ATA_HCYL ((uint32_t volatile*)(0x38700068))
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#define ATA_SELECT ((uint32_t volatile*)(0x3870006c))
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#define ATA_COMMAND ((uint32_t volatile*)(0x38700070))
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#define ATA_CONTROL ((uint32_t volatile*)(0x38700074))
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#define ATA_PIO_DTR (*((uint32_t volatile*)(0x38700054)))
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#define ATA_PIO_FED (*((uint32_t volatile*)(0x38700058)))
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#define ATA_PIO_SCR (*((uint32_t volatile*)(0x3870005c)))
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#define ATA_PIO_LLR (*((uint32_t volatile*)(0x38700060)))
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#define ATA_PIO_LMR (*((uint32_t volatile*)(0x38700064)))
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#define ATA_PIO_LHR (*((uint32_t volatile*)(0x38700068)))
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#define ATA_PIO_DVR (*((uint32_t volatile*)(0x3870006c)))
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#define ATA_PIO_CSD (*((uint32_t volatile*)(0x38700070)))
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#define ATA_PIO_DAD (*((uint32_t volatile*)(0x38700074)))
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#define ATA_PIO_READY (*((uint32_t volatile*)(0x38700078)))
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#define ATA_PIO_RDATA (*((uint32_t volatile*)(0x3870007c)))
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#define ATA_BUS_FIFO_STATUS (*((uint32_t volatile*)(0x38700080)))
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@ -602,6 +602,190 @@ struct dma_lli
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#define ATA_DMA_ADDR (*((void* volatile*)(0x38700088)))
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/////SDCI/////
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#define SDCI_CTRL (*((uint32_t volatile*)(0x38b00000)))
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#define SDCI_DCTRL (*((uint32_t volatile*)(0x38b00004)))
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#define SDCI_CMD (*((uint32_t volatile*)(0x38b00008)))
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#define SDCI_ARGU (*((uint32_t volatile*)(0x38b0000c)))
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#define SDCI_STATE (*((uint32_t volatile*)(0x38b00010)))
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#define SDCI_STAC (*((uint32_t volatile*)(0x38b00014)))
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#define SDCI_DSTA (*((uint32_t volatile*)(0x38b00018)))
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#define SDCI_FSTA (*((uint32_t volatile*)(0x38b0001c)))
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#define SDCI_RESP0 (*((uint32_t volatile*)(0x38b00020)))
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#define SDCI_RESP1 (*((uint32_t volatile*)(0x38b00024)))
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#define SDCI_RESP2 (*((uint32_t volatile*)(0x38b00028)))
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#define SDCI_RESP3 (*((uint32_t volatile*)(0x38b0002c)))
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#define SDCI_CDIV (*((uint32_t volatile*)(0x38b00030)))
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#define SDCI_SDIO_CSR (*((uint32_t volatile*)(0x38b00034)))
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#define SDCI_IRQ (*((uint32_t volatile*)(0x38b00038)))
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#define SDCI_IRQ_MASK (*((uint32_t volatile*)(0x38b0003c)))
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#define SDCI_DATA (*((uint32_t volatile*)(0x38b00040)))
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#define SDCI_DMAADDR (*((void* volatile*)(0x38b00044)))
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#define SDCI_DMASIZE (*((uint32_t volatile*)(0x38b00048)))
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#define SDCI_DMACOUNT (*((uint32_t volatile*)(0x38b0004c)))
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#define SDCI_RESET (*((uint32_t volatile*)(0x38b0006c)))
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#define SDCI_CTRL_SDCIEN BIT(0)
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#define SDCI_CTRL_CARD_TYPE_MASK BIT(1)
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#define SDCI_CTRL_CARD_TYPE_SD 0
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#define SDCI_CTRL_CARD_TYPE_MMC BIT(1)
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#define SDCI_CTRL_BUS_WIDTH_MASK BITRANGE(2, 3)
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#define SDCI_CTRL_BUS_WIDTH_1BIT 0
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#define SDCI_CTRL_BUS_WIDTH_4BIT BIT(2)
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#define SDCI_CTRL_BUS_WIDTH_8BIT BIT(3)
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#define SDCI_CTRL_DMA_EN BIT(4)
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#define SDCI_CTRL_L_ENDIAN BIT(5)
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#define SDCI_CTRL_DMA_REQ_CON_MASK BIT(6)
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#define SDCI_CTRL_DMA_REQ_CON_NEMPTY 0
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#define SDCI_CTRL_DMA_REQ_CON_FULL BIT(6)
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#define SDCI_CTRL_CLK_SEL_MASK BIT(7)
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#define SDCI_CTRL_CLK_SEL_PCLK 0
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#define SDCI_CTRL_CLK_SEL_SDCLK BIT(7)
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#define SDCI_CTRL_BIT_8 BIT(8)
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#define SDCI_CTRL_BIT_14 BIT(14)
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#define SDCI_DCTRL_TXFIFORST BIT(0)
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#define SDCI_DCTRL_RXFIFORST BIT(1)
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#define SDCI_DCTRL_TRCONT_MASK BITRANGE(4, 5)
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#define SDCI_DCTRL_TRCONT_TX BIT(4)
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#define SDCI_DCTRL_BUS_TEST_MASK BITRANGE(6, 7)
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#define SDCI_DCTRL_BUS_TEST_TX BIT(6)
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#define SDCI_DCTRL_BUS_TEST_RX BIT(7)
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#define SDCI_CDIV_CLKDIV_MASK BITRANGE(0, 7)
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#define SDCI_CDIV_CLKDIV(x) ((x) >> 1)
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#define SDCI_CDIV_CLKDIV_2 BIT(0)
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#define SDCI_CDIV_CLKDIV_4 BIT(1)
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#define SDCI_CDIV_CLKDIV_8 BIT(2)
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#define SDCI_CDIV_CLKDIV_16 BIT(3)
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#define SDCI_CDIV_CLKDIV_32 BIT(4)
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#define SDCI_CDIV_CLKDIV_64 BIT(5)
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#define SDCI_CDIV_CLKDIV_128 BIT(6)
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#define SDCI_CDIV_CLKDIV_256 BIT(7)
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#define SDCI_CMD_CMD_NUM_MASK BITRANGE(0, 5)
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#define SDCI_CMD_CMD_NUM_SHIFT 0
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#define SDCI_CMD_CMD_NUM(x) (x)
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#define SDCI_CMD_CMD_TYPE_MASK BITRANGE(6, 7)
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#define SDCI_CMD_CMD_TYPE_BC 0
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#define SDCI_CMD_CMD_TYPE_BCR BIT(6)
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#define SDCI_CMD_CMD_TYPE_AC BIT(7)
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#define SDCI_CMD_CMD_TYPE_ADTC (BIT(6) | BIT(7))
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#define SDCI_CMD_CMD_RD_WR BIT(8)
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#define SDCI_CMD_RES_TYPE_MASK BITRANGE(16, 18)
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#define SDCI_CMD_RES_TYPE_NONE 0
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#define SDCI_CMD_RES_TYPE_R1 BIT(16)
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#define SDCI_CMD_RES_TYPE_R2 BIT(17)
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#define SDCI_CMD_RES_TYPE_R3 (BIT(16) | BIT(17))
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#define SDCI_CMD_RES_TYPE_R4 BIT(18)
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#define SDCI_CMD_RES_TYPE_R5 (BIT(16) | BIT(18))
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#define SDCI_CMD_RES_TYPE_R6 (BIT(17) | BIT(18))
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#define SDCI_CMD_RES_BUSY BIT(19)
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#define SDCI_CMD_RES_SIZE_MASK BIT(20)
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#define SDCI_CMD_RES_SIZE_48 0
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#define SDCI_CMD_RES_SIZE_136 BIT(20)
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#define SDCI_CMD_NCR_NID_MASK BIT(21)
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#define SDCI_CMD_NCR_NID_NCR 0
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#define SDCI_CMD_NCR_NID_NID BIT(21)
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#define SDCI_CMD_CMDSTR BIT(31)
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#define SDCI_STATE_DAT_STATE_MASK BITRANGE(0, 3)
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#define SDCI_STATE_DAT_STATE_IDLE 0
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#define SDCI_STATE_DAT_STATE_DAT_RCV BIT(0)
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#define SDCI_STATE_DAT_STATE_CRC_RCV BIT(1)
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#define SDCI_STATE_DAT_STATE_DAT_END (BIT(0) | BIT(1))
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#define SDCI_STATE_DAT_STATE_DAT_SET BIT(2)
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#define SDCI_STATE_DAT_STATE_DAT_OUT (BIT(0) | BIT(2))
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#define SDCI_STATE_DAT_STATE_CRC_TIME (BIT(1) | BIT(2))
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#define SDCI_STATE_DAT_STATE_CRC_OUT (BIT(0) | BIT(1) | BIT(2))
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#define SDCI_STATE_DAT_STATE_ENDB_OUT BIT(3)
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#define SDCI_STATE_DAT_STATE_ENDB_STOD (BIT(0) | BIT(3))
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#define SDCI_STATE_DAT_STATE_DAT_CRCR (BIT(1) | BIT(3))
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#define SDCI_STATE_DAT_STATE_CARD_PRG (BIT(0) | BIT(1) | BIT(3))
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#define SDCI_STATE_DAT_STATE_DAT_BUSY (BIT(2) | BIT(3))
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#define SDCI_STATE_CMD_STATE_MASK (BIT(4) | BIT(5) | BIT(6))
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#define SDCI_STATE_CMD_STATE_CMD_IDLE 0
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#define SDCI_STATE_CMD_STATE_CMD_CMDO BIT(4)
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#define SDCI_STATE_CMD_STATE_CMD_CRCO BIT(5)
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#define SDCI_STATE_CMD_STATE_CMD_TOUT (BIT(4) | BIT(5))
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#define SDCI_STATE_CMD_STATE_CMD_RESR BIT(6)
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#define SDCI_STATE_CMD_STATE_CMD_INTV (BIT(4) | BIT(6))
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#define SDCI_STAC_CLR_CMDEND BIT(2)
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#define SDCI_STAC_CLR_BIT_3 BIT(3)
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#define SDCI_STAC_CLR_RESEND BIT(4)
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#define SDCI_STAC_CLR_DATEND BIT(6)
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#define SDCI_STAC_CLR_DAT_CRCEND BIT(7)
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#define SDCI_STAC_CLR_CRC_STAEND BIT(8)
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#define SDCI_STAC_CLR_RESTOUTE BIT(15)
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#define SDCI_STAC_CLR_RESENDE BIT(16)
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#define SDCI_STAC_CLR_RESINDE BIT(17)
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#define SDCI_STAC_CLR_RESCRCE BIT(18)
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#define SDCI_STAC_CLR_WR_DATCRCE BIT(22)
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#define SDCI_STAC_CLR_RD_DATCRCE BIT(23)
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#define SDCI_STAC_CLR_RD_DATENDE0 BIT(24)
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#define SDCI_STAC_CLR_RD_DATENDE1 BIT(25)
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#define SDCI_STAC_CLR_RD_DATENDE2 BIT(26)
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#define SDCI_STAC_CLR_RD_DATENDE3 BIT(27)
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#define SDCI_STAC_CLR_RD_DATENDE4 BIT(28)
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#define SDCI_STAC_CLR_RD_DATENDE5 BIT(29)
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#define SDCI_STAC_CLR_RD_DATENDE6 BIT(30)
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#define SDCI_STAC_CLR_RD_DATENDE7 BIT(31)
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#define SDCI_DSTA_CMDRDY BIT(0)
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#define SDCI_DSTA_CMDPRO BIT(1)
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#define SDCI_DSTA_CMDEND BIT(2)
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#define SDCI_DSTA_RESPRO BIT(3)
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#define SDCI_DSTA_RESEND BIT(4)
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#define SDCI_DSTA_DATPRO BIT(5)
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#define SDCI_DSTA_DATEND BIT(6)
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#define SDCI_DSTA_DAT_CRCEND BIT(7)
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#define SDCI_DSTA_CRC_STAEND BIT(8)
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#define SDCI_DSTA_DAT_BUSY BIT(9)
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#define SDCI_DSTA_SDCLK_HOLD BIT(12)
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#define SDCI_DSTA_DAT0_STATUS BIT(13)
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#define SDCI_DSTA_WP_DECT_INPUT BIT(14)
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#define SDCI_DSTA_RESTOUTE BIT(15)
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#define SDCI_DSTA_RESENDE BIT(16)
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#define SDCI_DSTA_RESINDE BIT(17)
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#define SDCI_DSTA_RESCRCE BIT(18)
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#define SDCI_DSTA_WR_CRC_STATUS_MASK BITRANGE(19, 21)
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#define SDCI_DSTA_WR_CRC_STATUS_OK BIT(20)
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#define SDCI_DSTA_WR_CRC_STATUS_TXERR (BIT(19) | BIT(21))
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#define SDCI_DSTA_WR_CRC_STATUS_CARDERR (BIT(19) | BIT(20) | BIT(21))
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#define SDCI_DSTA_WR_DATCRCE BIT(22)
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#define SDCI_DSTA_RD_DATCRCE BIT(23)
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#define SDCI_DSTA_RD_DATENDE0 BIT(24)
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#define SDCI_DSTA_RD_DATENDE1 BIT(25)
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#define SDCI_DSTA_RD_DATENDE2 BIT(26)
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#define SDCI_DSTA_RD_DATENDE3 BIT(27)
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#define SDCI_DSTA_RD_DATENDE4 BIT(28)
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#define SDCI_DSTA_RD_DATENDE5 BIT(29)
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#define SDCI_DSTA_RD_DATENDE6 BIT(30)
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#define SDCI_DSTA_RD_DATENDE7 BIT(31)
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#define SDCI_FSTA_RX_FIFO_EMPTY BIT(0)
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#define SDCI_FSTA_RX_FIFO_FULL BIT(1)
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#define SDCI_FSTA_TX_FIFO_EMPTY BIT(2)
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#define SDCI_FSTA_TX_FIFO_FULL BIT(3)
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#define SDCI_SDIO_CSR_SDIO_RW_EN BIT(0)
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#define SDCI_SDIO_CSR_SDIO_INT_EN BIT(1)
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#define SDCI_SDIO_CSR_SDIO_RW_REQ BIT(2)
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#define SDCI_SDIO_CSR_SDIO_RW_STOP BIT(3)
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#define SDCI_SDIO_CSR_SDIO_INT_PERIOD_MASK BIT(4)
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#define SDCI_SDIO_CSR_SDIO_INT_PERIOD_MORE 0
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#define SDCI_SDIO_CSR_SDIO_INT_PERIOD_XACT BIT(4)
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#define SDCI_IRQ_DAT_DONE_INT BIT(0)
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#define SDCI_IRQ_IOCARD_IRQ_INT BIT(1)
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#define SDCI_IRQ_READ_WAIT_INT BIT(2)
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#define SDCI_IRQ_MASK_MASK_DAT_DONE_INT BIT(0)
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#define SDCI_IRQ_MASK_MASK_IOCARD_IRQ_INT BIT(1)
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#define SDCI_IRQ_MASK_MASK_READ_WAIT_INT BIT(2)
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/////CLICKWHEEL/////
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#define WHEEL00 (*((uint32_t volatile*)(0x3C200000)))
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#define WHEEL04 (*((uint32_t volatile*)(0x3C200004)))
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@ -638,6 +822,8 @@ struct dma_lli
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#define IRQ_DMAC1 17
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#define IRQ_WHEEL 23
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#define IRQ_ATA 29
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#define IRQ_MMC 44
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#endif
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@ -100,7 +100,7 @@ SECTIONS
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*(.stack)
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stackbegin = .;
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_stackbegin = .;
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. += 0x4000;
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. += 0x2000;
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stackend = .;
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_stackend = .;
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_irqstackbegin = .;
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@ -95,7 +95,7 @@ SECTIONS
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*(.stack)
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stackbegin = .;
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_stackbegin = .;
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. += 0x4000;
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. += 0x2000;
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stackend = .;
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_stackend = .;
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_irqstackbegin = .;
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@ -1,197 +0,0 @@
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/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id: ata-meg-fx.c 27935 2010-08-28 23:12:11Z funman $
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*
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* Copyright (C) 2011 by Michael Sparmann
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version 2
|
||||
* of the License, or (at your option) any later version.
|
||||
*
|
||||
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
|
||||
* KIND, either express or implied.
|
||||
*
|
||||
****************************************************************************/
|
||||
#include "config.h"
|
||||
#include "cpu.h"
|
||||
#include "kernel.h"
|
||||
#include "thread.h"
|
||||
#include "system.h"
|
||||
#include "power.h"
|
||||
#include "panic.h"
|
||||
#include "pmu-target.h"
|
||||
#include "ata.h"
|
||||
#include "ata-target.h"
|
||||
#include "s5l8702.h"
|
||||
|
||||
|
||||
static struct wakeup ata_wakeup;
|
||||
|
||||
#ifdef HAVE_ATA_DMA
|
||||
static uint32_t ata_dma_flags;
|
||||
#endif
|
||||
|
||||
|
||||
void ata_reset(void)
|
||||
{
|
||||
ATA_SWRST = 1;
|
||||
sleep(HZ / 100);
|
||||
ATA_SWRST = 0;
|
||||
sleep(HZ / 10);
|
||||
}
|
||||
|
||||
void ata_enable(bool on)
|
||||
{
|
||||
if (on)
|
||||
{
|
||||
PWRCON(0) &= ~(1 << 5);
|
||||
ATA_CFG = 0x41;
|
||||
sleep(HZ / 100);
|
||||
ATA_CFG = 0x40;
|
||||
sleep(HZ / 20);
|
||||
ata_reset();
|
||||
ATA_CCONTROL = 1;
|
||||
sleep(HZ / 5);
|
||||
ATA_PIO_TIME = 0x191f7;
|
||||
*ATA_HCYL = 0;
|
||||
while (!(ATA_PIO_READY & 2)) yield();
|
||||
}
|
||||
else
|
||||
{
|
||||
ATA_CCONTROL = 0;
|
||||
while (!(ATA_CCONTROL & 2)) yield();
|
||||
PWRCON(1) |= 1 << 5;
|
||||
}
|
||||
}
|
||||
|
||||
bool ata_is_coldstart(void)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
|
||||
void ata_device_init(void)
|
||||
{
|
||||
VIC0INTENABLE = 1 << IRQ_ATA;
|
||||
}
|
||||
|
||||
uint16_t ata_read_cbr(uint32_t volatile* reg)
|
||||
{
|
||||
while (!(ATA_PIO_READY & 2));
|
||||
volatile uint32_t __attribute__((unused)) dummy = *reg;
|
||||
while (!(ATA_PIO_READY & 1));
|
||||
return ATA_PIO_RDATA;
|
||||
}
|
||||
|
||||
void ata_write_cbr(uint32_t volatile* reg, uint16_t data)
|
||||
{
|
||||
while (!(ATA_PIO_READY & 2));
|
||||
*reg = data;
|
||||
}
|
||||
|
||||
void ata_set_pio_timings(int mode)
|
||||
{
|
||||
if (mode >= 4) ATA_PIO_TIME = 0x7083;
|
||||
if (mode >= 3) ATA_PIO_TIME = 0x2072;
|
||||
else ATA_PIO_TIME = 0x11f3;
|
||||
}
|
||||
|
||||
#ifdef HAVE_ATA_DMA
|
||||
static void ata_set_mdma_timings(unsigned int mode)
|
||||
{
|
||||
if (mode >= 2) ATA_MDMA_TIME = 0x5072;
|
||||
if (mode >= 1) ATA_MDMA_TIME = 0x7083;
|
||||
else ATA_MDMA_TIME = 0x1c175;
|
||||
}
|
||||
|
||||
static void ata_set_udma_timings(unsigned int mode)
|
||||
{
|
||||
if (mode >= 4) ATA_UDMA_TIME = 0x2010a52;
|
||||
if (mode >= 3) ATA_UDMA_TIME = 0x2020a52;
|
||||
if (mode >= 2) ATA_UDMA_TIME = 0x3030a52;
|
||||
if (mode >= 1) ATA_UDMA_TIME = 0x3050a52;
|
||||
else ATA_UDMA_TIME = 0x5071152;
|
||||
}
|
||||
|
||||
void ata_dma_set_mode(unsigned char mode)
|
||||
{
|
||||
unsigned int modeidx = mode & 0x07;
|
||||
unsigned int dmamode = mode & 0xf8;
|
||||
|
||||
if (dmamode == 0x40 && modeidx <= ATA_MAX_UDMA)
|
||||
{
|
||||
/* Using Ultra DMA */
|
||||
ata_set_udma_timings(dmamode);
|
||||
ata_dma_flags = 0x60c;
|
||||
}
|
||||
else if (dmamode == 0x20 && modeidx <= ATA_MAX_MWDMA)
|
||||
{
|
||||
/* Using Multiword DMA */
|
||||
ata_set_mdma_timings(dmamode);
|
||||
ata_dma_flags = 0x408;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Don't understand this - force PIO. */
|
||||
ata_dma_flags = 0;
|
||||
}
|
||||
}
|
||||
|
||||
bool ata_dma_setup(void *addr, unsigned long bytes, bool write)
|
||||
{
|
||||
if ((((int)addr) & 0xf) || (((int)bytes) & 0xf) || !ata_dma_flags)
|
||||
return false;
|
||||
|
||||
if (write) clean_dcache();
|
||||
else invalidate_dcache();
|
||||
ATA_CCOMMAND = 2;
|
||||
|
||||
if (write)
|
||||
{
|
||||
ATA_SBUF_START = addr;
|
||||
ATA_SBUF_SIZE = bytes;
|
||||
ATA_CFG |= 0x10;
|
||||
}
|
||||
else
|
||||
{
|
||||
ATA_TBUF_START = addr;
|
||||
ATA_TBUF_SIZE = bytes;
|
||||
ATA_CFG &= ~0x10;
|
||||
}
|
||||
ATA_XFR_NUM = bytes - 1;
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
bool ata_dma_finish(void)
|
||||
{
|
||||
ATA_CFG |= ata_dma_flags;
|
||||
ATA_CFG &= ~0x180;
|
||||
wakeup_wait(&ata_wakeup, TIMEOUT_NOBLOCK);
|
||||
ATA_IRQ = 0x1f;
|
||||
ATA_IRQ_MASK = 1;
|
||||
ATA_CCOMMAND = 1;
|
||||
if (wakeup_wait(&ata_wakeup, HZ / 2) != OBJ_WAIT_SUCCEEDED)
|
||||
{
|
||||
ATA_CCOMMAND = 2;
|
||||
ATA_CFG &= ~0x100c;
|
||||
return false;
|
||||
}
|
||||
ATA_CCOMMAND = 2;
|
||||
ATA_CFG &= ~0x100c;
|
||||
return true;
|
||||
}
|
||||
#endif /* HAVE_ATA_DMA */
|
||||
|
||||
void INT_ATA(void)
|
||||
{
|
||||
uint32_t ata_irq = ATA_IRQ;
|
||||
ATA_IRQ = ata_irq;
|
||||
if (ata_irq & ATA_IRQ_MASK) wakeup_signal(&ata_wakeup);
|
||||
ATA_IRQ_MASK = 0;
|
||||
}
|
||||
|
|
@ -1,47 +0,0 @@
|
|||
/***************************************************************************
|
||||
* __________ __ ___.
|
||||
* Open \______ \ ____ ____ | | _\_ |__ _______ ___
|
||||
* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
|
||||
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
|
||||
* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
|
||||
* \/ \/ \/ \/ \/
|
||||
* $Id: ata-target.h 25525 2010-04-07 20:01:21Z torne $
|
||||
*
|
||||
* Copyright (C) 2011 by Michael Sparmann
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version 2
|
||||
* of the License, or (at your option) any later version.
|
||||
*
|
||||
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
|
||||
* KIND, either express or implied.
|
||||
*
|
||||
****************************************************************************/
|
||||
#ifndef ATA_TARGET_H
|
||||
#define ATA_TARGET_H
|
||||
|
||||
#include "inttypes.h"
|
||||
#include "s5l8702.h"
|
||||
|
||||
#ifdef BOOTLOADER
|
||||
#define ATA_DRIVER_CLOSE
|
||||
#endif
|
||||
|
||||
#define ATA_SWAP_IDENTIFY(word) (swap16(word))
|
||||
|
||||
void ata_reset(void);
|
||||
void ata_device_init(void);
|
||||
bool ata_is_coldstart(void);
|
||||
uint16_t ata_read_cbr(uint32_t volatile* reg);
|
||||
void ata_write_cbr(uint32_t volatile* reg, uint16_t data);
|
||||
|
||||
#define ATA_OUT8(reg, data) ata_write_cbr(reg, data)
|
||||
#define ATA_OUT16(reg, data) ata_write_cbr(reg, data)
|
||||
#define ATA_IN8(reg) ata_read_cbr(reg)
|
||||
#define ATA_IN16(reg) ata_read_cbr(reg)
|
||||
|
||||
#define ATA_SET_DEVICE_FEATURES
|
||||
void ata_set_pio_timings(int mode);
|
||||
|
||||
#endif
|
||||
345
firmware/target/arm/s5l8702/ipod6g/mmcdefs-target.h
Normal file
345
firmware/target/arm/s5l8702/ipod6g/mmcdefs-target.h
Normal file
|
|
@ -0,0 +1,345 @@
|
|||
//
|
||||
//
|
||||
// Copyright 2010 TheSeven
|
||||
//
|
||||
//
|
||||
// This file is part of emCORE.
|
||||
//
|
||||
// emCORE is free software: you can redistribute it and/or
|
||||
// modify it under the terms of the GNU General Public License as
|
||||
// published by the Free Software Foundation, either version 2 of the
|
||||
// License, or (at your option) any later version.
|
||||
//
|
||||
// emCORE is distributed in the hope that it will be useful,
|
||||
// but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
|
||||
// See the GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License along
|
||||
// with emCORE. If not, see <http://www.gnu.org/licenses/>.
|
||||
//
|
||||
//
|
||||
|
||||
|
||||
#ifndef __CONSTANTS_MMC_H__
|
||||
#define __CONSTANTS_MMC_H__
|
||||
|
||||
|
||||
#ifndef MIN
|
||||
#define MIN(a, b) (((a)<(b))?(a):(b))
|
||||
#endif
|
||||
|
||||
#ifndef MAX
|
||||
#define MAX(a, b) (((a)>(b))?(a):(b))
|
||||
#endif
|
||||
|
||||
#define BIT(x) (1 << (x))
|
||||
#define BITRANGE(x, y) ((0xfffffffful >> (31 + (x) - (y))) << (x))
|
||||
|
||||
#define ERR_RC(val) (BIT(31) | (val))
|
||||
#define IS_ERR(val) (val & BIT(31))
|
||||
#define RET_ERR(val) \
|
||||
{ \
|
||||
return ERR_RC(val); \
|
||||
}
|
||||
#define RET_ERR_MTX(val, mutex) \
|
||||
{ \
|
||||
mutex_unlock(mutex); \
|
||||
return ERR_RC(val); \
|
||||
}
|
||||
#define PASS_RC(expr, bits, val) \
|
||||
{ \
|
||||
int PASS_RC_rc = (expr); \
|
||||
if (IS_ERR(PASS_RC_rc)) \
|
||||
return ERR_RC((PASS_RC_rc << (bits)) | (val)); \
|
||||
}
|
||||
#define PASS_RC_MTX(expr, bits, val, mutex) \
|
||||
{ \
|
||||
int PASS_RC_MTX_rc = (expr); \
|
||||
if (IS_ERR(PASS_RC_MTX_rc)) \
|
||||
{ \
|
||||
mutex_unlock(mutex); \
|
||||
return ERR_RC((PASS_RC_MTX_rc << (bits)) | (val)); \
|
||||
} \
|
||||
}
|
||||
|
||||
#define TIMEOUT_EXPIRED(a,b) TIME_AFTER(USEC_TIMER,a + b)
|
||||
#define udelay(duration) \
|
||||
{ \
|
||||
long timestamp = USEC_TIMER; \
|
||||
while (!TIMEOUT_EXPIRED(timestamp, (long)(duration))); \
|
||||
}
|
||||
|
||||
|
||||
#define MMC_CMD_GO_IDLE_STATE 0
|
||||
#define MMC_CMD_SEND_OP_COND 1
|
||||
#define MMC_CMD_ALL_SEND_CID 2
|
||||
#define MMC_CMD_SET_RELATIVE_ADDR 3
|
||||
#define MMC_CMD_SET_DSR 4
|
||||
#define MMC_CMD_SLEEP_AWAKE 5
|
||||
#define MMC_CMD_SWITCH 6
|
||||
#define MMC_CMD_SELECT_CARD 7
|
||||
#define MMC_CMD_SEND_EXT_CSD 8
|
||||
#define MMC_CMD_SEND_CSD 9
|
||||
#define MMC_CMD_SEND_CID 10
|
||||
#define MMC_CMD_READ_DAT_UNTIL_STOP 11
|
||||
#define MMC_CMD_STOP_TRANSMISSION 12
|
||||
#define MMC_CMD_SEND_STATUS 13
|
||||
#define MMC_CMD_BUSTEST_R 14
|
||||
#define MMC_CMD_GO_INAVTIVE_STATE 15
|
||||
#define MMC_CMD_SET_BLOCKLEN 16
|
||||
#define MMC_CMD_READ_SINGLE_BLOCK 17
|
||||
#define MMC_CMD_READ_MULTIPLE_BLOCK 18
|
||||
#define MMC_CMD_BUSTEST_W 19
|
||||
#define MMC_CMD_WRITE_DAT_UNTIL_STOP 20
|
||||
#define MMC_CMD_SET_BLOCK_COUNT 23
|
||||
#define MMC_CMD_WRITE_BLOCK 24
|
||||
#define MMC_CMD_WRITE_MULTIPLE_BLOCK 25
|
||||
#define MMC_CMD_PROGRAM_CID 26
|
||||
#define MMC_CMD_PROGRAM_CSD 27
|
||||
#define MMC_CMD_SET_WRITE_PROT 28
|
||||
#define MMC_CMD_CLR_WRITE_PROT 29
|
||||
#define MMC_CMD_SEND_WRITE_PROT 30
|
||||
#define MMC_CMD_ERASE_GROUP_START 35
|
||||
#define MMC_CMD_ERASE_GROUP_END 36
|
||||
#define MMC_CMD_ERASE 38
|
||||
#define MMC_CMD_FAST_IO 39
|
||||
#define MMC_CMD_GO_IRQ_STATE 40
|
||||
#define MMC_CMD_LOCK_UNLOCK 42
|
||||
#define MMC_CMD_APP_CMD 55
|
||||
#define MMC_CMD_GEN_CMD 56
|
||||
#define MMC_CMD_CEATA_RW_MULTIPLE_REG 60
|
||||
#define MMC_CMD_CEATA_RW_MULTIPLE_BLOCK 61
|
||||
|
||||
#define MMC_CMD_SEND_OP_COND_OCR_MASK BITRANGE(0, 31)
|
||||
#define MMC_CMD_SEND_OP_COND_OCR_SHIFT 0
|
||||
#define MMC_CMD_SEND_OP_COND_OCR(x) (x)
|
||||
|
||||
#define MMC_CMD_SET_RELATIVE_ADDR_RCA_MASK BITRANGE(16, 31)
|
||||
#define MMC_CMD_SET_RELATIVE_ADDR_RCA_SHIFT 16
|
||||
#define MMC_CMD_SET_RELATIVE_ADDR_RCA(x) ((x) << 16)
|
||||
|
||||
#define MMC_CMD_SET_DSR_DSR_MASK BITRANGE(16, 31)
|
||||
#define MMC_CMD_SET_DSR_DSR_SHIFT 16
|
||||
#define MMC_CMD_SET_DSR_DSR(x) ((x) << 16)
|
||||
|
||||
#define MMC_CMD_SLEEP_AWAKE_SLEEP_AWAKE_MASK BIT(15)
|
||||
#define MMC_CMD_SLEEP_AWAKE_SLEEP_AWAKE_AWAKE 0
|
||||
#define MMC_CMD_SLEEP_AWAKE_SLEEP_AWAKE_SLEEP BIT(15)
|
||||
#define MMC_CMD_SLEEP_AWAKE_RCA_MASK BITRANGE(16, 31)
|
||||
#define MMC_CMD_SLEEP_AWAKE_RCA_SHIFT 16
|
||||
#define MMC_CMD_SLEEP_AWAKE_RCA(x) ((x) << 16)
|
||||
|
||||
#define MMC_CMD_SWITCH_ACCESS_MASK BITRANGE(24, 25);
|
||||
#define MMC_CMD_SWITCH_ACCESS_CMDSET 0
|
||||
#define MMC_CMD_SWITCH_ACCESS_SET_BITS BIT(24)
|
||||
#define MMC_CMD_SWITCH_ACCESS_CLEAR_BITS BIT(25)
|
||||
#define MMC_CMD_SWITCH_ACCESS_WRITE_BYTE (BIT(24) | BIT(25))
|
||||
#define MMC_CMD_SWTICH_INDEX_MASK BITRANGE(16, 23);
|
||||
#define MMC_CMD_SWITCH_INDEX_SHIFT 16
|
||||
#define MMC_CMD_SWITCH_INDEX(x) ((x) << 16)
|
||||
#define MMC_CMD_SWTICH_VALUE_MASK BITRANGE(8, 15);
|
||||
#define MMC_CMD_SWITCH_VALUE_SHIFT 8
|
||||
#define MMC_CMD_SWITCH_VALUE(x) ((x) << 8)
|
||||
#define MMC_CMD_SWTICH_CMDSET_MASK BITRANGE(0, 2);
|
||||
#define MMC_CMD_SWITCH_CMDSET_STANDARD_MMC 0
|
||||
|
||||
#define MMC_CMD_SELECT_CARD_RCA_MASK BITRANGE(16, 31)
|
||||
#define MMC_CMD_SELECT_CARD_RCA_SHIFT 16
|
||||
#define MMC_CMD_SELECT_CARD_RCA(x) ((x) << 16)
|
||||
|
||||
#define MMC_CMD_SEND_CSD_RCA_MASK BITRANGE(16, 31)
|
||||
#define MMC_CMD_SEND_CSD_RCA_SHIFT 16
|
||||
#define MMC_CMD_SEND_CSD_RCA(x) ((x) << 16)
|
||||
|
||||
#define MMC_CMD_SEND_CID_RCA_MASK BITRANGE(16, 31)
|
||||
#define MMC_CMD_SEND_CID_RCA_SHIFT 16
|
||||
#define MMC_CMD_SEND_CID_RCA(x) ((x) << 16)
|
||||
|
||||
#define MMC_CMD_READ_DAT_UNTIL_STOP_ADDRESS_MASK BITRANGE(0, 31)
|
||||
#define MMC_CMD_READ_DAT_UNTIL_STOP_ADDRESS_SHIFT 0
|
||||
#define MMC_CMD_READ_DAT_UNTIL_STOP_ADDRESS(x) (x)
|
||||
|
||||
#define MMC_CMD_SEND_STATUS_RCA_MASK BITRANGE(16, 31)
|
||||
#define MMC_CMD_SEND_STATUS_RCA_SHIFT 16
|
||||
#define MMC_CMD_SEND_STATUS_RCA(x) ((x) << 16)
|
||||
|
||||
#define MMC_CMD_GO_INACTIVE_STATE_RCA_MASK BITRANGE(16, 31)
|
||||
#define MMC_CMD_GO_INACTIVE_STATE_RCA_SHIFT 16
|
||||
#define MMC_CMD_GO_INACTIVE_STATE_RCA(x) ((x) << 16)
|
||||
|
||||
#define MMC_CMD_SET_BLOCKLEN_LENGTH_MASK BITRANGE(0, 31)
|
||||
#define MMC_CMD_SET_BLOCKLEN_LENGTH_SHIFT 0
|
||||
#define MMC_CMD_SET_BLOCKLEN_LENGTH(x) (x)
|
||||
|
||||
#define MMC_CMD_READ_SINGLE_BLOCK_ADDRESS_MASK BITRANGE(0, 31)
|
||||
#define MMC_CMD_READ_SINGLE_BLOCK_ADDRESS_SHIFT 0
|
||||
#define MMC_CMD_READ_SINGLE_BLOCK_ADDRESS(x) (x)
|
||||
|
||||
#define MMC_CMD_READ_MULTIPLE_BLOCK_ADDRESS_MASK BITRANGE(0, 31)
|
||||
#define MMC_CMD_READ_MULTIPLE_BLOCK_ADDRESS_SHIFT 0
|
||||
#define MMC_CMD_READ_MULTIPLE_BLOCK_ADDRESS(x) (x)
|
||||
|
||||
#define MMC_CMD_WRITE_DAT_UNTIL_STOP_ADDRESS_MASK BITRANGE(0, 31)
|
||||
#define MMC_CMD_WRITE_DAT_UNTIL_STOP_ADDRESS_SHIFT 0
|
||||
#define MMC_CMD_WRITE_DAT_UNTIL_STOP_ADDRESS(x) (x)
|
||||
|
||||
#define MMC_CMD_SET_BLOCK_COUNT_RELIABLE BIT(31)
|
||||
#define MMC_CMD_SET_BLOCK_COUNT_COUNT_MASK BITRANGE(0, 15)
|
||||
#define MMC_CMD_SET_BLOCK_COUNT_COUNT_SHIFT 0
|
||||
#define MMC_CMD_SET_BLOCK_COUNT_COUNT(x) (x)
|
||||
|
||||
#define MMC_CMD_WRITE_BLOCK_ADDRESS_MASK BITRANGE(0, 31)
|
||||
#define MMC_CMD_WRITE_BLOCK_ADDRESS_SHIFT 0
|
||||
#define MMC_CMD_WRITE_BLOCK_ADDRESS(x) (x)
|
||||
|
||||
#define MMC_CMD_WRITE_MULTIPLE_BLOCK_ADDRESS_MASK BITRANGE(0, 31)
|
||||
#define MMC_CMD_WRITE_MULTIPLE_BLOCK_ADDRESS_SHIFT 0
|
||||
#define MMC_CMD_WRITE_MULTIPLE_BLOCK_ADDRESS(x) (x)
|
||||
|
||||
#define MMC_CMD_SET_WRITE_PROT_ADDRESS_MASK BITRANGE(0, 31)
|
||||
#define MMC_CMD_SET_WRITE_PROT_ADDRESS_SHIFT 0
|
||||
#define MMC_CMD_SET_WRITE_PROT_ADDRESS(x) (x)
|
||||
|
||||
#define MMC_CMD_CLR_WRITE_PROT_ADDRESS_MASK BITRANGE(0, 31)
|
||||
#define MMC_CMD_CLR_WRITE_PROT_ADDRESS_SHIFT 0
|
||||
#define MMC_CMD_CLR_WRITE_PROT_ADDRESS(x) (x)
|
||||
|
||||
#define MMC_CMD_SEND_WRITE_PROT_ADDRESS_MASK BITRANGE(0, 31)
|
||||
#define MMC_CMD_SEND_WRITE_PROT_ADDRESS_SHIFT 0
|
||||
#define MMC_CMD_SEND_WRITE_PROT_ADDRESS(x) (x)
|
||||
|
||||
#define MMC_CMD_ERASE_GROUP_START_ADDRESS_MASK BITRANGE(0, 31)
|
||||
#define MMC_CMD_ERASE_GROUP_START_ADDRESS_SHIFT 0
|
||||
#define MMC_CMD_ERASE_GROUP_START_ADDRESS(x) (x)
|
||||
|
||||
#define MMC_CMD_ERASE_GROUP_END_ADDRESS_MASK BITRANGE(0, 31)
|
||||
#define MMC_CMD_ERASE_GROUP_END_ADDRESS_SHIFT 0
|
||||
#define MMC_CMD_ERASE_GROUP_END_ADDRESS(x) (x)
|
||||
|
||||
#define MMC_CMD_FAST_IO_RCA_MASK BITRANGE(16, 31)
|
||||
#define MMC_CMD_FAST_IO_RCA_SHIFT 16
|
||||
#define MMC_CMD_FAST_IO_RCA(x) ((x) << 16)
|
||||
#define MMC_CMD_FAST_IO_DIRECTION_MASK BIT(15)
|
||||
#define MMC_CMD_FAST_IO_DIRECTION_READ 0
|
||||
#define MMC_CMD_FAST_IO_DIRECTION_WRITE BIT(15)
|
||||
#define MMC_CMD_FAST_IO_ADDRESS_MASK BITRANGE(8, 14)
|
||||
#define MMC_CMD_FAST_IO_ADDRESS_SHIFT 8
|
||||
#define MMC_CMD_FAST_IO_ADDRESS(x) ((x) << 8)
|
||||
#define MMC_CMD_FAST_IO_DATA_MASK BITRANGE(0, 7)
|
||||
#define MMC_CMD_FAST_IO_DATA_SHIFT 0
|
||||
#define MMC_CMD_FAST_IO_DATA(x) (x)
|
||||
|
||||
#define MMC_CMD_APP_CMD_RCA_MASK BITRANGE(16, 31)
|
||||
#define MMC_CMD_APP_CMD_RCA_SHIFT 16
|
||||
#define MMC_CMD_APP_CMD_RCA(x) ((x) << 16)
|
||||
|
||||
#define MMC_CMD_GEN_CMD_DIRECTION_MASK BIT(0)
|
||||
#define MMC_CMD_GEN_CMD_DIRECTION_READ 0
|
||||
#define MMC_CMD_GEN_CMD_DIRECTION_WRITE BIT(0)
|
||||
|
||||
#define MMC_CMD_CEATA_RW_MULTIPLE_REG_DIRECTION_MASK BIT(31)
|
||||
#define MMC_CMD_CEATA_RW_MULTIPLE_REG_DIRECTION_READ 0
|
||||
#define MMC_CMD_CEATA_RW_MULTIPLE_REG_DIRECTION_WRITE BIT(31)
|
||||
#define MMC_CMD_CEATA_RW_MULTIPLE_REG_ADDRESS_MASK BITRANGE(16, 23)
|
||||
#define MMC_CMD_CEATA_RW_MULTIPLE_REG_ADDRESS_SHIFT 16
|
||||
#define MMC_CMD_CEATA_RW_MULTIPLE_REG_ADDRESS(x) ((x) << 16)
|
||||
#define MMC_CMD_CEATA_RW_MULTIPLE_REG_COUNT_MASK BITRANGE(0, 7)
|
||||
#define MMC_CMD_CEATA_RW_MULTIPLE_REG_COUNT_SHIFT 0
|
||||
#define MMC_CMD_CEATA_RW_MULTIPLE_REG_COUNT(x) (x)
|
||||
|
||||
#define MMC_CMD_CEATA_RW_MULTIPLE_BLOCK_DIRECTION_MASK BIT(31)
|
||||
#define MMC_CMD_CEATA_RW_MULTIPLE_BLOCK_DIRECTION_READ 0
|
||||
#define MMC_CMD_CEATA_RW_MULTIPLE_BLOCK_DIRECTION_WRITE BIT(31)
|
||||
#define MMC_CMD_CEATA_RW_MULTIPLE_BLOCK_COUNT_MASK BITRANGE(0, 15)
|
||||
#define MMC_CMD_CEATA_RW_MULTIPLE_BLOCK_COUNT_SHIFT 0
|
||||
#define MMC_CMD_CEATA_RW_MULTIPLE_BLOCK_COUNT(x) (x)
|
||||
|
||||
#define MMC_CMD_SWITCH_FIELD_ERASE_GROUP_DEF 175
|
||||
#define MMC_CMD_SWITCH_FIELD_BOOT_BUS_WIDTH 177
|
||||
#define MMC_CMD_SWITCH_FIELD_BOOT_CONFIG 179
|
||||
#define MMC_CMD_SWITCH_FIELD_ERASED_MEM_CONT 181
|
||||
#define MMC_CMD_SWITCH_FIELD_BUS_WIDTH 183
|
||||
#define MMC_CMD_SWITCH_FIELD_HS_TIMING 185
|
||||
#define MMC_CMD_SWITCH_FIELD_POWER_CLASS 187
|
||||
#define MMC_CMD_SWITCH_FIELD_CMD_SET_REV 189
|
||||
#define MMC_CMD_SWITCH_FIELD_CMD_SET 191
|
||||
#define MMC_CMD_SWITCH_FIELD_EXT_CSD_REV 192
|
||||
#define MMC_CMD_SWITCH_FIELD_CSD_STRUCTURE 194
|
||||
#define MMC_CMD_SWITCH_FIELD_CARD_TYPE 196
|
||||
#define MMC_CMD_SWITCH_FIELD_PWR_CL_52_195 200
|
||||
#define MMC_CMD_SWITCH_FIELD_PWR_CL_26_195 201
|
||||
#define MMC_CMD_SWITCH_FIELD_PWR_CL_52_360 202
|
||||
#define MMC_CMD_SWITCH_FIELD_PWR_CL_26_360 203
|
||||
#define MMC_CMD_SWITCH_FIELD_MIN_PERF_R_4_26 205
|
||||
#define MMC_CMD_SWITCH_FIELD_MIN_PERF_W_4_26 206
|
||||
#define MMC_CMD_SWITCH_FIELD_MIN_PERF_R_8_26_4_52 207
|
||||
#define MMC_CMD_SWITCH_FIELD_MIN_PERF_W_8_26_4_52 208
|
||||
#define MMC_CMD_SWITCH_FIELD_MIN_PERF_R_8_52 209
|
||||
#define MMC_CMD_SWITCH_FIELD_MIN_PERF_W_8_52 210
|
||||
#define MMC_CMD_SWITCH_FIELD_SEC_COUNT_0 212
|
||||
#define MMC_CMD_SWITCH_FIELD_SEC_COUNT_1 213
|
||||
#define MMC_CMD_SWITCH_FIELD_SEC_COUNT_2 214
|
||||
#define MMC_CMD_SWITCH_FIELD_SEC_COUNT_3 215
|
||||
#define MMC_CMD_SWITCH_FIELD_S_A_TIMEOUT 217
|
||||
#define MMC_CMD_SWITCH_FIELD_S_C_VCCQ 219
|
||||
#define MMC_CMD_SWITCH_FIELD_S_C_VCC 220
|
||||
#define MMC_CMD_SWITCH_FIELD_HC_WP_GRP_SIZE 221
|
||||
#define MMC_CMD_SWITCH_FIELD_REL_WR_SEC_C 222
|
||||
#define MMC_CMD_SWITCH_FIELD_ERASE_TIMEOUT_MULT 223
|
||||
#define MMC_CMD_SWITCH_FIELD_HC_ERASE_GRP_SIZE 224
|
||||
#define MMC_CMD_SWITCH_FIELD_ACC_SIZE 225
|
||||
#define MMC_CMD_SWITCH_FIELD_BOOT_SIZE_MULTI 226
|
||||
#define MMC_CMD_SWITCH_FIELD_S_CMD_SET 504
|
||||
|
||||
#define MMC_CMD_SWITCH_FIELD_BUS_WIDTH_1BIT 0
|
||||
#define MMC_CMD_SWITCH_FIELD_BUS_WIDTH_4BIT 1
|
||||
#define MMC_CMD_SWITCH_FIELD_BUS_WIDTH_8BIT 2
|
||||
|
||||
#define MMC_CMD_SWITCH_FIELD_HS_TIMING_LOW_SPEED 0
|
||||
#define MMC_CMD_SWITCH_FIELD_HS_TIMING_HIGH_SPEED 1
|
||||
|
||||
#define MMC_STATUS_APP_CMD BIT(5)
|
||||
#define MMC_STATUS_SWITCH_ERROR BIT(7)
|
||||
#define MMC_STATUS_READY_FOR_DATA BIT(8)
|
||||
#define MMC_STATUS_CURRENT_STATE_MASK BITRANGE(9, 12)
|
||||
#define MMC_STATUS_CURRENT_STATE_IDLE 0
|
||||
#define MMC_STATUS_CURRENT_STATE_READY BIT(9)
|
||||
#define MMC_STATUS_CURRENT_STATE_IDENT BIT(10)
|
||||
#define MMC_STATUS_CURRENT_STATE_STBY (BIT(9) | BIT(10))
|
||||
#define MMC_STATUS_CURRENT_STATE_TRAN BIT(11)
|
||||
#define MMC_STATUS_CURRENT_STATE_DATA (BIT(9) | BIT(11))
|
||||
#define MMC_STATUS_CURRENT_STATE_RCV (BIT(10) | BIT(11))
|
||||
#define MMC_STATUS_CURRENT_STATE_PRG (BIT(9) | BIT(10) | BIT(11))
|
||||
#define MMC_STATUS_CURRENT_STATE_DIS BIT(12)
|
||||
#define MMC_STATUS_CURRENT_STATE_BTST (BIT(9) | BIT(12))
|
||||
#define MMC_STATUS_CURRENT_STATE_SLP (BIT(10) | BIT(12))
|
||||
#define MMC_STATUS_ERASE_RESET BIT(13)
|
||||
#define MMC_STATUS_WP_ERASE_SKIP BIT(15)
|
||||
#define MMC_STATUS_CID_CSD_OVERWRITE BIT(16)
|
||||
#define MMC_STATUS_OVERRUN BIT(17)
|
||||
#define MMC_STATUS_UNDERRUN BIT(18)
|
||||
#define MMC_STATUS_ERROR BIT(19)
|
||||
#define MMC_STATUS_CC_ERROR BIT(20)
|
||||
#define MMC_STATUS_CARD_ECC_FAILED BIT(21)
|
||||
#define MMC_STATUS_ILLEGAL_COMMAND BIT(22)
|
||||
#define MMC_STATUS_COM_CRC_ERROR BIT(23)
|
||||
#define MMC_STATUS_LOCK_UNLOCK_FAILED BIT(24)
|
||||
#define MMC_STATUS_CARD_IS_LOCKED BIT(25)
|
||||
#define MMC_STATUS_WP_VIOLATION BIT(26)
|
||||
#define MMC_STATUS_ERASE_PARAM BIT(27)
|
||||
#define MMC_STATUS_ERASE_SEQ_ERROR BIT(28)
|
||||
#define MMC_STATUS_BLOCK_LEN_ERROR BIT(29)
|
||||
#define MMC_STATUS_ADDRESS_MISALIGN BIT(30)
|
||||
#define MMC_STATUS_ADDRESS_OUT_OF_RANGE BIT(31)
|
||||
|
||||
#define MMC_OCR_170_195 BIT(7)
|
||||
#define MMC_OCR_200_260 BITRANGE(8, 14)
|
||||
#define MMC_OCR_270_360 BITRANGE(15, 23)
|
||||
#define MMC_OCR_ACCESS_MODE_MASK BITRANGE(29, 30)
|
||||
#define MMC_OCR_ACCESS_MODE_BYTE 0
|
||||
#define MMC_OCR_ACCESS_MODE_SECTOR BIT(30)
|
||||
#define MMC_OCR_POWER_UP_DONE BIT(31)
|
||||
|
||||
|
||||
#endif
|
||||
1142
firmware/target/arm/s5l8702/ipod6g/storage_ata-ipod6g.c
Normal file
1142
firmware/target/arm/s5l8702/ipod6g/storage_ata-ipod6g.c
Normal file
File diff suppressed because it is too large
Load Diff
|
|
@ -97,7 +97,7 @@ default_interrupt(INT_IRQ40);
|
|||
default_interrupt(INT_IRQ41);
|
||||
default_interrupt(INT_IRQ42);
|
||||
default_interrupt(INT_IRQ43);
|
||||
default_interrupt(INT_IRQ44);
|
||||
default_interrupt(INT_MMC);
|
||||
default_interrupt(INT_IRQ45);
|
||||
default_interrupt(INT_IRQ46);
|
||||
default_interrupt(INT_IRQ47);
|
||||
|
|
@ -169,7 +169,7 @@ static void (* const irqvector[])(void) =
|
|||
INT_DMAC0,INT_DMAC1,INT_IRQ18,INT_USB_FUNC,INT_IRQ20,INT_IRQ21,INT_IRQ22,INT_WHEEL,
|
||||
INT_IRQ24,INT_IRQ25,INT_IRQ26,INT_IRQ27,INT_IRQ28,INT_ATA,INT_IRQ30,INT_IRQ31,
|
||||
INT_IRQ32,INT_IRQ33,INT_IRQ34,INT_IRQ35,INT_IRQ36,INT_IRQ37,INT_IRQ38,INT_IRQ39,
|
||||
INT_IRQ40,INT_IRQ41,INT_IRQ42,INT_IRQ43,INT_IRQ55,INT_IRQ56,INT_IRQ57,INT_IRQ58,
|
||||
INT_IRQ40,INT_IRQ41,INT_IRQ42,INT_IRQ43,INT_MMC,INT_IRQ45,INT_IRQ46,INT_IRQ47,
|
||||
INT_IRQ48,INT_IRQ49,INT_IRQ50,INT_IRQ51,INT_IRQ52,INT_IRQ53,INT_IRQ54,INT_IRQ55,
|
||||
INT_IRQ56,INT_IRQ57,INT_IRQ58,INT_IRQ59,INT_IRQ60,INT_IRQ61,INT_IRQ62,INT_IRQ63
|
||||
};
|
||||
|
|
@ -218,6 +218,8 @@ void system_init(void)
|
|||
{
|
||||
pmu_init();
|
||||
VIC0INTENABLE = 1 << IRQ_WHEEL;
|
||||
VIC0INTENABLE = 1 << IRQ_ATA;
|
||||
VIC1INTENABLE = 1 << (IRQ_MMC - 32);
|
||||
}
|
||||
|
||||
void system_reboot(void)
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user