Gigabeat S memory management stuff.
* Moved crt0.S to imx31 subdirectory, as it was the last target using the unified file. * DRAM is now remapped to 0x0, facilitating interrupts (which aren't done yet) git-svn-id: svn://svn.rockbox.org/rockbox/trunk@15965 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Will Robertson
parent
a9933ce32d
commit
32f6109fb1
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@ -108,7 +108,7 @@ void main(void)
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printf("Firmware file: %s", buf);
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printf("Loading firmware");
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unsigned char *loadbuffer = (unsigned char *)0x88000000;
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unsigned char *loadbuffer = (unsigned char *)0x0;
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int buffer_size = 1024*1024;
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rc = load_firmware(loadbuffer, buf, buffer_size);
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@ -326,6 +326,8 @@ target/arm/tms320dm320/crt0.S
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target/arm/s3c2440/crt0.S
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#elif defined(CPU_TCC77X)
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target/arm/tcc77x/crt0.S
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#elif CONFIG_CPU==IMX31L
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target/arm/imx31/crt0.S
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#elif defined(CPU_ARM)
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target/arm/crt0.S
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#endif /* defined(CPU_*) */
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@ -15,6 +15,8 @@ INPUT(target/arm/tms320dm320/crt0.o)
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INPUT(target/arm/s3c2440/crt0.o)
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#elif CONFIG_CPU == PNX0101
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INPUT(target/arm/pnx0101/crt0-pnx0101.o)
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#elif CONFIG_CPU == IMX31L
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INPUT(target/arm/imx31/crt0.o)
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#elif defined(CPU_ARM)
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INPUT(target/arm/crt0.o)
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#endif
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@ -70,7 +72,7 @@ INPUT(target/sh/crt0.o)
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#define IRAMORIG 0x00000000
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#define IRAMSIZE 0x4000
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#elif CONFIG_CPU==IMX31L
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#define DRAMORIG (0x88000000 + STUBOFFSET)
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#define DRAMORIG (0x0 + STUBOFFSET)
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#define IRAMORIG 0x1FFFC000
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#define IRAMSIZE 0x4000
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#else
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@ -15,6 +15,8 @@ INPUT(target/arm/tms320dm320/crt0.o)
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INPUT(target/arm/s3c2440/crt0.o)
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#elif defined(CPU_TCC77X)
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INPUT(target/arm/tcc77x/crt0.o)
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#elif CONFIG_CPU==IMX31L
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INPUT(target/arm/imx31/crt0.o)
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#else
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INPUT(target/arm/crt0.o)
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#endif
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@ -35,12 +35,7 @@ start:
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*/
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newstart:
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#if CONFIG_CPU == IMX31L
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mov r0,#0xD3
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msr cpsr, r0
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#else
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msr cpsr, #0xd3 /* enter supervisor mode, disable IRQ */
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#endif
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#if !defined(BOOTLOADER)
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#if !defined(DEBUG)
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@ -60,11 +55,7 @@ newstart:
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ldr r0, =fiq_handler
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str r0, [r1, #28]
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#endif
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#endif
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#if !defined(BOOTLOADER)
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#if !defined(STUB)
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/* Zero out IBSS */
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ldr r2, =_iedata
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ldr r3, =_iend
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@ -83,7 +74,6 @@ newstart:
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ldrhi r5, [r2], #4
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strhi r5, [r3], #4
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bhi 1b
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#endif /* !STUB */
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#endif /* !BOOTLOADER */
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/* Initialise bss section to zero */
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@ -108,8 +98,6 @@ newstart:
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#ifdef BOOTLOADER
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/* Code for ARM bootloader targets other than iPod go here */
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#if CONFIG_CPU == IMX31L
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mov r0, #0
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mcr 15, 0, r0, c7, c7, 0 /* invalidate I cache and D cache */
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mcr 15, 0, r0, c8, c7, 0 /* invalidate TLBs */
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@ -169,13 +157,83 @@ L2_loop:
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mov r0,#0xd3
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msr cpsr, r0
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ldr sp, =stackend
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/*remap memory as well as exception vectors*/
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/*for now this will be done in bootloader, especially
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if usb will be needed within the bootloader to load the
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main firmware file. Interrupts will be needed for this
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(whether they be swi or irq)*/
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bl memory_init
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/* TTB Initialisation */
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ldr r3, =(0x80000000+64*1024*1024-TTB_SIZE)
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mov r1, #0
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ldr r2, =(0x80000000+64*1024*1024)
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ttbloop:
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str r1, [r3], #4
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cmp r3, r2
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bne ttbloop
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/* Set TTB base address */
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ldr r3, =(0x80000000+64*1024*1024-TTB_SIZE)
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mcr 15, 0 ,r3, cr2, cr0, 0
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/* Set all domains to manager status */
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mvn r3, #0
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mcr 15, 0, r3, cr3, cr0, 0
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/* Set page tables */
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/* Map each memory loc to itself, no cache */
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mov r1, #0 /* Physical address */
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ldr r3, =(0x80000000+64*1024*1024-TTB_SIZE) /* TTB pointer */
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ldr r4, =(0x80000000+64*1024*1024-TTB_SIZE+0x4000) /* End position */
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maploop1:
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mov r2, r1
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orr r2, r2, #(1<<10) /* superuser - r/w, user - no access */
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//orr r2, r2, #(0<<5) /* domain 0th */
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orr r2, r2, #(1<<4) /* should be "1" */
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orr r2, r2, #(1<<1) /* Section signature */
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str r2, [r3], #4
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add r1, r1, #(1<<20)
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cmp r3, r4
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bne maploop1
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/* Map 0x80000000 -> 0x0, cached */
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mov r1, #0x80000000 /* Physical address */
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ldr r3, =(0x80000000+64*1024*1024-TTB_SIZE) /* TTB pointer */
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ldr r4, =(0x80000000+64*1024*1024-TTB_SIZE+256) /* End position */
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maploop2:
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mov r2, r1
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orr r2, r2, #(1<<10) /* superuser - r/w, user - no access */
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//orr r2, r2, #(0<<5) /* domain 0th */
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orr r2, r2, #(1<<4) /* should be "1" */
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orr r2, r2, #(1<<3) /* cache flags */
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orr r2, r2, #(1<<2) /* more cache stuff */
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orr r2, r2, #(1<<1) /* Section signature */
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str r2, [r3], #4
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add r1, r1, #(1<<20)
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cmp r3, r4
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bne maploop2
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/* Enable MMU */
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mrc 15, 0, r3, cr1, cr0, 0
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tst r3, #0x4
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bleq clean_dcache
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tst r3, #0x1000
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bleq clean_dcache
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mov r0, #0
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mcr 15, 0, r0, cr8, cr7, 0 /* Invalidate TLB */
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mcr 15, 0, r0, cr7, cr7, 0 /* Invalidate icache and dcache */
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mrc 15, 0, r0, cr1, cr0, 0
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orr r0, r0, #1 /* enable mmu bit */
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orr r0, r0, #(1<<2) /* enable dcache */
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orr r0, r0, #(1<<12) /* enable icache */
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mcr 15, 0, r0, cr1, cr0, 0
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nop
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nop
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nop
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nop
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mov r0,#0
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ldr r1,=_vectorstart
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mov r2,#0
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@ -253,7 +311,6 @@ irq_stack:
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.space 256*4
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fiq_stack:
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#endif
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#else /* BOOTLOADER */
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@ -276,9 +333,7 @@ fiq_stack:
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/* main() should never return */
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/* Exception handlers. Will be copied to address 0 after memory remapping */
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#if CONFIG_CPU == IMX31L
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_vectorstart:
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#endif
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.section .vectors,"aw"
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ldr pc, [pc, #24]
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ldr pc, [pc, #24]
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@ -303,11 +358,9 @@ vectors:
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.text
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#ifndef STUB
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.global irq
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.global fiq
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.global UIE
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#endif
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/* All illegal exceptions call into UIE with exception address as first
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parameter. This is calculated differently depending on which exception
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@ -336,11 +389,6 @@ data_abort_handler:
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mov r1, #2
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b UIE
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#ifdef STUB
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UIE:
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b UIE
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#endif
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/* 256 words of IRQ stack */
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.space 256*4
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irq_stack:
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