Gigabeat S now uses the shared ARM MMU code rather than the (mostly duplicated) private code. No functional change.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@15961 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Will Robertson
parent
0fb794df81
commit
383a32a7ae
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@ -598,6 +598,7 @@ target/arm/s3c2440/gigabeat-fx/pcm-meg-fx.c
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#ifdef GIGABEAT_S
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#ifndef SIMULATOR
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target/arm/mmu-arm.c
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target/arm/imx31/gigabeat-s/adc-imx31.c
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target/arm/imx31/gigabeat-s/ata-imx31.c
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target/arm/imx31/gigabeat-s/backlight-imx31.c
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@ -28,7 +28,7 @@
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//when background memory is written.
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#define LCD_BUFFER_SIZE ((320*240*2))
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#define TTB_SIZE (0x4000)
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#define TTB_BASE (0x80000000 + (32*1024*1024*2)-TTB_SIZE); /*64 megs*/
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#define TTB_BASE ((unsigned int *)(0x88000000 + (64*1024*1024)-TTB_SIZE))
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/*
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* AIPS 1
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*/
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@ -25,8 +25,6 @@
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#include "panic.h"
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#include "pcf50606.h"
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#include "ata-target.h"
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#include "mmu-imx31.h"
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#include "backlight-target.h"
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#define ATA_RST (1 << 6)
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@ -1,237 +1,36 @@
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#include <string.h>
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#include "mmu-imx31.h"
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/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2007 by Will Robertson
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*
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* All files in this archive are subject to the GNU General Public License.
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* See the file COPYING in the source tree root for full license agreement.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include "cpu.h"
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static void enable_mmu(void);
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static void set_ttb(void);
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static void set_page_tables(void);
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static void map_section(unsigned int pa, unsigned int va, int mb, int cache_flags);
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#define SECTION_ADDRESS_MASK (-1 << 20)
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#define CACHE_ALL (1 << 3 | 1 << 2 )
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#define CACHE_NONE 0
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#define BUFFERED (1 << 2)
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#define MB (1 << 20)
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#include "mmu-imx31.h"
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#include "mmu-arm.h"
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void memory_init(void) {
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set_ttb();
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ttb_init();
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set_page_tables();
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enable_mmu();
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}
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unsigned int* ttb_base = (unsigned int *) TTB_BASE;
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const int ttb_size = 4096;
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void set_ttb() {
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int i;
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int* ttbPtr;
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int domain_access;
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/* must be 16Kb (0x4000) aligned */
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ttb_base = (int*) TTB_BASE;
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for (i=0; i<ttb_size; i++,ttbPtr++)
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ttbPtr = 0;
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asm volatile("mcr p15, 0, %0, c2, c0, 0" : : "r" (ttb_base));
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/* set domain D0 to "client" permission access */
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domain_access = 3;
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asm volatile("mcr p15, 0, %0, c3, c0, 0" : : "r" (domain_access));
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}
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void set_page_tables() {
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map_section(0, 0, 0x1000, CACHE_NONE); /* map every memory region to itself */
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/*This pa *might* change*/
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/*This pa *might* change*/
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map_section(0x80000000, 0, 64, CACHE_ALL); /* map RAM to 0 and enable caching for it */
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map_section((int)FRAME1, (int)FRAME1, 1, BUFFERED); /* enable buffered writing for the framebuffer */
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map_section((int)FRAME2, (int)FRAME2, 1, BUFFERED);
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map_section((int)FRAME2, (int)FRAME2, 1, BUFFERED);
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}
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void map_section(unsigned int pa, unsigned int va, int mb, int cache_flags) {
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unsigned int* ttbPtr;
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int i;
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int section_no;
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section_no = va >> 20; /* sections are 1Mb size */
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ttbPtr = ttb_base + section_no;
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pa &= SECTION_ADDRESS_MASK; /* align to 1Mb */
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for(i=0; i<mb; i++, pa += MB) {
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*(ttbPtr + i) =
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pa |
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1 << 10 | /* superuser - r/w, user - no access */
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0 << 5 | /* domain 0th */
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1 << 4 | /* should be "1" */
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cache_flags |
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1 << 1; /* Section signature */
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}
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}
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static void enable_mmu(void) {
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int regread;
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asm volatile(
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"MRC p15, 0, %r0, c1, c0, 0\n" /* Read reg1, control register */
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: /* outputs */
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"=r"(regread)
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: /* inputs */
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: /* clobbers */
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"r0"
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);
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if ( !(regread & 0x04) || !(regread & 0x00001000) ) /* Was the ICache or DCache Enabled? */
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clean_dcache(); /* If so we need to clean the DCache before invalidating below */
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asm volatile("mov r0, #0\n"
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"mcr p15, 0, r0, c8, c7, 0\n" /* invalidate TLB */
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"mcr p15, 0, r0, c7, c7,0\n" /* invalidate both icache and dcache */
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"mrc p15, 0, r0, c1, c0, 0\n"
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"orr r0, r0, #1<<0\n" /* enable mmu bit, icache and dcache */
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"orr r0, r0, #1<<2\n" /* enable dcache */
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"orr r0, r0, #1<<12\n" /* enable icache */
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"mcr p15, 0, r0, c1, c0, 0" : : : "r0");
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asm volatile("nop \n nop \n nop \n nop");
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}
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/* Invalidate DCache for this range */
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/* Will do write back */
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void invalidate_dcache_range(const void *base, unsigned int size) {
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unsigned int addr = (((int) base) & ~31); /* Align start to cache line*/
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unsigned int end = ((addr+size) & ~31)+64; /* Align end to cache line, pad */
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asm volatile(
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"inv_start: \n"
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"mcr p15, 0, %0, c7, c14, 1 \n" /* Clean and invalidate this line */
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"add %0, %0, #32 \n"
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"cmp %0, %1 \n"
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"mcrne p15, 0, %0, c7, c14, 1 \n" /* Clean and invalidate this line */
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"addne %0, %0, #32 \n"
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"cmpne %0, %1 \n"
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"mcrne p15, 0, %0, c7, c14, 1 \n" /* Clean and invalidate this line */
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"addne %0, %0, #32 \n"
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"cmpne %0, %1 \n"
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"mcrne p15, 0, %0, c7, c14, 1 \n" /* Clean and invalidate this line */
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"addne %0, %0, #32 \n"
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"cmpne %0, %1 \n"
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"mcrne p15, 0, %0, c7, c14, 1 \n" /* Clean and invalidate this line */
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"addne %0, %0, #32 \n"
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"cmpne %0, %1 \n"
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"mcrne p15, 0, %0, c7, c14, 1 \n" /* Clean and invalidate this line */
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"addne %0, %0, #32 \n"
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"cmpne %0, %1 \n"
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"mcrne p15, 0, %0, c7, c14, 1 \n" /* Clean and invalidate this line */
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"addne %0, %0, #32 \n"
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"cmpne %0, %1 \n"
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"mcrne p15, 0, %0, c7, c14, 1 \n" /* Clean and invalidate this line */
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"addne %0, %0, #32 \n"
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"cmpne %0, %1 \n"
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"bne inv_start \n"
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"mov %0, #0\n"
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"mcr p15,0,%0,c7,c10,4\n" /* Drain write buffer */
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: : "r" (addr), "r" (end));
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}
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/* clean DCache for this range */
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/* forces DCache writeback for the specified range */
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void clean_dcache_range(const void *base, unsigned int size) {
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unsigned int addr = (int) base;
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unsigned int end = addr+size+32;
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asm volatile(
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"bic %0, %0, #31 \n"
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"clean_start: \n"
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"mcr p15, 0, %0, c7, c10, 1 \n" /* Clean this line */
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"add %0, %0, #32 \n"
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"cmp %0, %1 \n"
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"mcrlo p15, 0, %0, c7, c10, 1 \n" /* Clean this line */
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"addlo %0, %0, #32 \n"
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"cmplo %0, %1 \n"
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"mcrlo p15, 0, %0, c7, c10, 1 \n" /* Clean this line */
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"addlo %0, %0, #32 \n"
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"cmplo %0, %1 \n"
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"mcrlo p15, 0, %0, c7, c10, 1 \n" /* Clean this line */
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"addlo %0, %0, #32 \n"
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"cmplo %0, %1 \n"
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"mcrlo p15, 0, %0, c7, c10, 1 \n" /* Clean this line */
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"addlo %0, %0, #32 \n"
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"cmplo %0, %1 \n"
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"mcrlo p15, 0, %0, c7, c10, 1 \n" /* Clean this line */
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"addlo %0, %0, #32 \n"
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"cmplo %0, %1 \n"
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"mcrlo p15, 0, %0, c7, c10, 1 \n" /* Clean this line */
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"addlo %0, %0, #32 \n"
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"cmplo %0, %1 \n"
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"mcrlo p15, 0, %0, c7, c10, 1 \n" /* Clean this line */
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"addlo %0, %0, #32 \n"
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"cmplo %0, %1 \n"
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"blo clean_start \n"
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"mov %0, #0\n"
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"mcr p15,0,%0,c7,c10,4 \n" /* Drain write buffer */
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: : "r" (addr), "r" (end));
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}
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/* Dump DCache for this range */
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/* Will *NOT* do write back */
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void dump_dcache_range(const void *base, unsigned int size) {
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unsigned int addr = (int) base;
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unsigned int end = addr+size;
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asm volatile(
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"tst %0, #31 \n" /* Check to see if low five bits are set */
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"bic %0, %0, #31 \n" /* Clear them */
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"mcrne p15, 0, %0, c7, c14, 1 \n" /* Clean and invalidate this line, if those bits were set */
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"add %0, %0, #32 \n" /* Move to the next cache line */
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"tst %1, #31 \n" /* Check last line for bits set */
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"bic %1, %1, #31 \n" /* Clear those bits */
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"mcrne p15, 0, %1, c7, c14, 1 \n" /* Clean and invalidate this line, if not cache aligned */
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"dump_start: \n"
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"mcr p15, 0, %0, c7, c6, 1 \n" /* Invalidate this line */
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"add %0, %0, #32 \n" /* Next cache line */
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"cmp %0, %1 \n"
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"bne dump_start \n"
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"dump_end: \n"
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"mcr p15,0,%0,c7,c10,4 \n" /* Drain write buffer */
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: : "r" (addr), "r" (end));
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}
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/* Cleans entire DCache */
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void clean_dcache(void)
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{
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unsigned int index, addr;
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for(index = 0; index <= 63; index++) {
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addr = (0 << 5) | (index << 26);
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asm volatile(
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"mcr p15, 0, %0, c7, c10, 2 \n" /* Clean this entry by index */
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: : "r" (addr));
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addr = (1 << 5) | (index << 26);
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asm volatile(
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"mcr p15, 0, %0, c7, c10, 2 \n" /* Clean this entry by index */
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: : "r" (addr));
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addr = (2 << 5) | (index << 26);
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asm volatile(
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"mcr p15, 0, %0, c7, c10, 2 \n" /* Clean this entry by index */
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: : "r" (addr));
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addr = (3 << 5) | (index << 26);
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asm volatile(
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"mcr p15, 0, %0, c7, c10, 2 \n" /* Clean this entry by index */
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: : "r" (addr));
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addr = (4 << 5) | (index << 26);
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asm volatile(
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"mcr p15, 0, %0, c7, c10, 2 \n" /* Clean this entry by index */
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: : "r" (addr));
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addr = (5 << 5) | (index << 26);
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asm volatile(
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"mcr p15, 0, %0, c7, c10, 2 \n" /* Clean this entry by index */
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: : "r" (addr));
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addr = (6 << 5) | (index << 26);
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asm volatile(
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"mcr p15, 0, %0, c7, c10, 2 \n" /* Clean this entry by index */
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: : "r" (addr));
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addr = (7 << 5) | (index << 26);
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asm volatile(
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"mcr p15, 0, %0, c7, c10, 2 \n" /* Clean this entry by index */
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: : "r" (addr));
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}
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}
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@ -17,19 +17,5 @@
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*
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****************************************************************************/
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/* Invalidate DCache for this range */
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/* Will do write back */
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void invalidate_dcache_range(const void *base, unsigned int size);
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/* clean DCache for this range */
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/* forces DCache writeback for the specified range */
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void clean_dcache_range(const void *base, unsigned int size);
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/* Dump DCache for this range */
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/* Will *NOT* do write back */
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void dump_dcache_range(const void *base, unsigned int size);
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/* Cleans entire DCache */
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void clean_dcache(void);
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void memory_init(void);
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void set_page_tables(void);
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