Fix a couple mistakes. Forgot to add a few definitions.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@17535 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Michael Sevakis
parent
cda664b701
commit
3c102ffd4d
|
|
@ -393,10 +393,10 @@ enum mc13783_regs_enum
|
|||
#define MC13783_VBKUP2EN (0x1 << 12)
|
||||
#define MC13783_VBKUP2AUTO (0x1 << 13)
|
||||
#define MC13783_VBKUP2 (0x3 << 14)
|
||||
#define MC13783_VBKUP2_1_0V (0x0 << 10)
|
||||
#define MC13783_VBKUP2_1_2V (0x1 << 10)
|
||||
#define MC13783_VBKUP2_1_5V (0x2 << 10)
|
||||
#define MC13783_VBKUP2_1_8V (0x3 << 10)
|
||||
#define MC13783_VBKUP2_1_0V (0x0 << 14)
|
||||
#define MC13783_VBKUP2_1_2V (0x1 << 14)
|
||||
#define MC13783_VBKUP2_1_5V (0x2 << 14)
|
||||
#define MC13783_VBKUP2_1_8V (0x3 << 14)
|
||||
#define MC13783_BPDET (0x3 << 16)
|
||||
/* 00: UVDET 2.6, LOBATL UVDET+0.2, LOBATH UVDET+0.4 BPON 3.2 */
|
||||
#define MC13783_BPDET_2_4 (0x0 << 16)
|
||||
|
|
@ -547,54 +547,172 @@ enum mc13783_regs_enum
|
|||
|
||||
/* SWITCHERS4 (28) */
|
||||
#define MC13783_SW1AMODE (0x3 << 0)
|
||||
#define MC13783_SW1AMODE_OFF (0x0 << 0)
|
||||
#define MC13783_SW1AMODE_PWM (0x1 << 0)
|
||||
#define MC13783_SW1AMODE_PWM_SKIP (0x2 << 0)
|
||||
#define MC13783_SW1AMODE_PFM (0x3 << 0)
|
||||
#define MC13783_SW1ASTBYMODE (0x3 << 2)
|
||||
#define MC13783_SW1ASTBYMODE_OFF (0x0 << 2)
|
||||
#define MC13783_SW1ASTBYMODE_PWM (0x1 << 2)
|
||||
#define MC13783_SW1ASTBYMODE_PWM_SKIP (0x2 << 2)
|
||||
#define MC13783_SW1ASTBYMODE_PFM (0x3 << 2)
|
||||
#define MC13783_SW1ADVSSPEED (0x3 << 6)
|
||||
/* 25mV every ... */
|
||||
#define MC13783_SW1ADVSSPEED_4US_NO_PWR_RDY (0x0 << 6)
|
||||
#define MC13783_SW1ADVSSPEED_4US (0x1 << 6)
|
||||
#define MC13783_SW1ADVSSPEED_8US (0x2 << 6)
|
||||
#define MC13783_SW1ADVSSPEED_16US (0x3 << 6)
|
||||
#define MC13783_SW1APANIC (0x1 << 8)
|
||||
#define MC13783_SW1ASFST (0x1 << 9)
|
||||
#define MC13783_SW1BMODE (0x3 << 10)
|
||||
#define MC13783_SW1BMODE_OFF (0x0 << 10)
|
||||
#define MC13783_SW1BMODE_PWM (0x1 << 10)
|
||||
#define MC13783_SW1BMODE_PWM_SKIP (0x2 << 10)
|
||||
#define MC13783_SW1BMODE_PFM (0x3 << 10)
|
||||
#define MC13783_SW1BSTBYMODE (0x3 << 12)
|
||||
#define MC13783_SW1BSTBYMODE_OFF (0x0 << 12)
|
||||
#define MC13783_SW1BSTBYMODE_PWM (0x1 << 12)
|
||||
#define MC13783_SW1BSTBYMODE_PWM_SKIP (0x2 << 12)
|
||||
#define MC13783_SW1BSTBYMODE_PFM (0x3 << 12)
|
||||
#define MC13783_SW1BDVSSPEED (0x3 << 14)
|
||||
/* 25mV every ... */
|
||||
#define MC13783_SW1BDVSSPEED_4US_NO_PWR_RDY (0x0 << 14)
|
||||
#define MC13783_SW1BDVSSPEED_4US (0x1 << 14)
|
||||
#define MC13783_SW1BDVSSPEED_8US (0x2 << 14)
|
||||
#define MC13783_SW1BDVSSPEED_16US (0x3 << 14)
|
||||
#define MC13783_SW1BPANIC (0x1 << 16)
|
||||
#define MC13783_SW1BSFST (0x1 << 17)
|
||||
#define MC13783_PLLEN (0x1 << 18)
|
||||
#define MC13783_PLLX (0x7 << 19)
|
||||
#define MC13783_PLLX_28 (0x0 << 19)
|
||||
#define MC13783_PLLX_29 (0x1 << 19)
|
||||
#define MC13783_PLLX_30 (0x2 << 19)
|
||||
#define MC13783_PLLX_31 (0x3 << 19)
|
||||
#define MC13783_PLLX_32 (0x4 << 19)
|
||||
#define MC13783_PLLX_33 (0x5 << 19)
|
||||
#define MC13783_PLLX_34 (0x6 << 19)
|
||||
#define MC13783_PLLX_35 (0x7 << 19)
|
||||
|
||||
/* SWITCHERS5 (29) */
|
||||
#define MC13783_SW2AMODE (0x3 << 0)
|
||||
#define MC13783_SW2AMODE_OFF (0x0 << 0)
|
||||
#define MC13783_SW2AMODE_PWM (0x1 << 0)
|
||||
#define MC13783_SW2AMODE_PWM_SKIP (0x2 << 0)
|
||||
#define MC13783_SW2AMODE_PFM (0x3 << 0)
|
||||
#define MC13783_SW2ASTBYMODE (0x3 << 2)
|
||||
#define MC13783_SW2ASTBYMODE_OFF (0x0 << 2)
|
||||
#define MC13783_SW2ASTBYMODE_PWM (0x1 << 2)
|
||||
#define MC13783_SW2ASTBYMODE_PWM_SKIP (0x2 << 2)
|
||||
#define MC13783_SW2ASTBYMODE_PFM (0x3 << 2)
|
||||
#define MC13783_SW2ADVSSPEED (0x3 << 6)
|
||||
#define MC13783_SW2ADVSSPEED_4US_NO_PWR_RDY (0x0 << 6)
|
||||
#define MC13783_SW2ADVSSPEED_4US (0x1 << 6)
|
||||
#define MC13783_SW2ADVSSPEED_8US (0x2 << 6)
|
||||
#define MC13783_SW2ADVSSPEED_16US (0x3 << 6)
|
||||
#define MC13783_SW2APANIC (0x1 << 8)
|
||||
#define MC13783_SW2ASFST (0x1 << 9)
|
||||
#define MC13783_SW2BMODE (0x3 << 10)
|
||||
#define MC13783_SW2BMODE_OFF (0x0 << 10)
|
||||
#define MC13783_SW2BMODE_PWM (0x1 << 10)
|
||||
#define MC13783_SW2BMODE_PWM_SKIP (0x2 << 10)
|
||||
#define MC13783_SW2BMODE_PFM (0x3 << 10)
|
||||
#define MC13783_SW2BSTBYMODE (0x3 << 12)
|
||||
#define MC13783_SW2BSTBYMODE_OFF (0x0 << 12)
|
||||
#define MC13783_SW2BSTBYMODE_PWM (0x1 << 12)
|
||||
#define MC13783_SW2BSTBYMODE_PWM_SKIP (0x2 << 12)
|
||||
#define MC13783_SW2BSTBYMODE_PFM (0x3 << 12)
|
||||
#define MC13783_SW2BDVSSPEED (0x3 << 14)
|
||||
#define MC13783_SW2BDVSSPEED_4US_NO_PWR_RDY (0x0 << 14)
|
||||
#define MC13783_SW2BDVSSPEED_4US (0x1 << 14)
|
||||
#define MC13783_SW2BDVSSPEED_8US (0x2 << 14)
|
||||
#define MC13783_SW2BDVSSPEED_16US (0x3 << 14)
|
||||
#define MC13783_SW2BPANIC (0x1 << 16)
|
||||
#define MC13783_SW2BSFST (0x1 << 17)
|
||||
#define MC13783_SW3 (0x3 << 18)
|
||||
#define MC13783_SW3_PRI_VOL_BOTH_OP (0x0 << 18)
|
||||
#define MC13783_SW3_SEC_VOL_BOTH_OP (0x2 << 18)
|
||||
#define MC13783_SW3_PRI_ONLY (0x3 << 18)
|
||||
#define MC13783_SW3_5_0V (0x0 << 18)
|
||||
/* 0x1...0x2 same as 0x0 */
|
||||
#define MC13783_SW3_5_5V (0x3 << 18)
|
||||
#define MC13783_SW3EN (0x1 << 20)
|
||||
#define MC13783_SW3STBY (0x1 << 21)
|
||||
#define MC13783_SW3MODE (0x1 << 22)
|
||||
|
||||
/* REGULATOR_SETTING0 (30) */
|
||||
#define MC13783_VIOLO (0x3 << 2)
|
||||
#define MC13783_VIOLO_1_20V (0x0 << 2)
|
||||
#define MC13783_VIOLO_1_30V (0x1 << 2)
|
||||
#define MC13783_VIOLO_1_50V (0x2 << 2)
|
||||
#define MC13783_VIOLO_1_80V (0x3 << 2)
|
||||
#define MC13783_VDIG (0x3 << 4)
|
||||
#define MC13783_VDIG_1_20V (0x0 << 4)
|
||||
#define MC13783_VDIG_1_30V (0x1 << 4)
|
||||
#define MC13783_VDIG_1_50V (0x2 << 4)
|
||||
#define MC13783_VDIG_1_80V (0x3 << 4)
|
||||
#define MC13783_VGEN (0x7 << 6)
|
||||
#define MC13783_VGEN_1_20V (0x0 << 6)
|
||||
#define MC13783_VGEN_1_30V (0x1 << 6)
|
||||
#define MC13783_VGEN_1_50V (0x2 << 6)
|
||||
#define MC13783_VGEN_1_80V (0x3 << 6)
|
||||
#define MC13783_VGEN_1_10V (0x4 << 6)
|
||||
#define MC13783_VGEN_2_00V (0x5 << 6)
|
||||
#define MC13783_VGEN_2_775V (0x6 << 6)
|
||||
#define MC13783_VGEN_2_40V (0x7 << 6)
|
||||
#define MC13783_VRFDIG (0x3 << 9)
|
||||
#define MC13783_VREFDIG_1_20V (0x0 << 9)
|
||||
#define MC13783_VREFDIG_1_30V (0x1 << 9)
|
||||
#define MC13783_VREFDIG_1_80V (0x2 << 9)
|
||||
#define MC13783_VREFDIG_1_875V (0x3 << 9)
|
||||
#define MC13783_VRFREF (0x3 << 11)
|
||||
#define MC13783_VRFREF_2_475V (0x0 << 11)
|
||||
#define MC13783_VRFREF_2_600V (0x1 << 11)
|
||||
#define MC13783_VRFREF_2_700V (0x2 << 11)
|
||||
#define MC13783_VRFREF_2_775V (0x3 << 11)
|
||||
#define MC13783_VRFCP (0x1 << 13)
|
||||
#define MC13783_VSIM (0x1 << 14)
|
||||
#define MC13783_VESIM (0x1 << 15)
|
||||
#define MC13783_VCAM (0x7 << 16)
|
||||
#define MC13783_VCAM_1_50V (0x0 << 16)
|
||||
#define MC13783_VCAM_1_80V (0x1 << 16)
|
||||
#define MC13783_VCAM_2_50V (0x2 << 16)
|
||||
#define MC13783_VCAM_2_55V (0x3 << 16)
|
||||
#define MC13783_VCAM_2_60V (0x4 << 16)
|
||||
#define MC13783_VCAM_2_75V (0x5 << 16)
|
||||
#define MC13783_VCAM_2_80V (0x6 << 16)
|
||||
#define MC13783_VCAM_3_00V (0x7 << 16)
|
||||
|
||||
/* REGULATOR_SETTING1 (31) */
|
||||
#define MC13783_VVIB (0x3 << 0)
|
||||
#define MC13783_VVIB_1_30V (0x0 << 0)
|
||||
#define MC13783_VVIB_1_80V (0x1 << 0)
|
||||
#define MC13783_VVIB_2_00V (0x2 << 0)
|
||||
#define MC13783_VVIB_3_00V (0x3 << 0)
|
||||
#define MC13783_VRF1 (0x3 << 2)
|
||||
#define MC13783_VRF1_1_500V (0x0 << 2)
|
||||
#define MC13783_VRF1_1_875V (0x1 << 2)
|
||||
#define MC13783_VRF1_2_700V (0x2 << 2)
|
||||
#define MC13783_VRF1_2_775V (0x3 << 2)
|
||||
#define MC13783_VRF2 (0x3 << 4)
|
||||
#define MC13783_VRF2_1_500V (0x0 << 4)
|
||||
#define MC13783_VRF2_1_875V (0x1 << 4)
|
||||
#define MC13783_VRF2_2_700V (0x2 << 4)
|
||||
#define MC13783_VRF2_2_775V (0x3 << 4)
|
||||
#define MC13783_VMMC1 (0x7 << 6)
|
||||
#define MC13783_VMMC1_1_60V (0x0 << 6)
|
||||
#define MC13783_VMMC1_1_80V (0x1 << 6)
|
||||
#define MC13783_VMMC1_2_00V (0x2 << 6)
|
||||
#define MC13783_VMMC1_2_60V (0x3 << 6)
|
||||
#define MC13783_VMMC1_2_70V (0x4 << 6)
|
||||
#define MC13783_VMMC1_2_80V (0x5 << 6)
|
||||
#define MC13783_VMMC1_2_90V (0x6 << 6)
|
||||
#define MC13783_VMMC1_3_00V (0x7 << 6)
|
||||
#define MC13783_VMMC2 (0x7 << 9)
|
||||
#define MC13783_VMMC2_1_60V (0x0 << 9)
|
||||
#define MC13783_VMMC2_1_80V (0x1 << 9)
|
||||
#define MC13783_VMMC2_2_00V (0x2 << 9)
|
||||
#define MC13783_VMMC2_2_60V (0x3 << 9)
|
||||
#define MC13783_VMMC2_2_70V (0x4 << 9)
|
||||
#define MC13783_VMMC2_2_80V (0x5 << 9)
|
||||
#define MC13783_VMMC2_2_90V (0x6 << 9)
|
||||
#define MC13783_VMMC2_3_00V (0x7 << 9)
|
||||
|
||||
/* REGULATOR_MODE0 (32) */
|
||||
#define MC13783_VAUDIOEN (0x1 << 0)
|
||||
|
|
@ -689,13 +807,29 @@ enum mc13783_regs_enum
|
|||
/* AUDIO_RX1 (37) */
|
||||
#define MC13783_PGARXEN (0x1 << 0)
|
||||
#define MC13783_PGARX (0xf << 1)
|
||||
/* <=0010=-33dB...1101=0dB...1111=+6dB in 3dB steps */
|
||||
#define MC13783_PGARXw(x) (((x) << 1) & MC13783_PGARX)
|
||||
#define MC13783_PGARXr(x) (((x) & MC13783_PGARX) >> 1)
|
||||
#define MC13783_PGASTEN (0x1 << 5)
|
||||
#define MC13783_PGAST (0xf << 6)
|
||||
/* <=0010=-33dB...1101=0dB...1111=+6dB in 3dB steps */
|
||||
#define MC13783_PGASTw(x) (((x) << 6) & MC13783_PGAST)
|
||||
#define MC13783_PGASTr(x) (((x) & MC13783_PGAST) >> 6)
|
||||
#define MC13783_ARXINEN (0x1 << 10)
|
||||
#define MC13783_ARXIN (0x1 << 11)
|
||||
#define MC13783_PGARXIN (0xf << 12)
|
||||
/* <=0010=-33dB...1101=0dB...1111=+6dB in 3dB steps */
|
||||
#define MC13783_PGARXINw(x) (((x) << 12) & MC13783_PGARXIN)
|
||||
#define MC13783_PGARXINr(x) (((x) & MC13783_PGARXIN) >> 12)
|
||||
#define MC13783_MONO (0x3 << 16)
|
||||
#define MC13783_MONO_LR_INDEPENDENT (0x0 << 16)
|
||||
#define MC13783_MONO_ST_OPPOSITE (0x1 << 16)
|
||||
#define MC13783_MONO_ST_TO_MONO (0x2 << 16)
|
||||
#define MC13783_MONO_MONO_OPPOSITE (0x3 << 16)
|
||||
#define MC13783_BAL (0x7 << 18)
|
||||
/* 000=-21dB...3dB steps...111=0dB: left or right */
|
||||
#define MC13783_BALw(x) (((x) << 18) & MC13783_BAL)
|
||||
#define MC13783_BALr(x) (((x) & MC13783_BAL) >> 18)
|
||||
#define MC13783_BALLR (0x1 << 21)
|
||||
|
||||
/* AUDIO_TX (38) */
|
||||
|
|
@ -713,19 +847,55 @@ enum mc13783_regs_enum
|
|||
#define MC13783_ATXOUTEN (0x1 << 12)
|
||||
#define MC13783_RXINREC (0x1 << 13)
|
||||
#define MC13783_PGATXR (0x1f << 14)
|
||||
/* 00000=-8dB...01000=0dB...11111=+23dB */
|
||||
#define MC13783_PGATXRw(x) (((x) << 14) & MC13783_PGATXR)
|
||||
#define MC13783_PGATXRr(x) (((x) & MC13783_PGATXR) >> 14)
|
||||
#define MC13783_PGATXL (0x1f << 19)
|
||||
/* 00000=-8dB...01000=0dB...11111=+23dB */
|
||||
#define MC13783_PGATXLw(x) (((x) << 19) & MC13783_PGATXL)
|
||||
#define MC13783_PGATXLr(x) (((x) & MC13783_PGATXL) >> 19)
|
||||
|
||||
/* SSI_NETWORK (39) */
|
||||
#define MC13783_CDCTXRXSLOT (0x3 << 2)
|
||||
#define MC13783_CDCTXRXSLOT_TS0 (0x0 << 2)
|
||||
#define MC13783_CDCTXRXSLOT_TS1 (0x1 << 2)
|
||||
#define MC13783_CDCTXRXSLOT_TS2 (0x2 << 2)
|
||||
#define MC13783_CDCTXRXSLOT_TS3 (0x3 << 2)
|
||||
#define MC13783_CDCTXSECSLOT (0x3 << 4)
|
||||
#define MC13783_CDCTXSECSLOT_TS0 (0x0 << 4)
|
||||
#define MC13783_CDCTXSECSLOT_TS1 (0x1 << 4)
|
||||
#define MC13783_CDCTXSECSLOT_TS2 (0x2 << 4)
|
||||
#define MC13783_CDCTXSECSLOT_TS3 (0x3 << 4)
|
||||
#define MC13783_CDCRXSECSLOT (0x3 << 6)
|
||||
#define MC13783_CDCRXSECSLOT_TS0 (0x0 << 6)
|
||||
#define MC13783_CDCRXSECSLOT_TS1 (0x1 << 6)
|
||||
#define MC13783_CDCRXSECSLOT_TS2 (0x2 << 6)
|
||||
#define MC13783_CDCRXSECSLOT_TS3 (0x3 << 6)
|
||||
#define MC13783_CDCRXSECGAIN (0x3 << 8)
|
||||
/* -inf, -0dB, -6dB, -12dB */
|
||||
#define MC13783_CDCRXSECGAINw(x) (((x) << 8) & MC13783_CDCRXSECGAIN)
|
||||
#define MC13783_CDCRXSECGAINr(x) (((x) & MC13783_CDCRXSECGAIN) >> 8)
|
||||
#define MC13783_CDCSUMGAIN (0x1 << 10)
|
||||
#define MC13783_CDCFSDLY (0x1 << 11)
|
||||
#define MC13783_STDCSLOTS (0x3 << 12)
|
||||
#define MC13783_STDCSLOTS_8 (0x0 << 12)
|
||||
#define MC13783_STDCSLOTS_LR6 (0x1 << 12)
|
||||
#define MC13783_STDCSLOTS_LR2 (0x2 << 12)
|
||||
#define MC13783_STDCSLOTS_LR (0x3 << 12)
|
||||
#define MC13783_STDCRXSLOT (0x3 << 14)
|
||||
#define MC13783_STDCRXSLOT_TS0_TS1 (0x0 << 14)
|
||||
#define MC13783_STDCRXSLOT_TS2_TS3 (0x1 << 14)
|
||||
#define MC13783_STDCRXSLOT_TS4_TS5 (0x2 << 14)
|
||||
#define MC13783_STDCRXSLOT_TS6_TS7 (0x3 << 14)
|
||||
#define MC13783_STDCRXSECSLOT (0x3 << 16)
|
||||
#define MC13783_STDCRXSECSLOT_TS0_TS1 (0x0 << 16)
|
||||
#define MC13783_STDCRXSECSLOT_TS2_TS3 (0x1 << 16)
|
||||
#define MC13783_STDCRXSECSLOT_TS4_TS5 (0x2 << 16)
|
||||
#define MC13783_STDCRXSECSLOT_TS6_TS7 (0x3 << 16)
|
||||
#define MC13783_STDCRXSECGAIN (0x3 << 18)
|
||||
/* -inf, -0dB, -6dB, -12dB */
|
||||
#define MC13783_STDCRXSECGAINw(x) (((x) << 8) & MC13783_STDCRXSECGAIN)
|
||||
#define MC13783_STDCRXSECGAINr(x) (((x) & MC13783_STDCRXSECGAIN) >> 8)
|
||||
#define MC13783_STDSUMGAIN (0x1 << 20)
|
||||
|
||||
/* AUDIO_CODEC (40) */
|
||||
|
|
@ -735,6 +905,8 @@ enum mc13783_regs_enum
|
|||
#define MC13783_CDCBCLINV (0x1 << 3)
|
||||
#define MC13783_CDCFSINV (0x1 << 4)
|
||||
#define MC13783_CDCFS (0x3 << 5)
|
||||
#define MC13783_CDCFS_NET (0x1 << 5)
|
||||
#define MC13783_CDCFS_I2S (0x2 << 5)
|
||||
#define MC13783_CDCCLK (0x7 << 7)
|
||||
#define MC13783_CDCFS8K16K (0x1 << 10)
|
||||
#define MC13783_CDCEN (0x1 << 11)
|
||||
|
|
@ -755,13 +927,39 @@ enum mc13783_regs_enum
|
|||
#define MC13783_STDCBCLINV (0x1 << 3)
|
||||
#define MC13783_STDCFSINV (0x1 << 4)
|
||||
#define MC13783_STDCFS (0x3 << 5)
|
||||
#define MC13783_STDCFS_NORMAL (0x0 << 5)
|
||||
#define MC13783_STDCFS_NET (0x1 << 5)
|
||||
#define MC13783_STDCFS_I2S (0x2 << 5)
|
||||
#define MC13783_STDCCLK (0x7 << 7)
|
||||
/* Master */
|
||||
#define MC13783_STDCCLK_13_0MHZ (0x0 << 7)
|
||||
#define MC13783_STDCCLK_15_36MHZ (0x1 << 7)
|
||||
#define MC13783_STDCCLK_16_8MHZ (0x2 << 7)
|
||||
#define MC13783_STDCCLK_26_0MHZ (0x4 << 7)
|
||||
#define MC13783_STDCCLK_12_0MHZ (0x5 << 7)
|
||||
#define MC13783_STDCCLK_3_6864MHZ (0x6 << 7)
|
||||
#define MC13783_STDCCLK_33_6MHZ (0x7 << 7)
|
||||
/* Slave */
|
||||
#define MC13783_STDCCLK_CLIMCL (0x5 << 7)
|
||||
#define MC13783_STDCCLK_FS (0x6 << 7)
|
||||
#define MC13783_STDCCLK_BCL (0x7 << 7)
|
||||
#define MC13783_STDCFSDLYB (0x1 << 10)
|
||||
#define MC13783_STDCEN (0x1 << 11)
|
||||
#define MC13783_STDCCLKEN (0x1 << 12)
|
||||
#define MC13783_STDCRESET (0x1 << 15)
|
||||
#define MC13783_SPDIF (0x1 << 16)
|
||||
#define MC13783_SR (0xf << 17)
|
||||
#define MC13783_SR_8000 (0x0 << 17)
|
||||
#define MC13783_SR_11025 (0x1 << 17)
|
||||
#define MC13783_SR_12000 (0x2 << 17)
|
||||
#define MC13783_SR_16000 (0x3 << 17)
|
||||
#define MC13783_SR_22050 (0x4 << 17)
|
||||
#define MC13783_SR_24000 (0x5 << 17)
|
||||
#define MC13783_SR_32000 (0x6 << 17)
|
||||
#define MC13783_SR_44100 (0x7 << 17)
|
||||
#define MC13783_SR_48000 (0x8 << 17)
|
||||
#define MC13783_SR_64000 (0x9 << 17)
|
||||
#define MC13783_SR_96000 (0xa << 17)
|
||||
|
||||
/* ADC0 (43) */
|
||||
#define MC13783_LICELLCON (0x1 << 0)
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user