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Enable frequency scaling on AMSv2 devices. 

Voltage scaling is not yet enabled, but will follow once we are sure
these changes are stable.  Preliminary testing suggests a large
increase in battery life, which will be further improved by voltage
scaling.  Patch by Mihail Zenkov with help from myself and others on
the forums.

Change-Id: I171d20bbee19a48c13cd14efb0d023883cc8c687
This commit is contained in:
Mihail Zenkov 2016-01-19 00:21:10 +01:00 committed by Michael Giacomelli
parent 7432af0958
commit 3f54101858
7 changed files with 35 additions and 54 deletions
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4
firmware/export/config/sansaclipplus.h
View File

@ -176,7 +176,7 @@
#define CURRENT_MAX_CHG 150
/* Define this to the CPU frequency */
#define CPU_FREQ 240000000
#define CPU_FREQ 192000000
/* Type of LCD */
#define CONFIG_LCD LCD_SSD1303
@ -194,7 +194,7 @@
#define CONFIG_LED LED_VIRTUAL
/* Define this if you have adjustable CPU frequency */
//#define HAVE_ADJUSTABLE_CPU_FREQ
#define HAVE_ADJUSTABLE_CPU_FREQ
#define BOOTFILE_EXT "sansa"
#define BOOTFILE "rockbox." BOOTFILE_EXT

4
firmware/export/config/sansaclipv2.h
View File

@ -172,7 +172,7 @@
#define CURRENT_MAX_CHG 150
/* Define this to the CPU frequency */
#define CPU_FREQ 240000000
#define CPU_FREQ 192000000
/* Type of LCD */
#define CONFIG_LCD LCD_SSD1303
@ -190,7 +190,7 @@
#define CONFIG_LED LED_VIRTUAL
/* Define this if you have adjustable CPU frequency */
//#define HAVE_ADJUSTABLE_CPU_FREQ
#define HAVE_ADJUSTABLE_CPU_FREQ
#define BOOTFILE_EXT "sansa"
#define BOOTFILE "rockbox." BOOTFILE_EXT

4
firmware/export/config/sansaclipzip.h
View File

@ -175,7 +175,7 @@
#define CURRENT_MAX_CHG 150
/* Define this to the CPU frequency */
#define CPU_FREQ 240000000
#define CPU_FREQ 192000000
/* Type of LCD */
#define CONFIG_LCD LCD_CLIPZIP
@ -193,7 +193,7 @@
#define CONFIG_LED LED_VIRTUAL
/* Define this if you have adjustable CPU frequency */
//#define HAVE_ADJUSTABLE_CPU_FREQ
#define HAVE_ADJUSTABLE_CPU_FREQ
#define BOOTFILE_EXT "sansa"
#define BOOTFILE "rockbox." BOOTFILE_EXT

4
firmware/export/config/sansafuzev2.h
View File

@ -182,7 +182,7 @@
#define CURRENT_MAX_CHG 200
/* Define this to the CPU frequency */
#define CPU_FREQ 240000000
#define CPU_FREQ 192000000
/* Type of LCD */
#define CONFIG_LCD LCD_FUZE
@ -208,7 +208,7 @@
#define HAVE_BOOTLOADER_USB_MODE
/* Define this if you have adjustable CPU frequency */
//#define HAVE_ADJUSTABLE_CPU_FREQ
#define HAVE_ADJUSTABLE_CPU_FREQ
#define BOOTFILE_EXT "sansa"
#define BOOTFILE "rockbox." BOOTFILE_EXT

4
firmware/rolo.c
View File

@ -267,6 +267,10 @@ int rolo_load(const char* filename)
lcd_remote_update();
#endif
adc_close();
#if CONFIG_CPU == AS3525v2
/* Set CVDD1 power supply to default*/
ascodec_write_pmu(0x17, 1, 0);
#endif
#if CONFIG_CPU != IMX31L /* We're not finished yet */
#ifdef CPU_ARM

34
firmware/target/arm/as3525/clock-target.h
View File

@ -70,11 +70,8 @@
* - bit 12 = unknown (always set to 1)
* Fpll = Fin * F / (R * OD), where Fin = 12 MHz
*/
#define AS3525_PLLA_FREQ 240000000
#define AS3525_PLLA_SETTING 0x113B
#define AS3525_PLLB_FREQ 192000000 /* allows 44.1kHz with 0.04% error*/
#define AS3525_PLLB_SETTING 0x155F
#define AS3525_PLLA_FREQ 192000000 /* allows 44.1kHz with 0.04% error*/
#define AS3525_PLLA_SETTING 0x155F
#define AS3525_FCLK_PREDIV 0
#define AS3525_FCLK_FREQ AS3525_PLLA_FREQ
@ -86,13 +83,9 @@
* Also note that CGU_PERI is based on fclk, not PLLA
*/
#ifdef SANSA_FUZEV2
/* display is unbearably slow at 24MHz
* 34285715 HZ works ok but 40MHz works even better*/
#define AS3525_DRAM_FREQ 40000000 /* Initial DRAM frequency */
#else
#define AS3525_DRAM_FREQ 24000000 /* Initial DRAM frequency */
#endif /* SANSA_FUZEV2 */
#define AS3525_DRAM_FREQ 96000000 /* Initial DRAM frequency */
#else
/* AS3525v1 */
@ -131,8 +124,8 @@
/* Tell the software what frequencies we're running */
#define CPUFREQ_MAX AS3525_FCLK_FREQ
#define CPUFREQ_DEFAULT AS3525_PCLK_FREQ
#define CPUFREQ_NORMAL AS3525_PCLK_FREQ
#define CPUFREQ_DEFAULT 38400000
#define CPUFREQ_NORMAL CPUFREQ_DEFAULT
/* FCLK */
#define AS3525_FCLK_SEL AS3525_CLK_PLLA
@ -145,21 +138,8 @@
#endif /* CONFIG_CPU == AS3525v2 */
/* MCLK */
#if CONFIG_CPU == AS3525v2
/* on AMSv2 we can enable PLLB for MCLK to increase PCM sample rate accuracy
with no significant impact on battery life */
#define AS3525_MCLK_SEL AS3525_CLK_PLLB
#else
#define AS3525_MCLK_SEL AS3525_CLK_PLLA
#endif /* CONFIG_CPU == AS3525v2 */
#if (AS3525_MCLK_SEL==AS3525_CLK_PLLA)
#define AS3525_MCLK_FREQ AS3525_PLLA_FREQ
#elif (AS3525_MCLK_SEL==AS3525_CLK_PLLB)
#define AS3525_MCLK_FREQ AS3525_PLLB_FREQ
#else
#error Choose either PLLA or PLLB for MCLK!
#endif
/* PCLK */

35
firmware/target/arm/as3525/system-as3525.c
View File

@ -306,8 +306,6 @@ void system_init(void)
CGU_PERI |= CGU_ROM_ENABLE; /* needed for rebooting */
set_cpu_frequency(CPUFREQ_DEFAULT);
#if 0 /* the GPIO clock is already enabled by the dualboot function */
CGU_PERI |= CGU_GPIO_CLOCK_ENABLE;
#endif
@ -335,10 +333,8 @@ void system_init(void)
ascodec_write_pmu(0x18, 1, 0x35);
/* AVDD17: set AVDD17 power supply to 2.5V */
ascodec_write_pmu(0x18, 7, 0x31);
#ifdef SANSA_CLIPZIP
/* CVDD2: set CVDD2 power supply to 2.8V */
ascodec_write_pmu(0x17, 2, 0xF4);
#endif
/* CVDD2: set CVDD2 power supply (digital for DAC/SD/etc) to 2.65V */
ascodec_write_pmu(0x17, 2, 0x80 | 113);
#else /* HAVE_AS3543 */
ascodec_write(AS3514_CVDD_DCDC3, AS314_CP_DCDC3_SETTING);
#endif /* HAVE_AS3543 */
@ -460,23 +456,18 @@ void set_cpu_frequency(long frequency)
}
}
#else /* as3525v2 */
/* FIXME : disabled for now, seems to cause buggy memory accesses
* Disabling MMU or putting the function in uncached memory seems to help? */
void set_cpu_frequency(long frequency)
{
int oldstatus = disable_irq_save();
/* We only have 2 settings */
cpu_frequency = (frequency == CPUFREQ_MAX) ? frequency : CPUFREQ_NORMAL;
if(frequency == CPUFREQ_MAX)
{
/* Change PCLK while FCLK is low, so it doesn't go too high */
CGU_PERI = (CGU_PERI & ~(0xF << 2)) | (AS3525_PCLK_DIV0 << 2);
/* Set CVDD1 power supply */
/*ascodec_write_pmu(0x17, 1, 0x80 | 47);*/
CGU_PROC = ((AS3525_FCLK_POSTDIV << 4) |
(AS3525_FCLK_PREDIV << 2) |
AS3525_FCLK_SEL);
cpu_frequency = CPUFREQ_MAX;
}
else
{
@ -484,11 +475,17 @@ void set_cpu_frequency(long frequency)
(AS3525_FCLK_PREDIV << 2) |
AS3525_FCLK_SEL);
/* Change PCLK after FCLK is low, so it doesn't go too high */
CGU_PERI = (CGU_PERI & ~(0xF << 2)) | (AS3525_PCLK_DIV0_UNBOOSTED << 2);
}
cpu_frequency = CPUFREQ_NORMAL;
restore_irq(oldstatus);
/* Set CVDD1 power supply */
/*
#ifdef SANSA_CLIPZIP
ascodec_write_pmu(0x17, 1, 0x80 | 19);
#else
ascodec_write_pmu(0x17, 1, 0x80 | 22);
#endif
*/
}
}
#endif