Ingenic Jz4740:
* Clean up header file a bit * Add information about the IPU * Add original license * Add Ingenic Media Extension Instruction Set header file git-svn-id: svn://svn.rockbox.org/rockbox/trunk@19621 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Maurus Cuelenaere
parent
e25505daa4
commit
54919ae917
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@ -1,3 +1,39 @@
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/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2008 by Maurus Cuelenaere
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* Copyright (C) 2006-2007 by Ingenic Semiconductor Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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/*
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* linux/include/asm-mips/mach-jz4740/jz4740.h
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*
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* JZ4740 common definition.
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*
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* Copyright (C) 2006 - 2007 Ingenic Semiconductor Inc.
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*
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* Author: <lhhuang@ingenic.cn>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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/*
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* Include file for Ingenic Semiconductor's JZ4740 CPU.
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*/
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@ -6,50 +42,50 @@
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#ifndef __ASSEMBLY__
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#define REG8(addr) (*(volatile unsigned char *)(addr))
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#define REG8(addr) (*(volatile unsigned char *)(addr))
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#define REG16(addr) (*(volatile unsigned short *)(addr))
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#define REG32(addr) (*(volatile unsigned int *)(addr))
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#define REG32(addr) (*(volatile unsigned int *)(addr))
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#endif /* !ASSEMBLY */
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//----------------------------------------------------------------------
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// Boot ROM Specification
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//
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/*************************************************************************
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* Boot ROM Specification
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*/
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/* NOR Boot config */
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#define JZ4740_NORBOOT_8BIT 0x00000000 /* 8-bit data bus flash */
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#define JZ4740_NORBOOT_16BIT 0x10101010 /* 16-bit data bus flash */
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#define JZ4740_NORBOOT_32BIT 0x20202020 /* 32-bit data bus flash */
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#define JZ4740_NORBOOT_16BIT 0x10101010 /* 16-bit data bus flash */
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#define JZ4740_NORBOOT_32BIT 0x20202020 /* 32-bit data bus flash */
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/* NAND Boot config */
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#define JZ4740_NANDBOOT_B8R3 0xffffffff /* 8-bit bus & 3 row cycles */
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#define JZ4740_NANDBOOT_B8R2 0xf0f0f0f0 /* 8-bit bus & 2 row cycles */
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#define JZ4740_NANDBOOT_B16R3 0x0f0f0f0f /* 16-bit bus & 3 row cycles */
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#define JZ4740_NANDBOOT_B16R2 0x00000000 /* 16-bit bus & 2 row cycles */
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#define JZ4740_NANDBOOT_B16R3 0x0f0f0f0f /* 16-bit bus & 3 row cycles */
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#define JZ4740_NANDBOOT_B16R2 0x00000000 /* 16-bit bus & 2 row cycles */
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//----------------------------------------------------------------------
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// Register Definitions
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//
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/*************************************************************************
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* Register Definitions
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*/
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#define CPM_BASE 0xB0000000
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#define INTC_BASE 0xB0001000
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#define INTC_BASE 0xB0001000
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#define TCU_BASE 0xB0002000
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#define WDT_BASE 0xB0002000
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#define RTC_BASE 0xB0003000
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#define GPIO_BASE 0xB0010000
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#define GPIO_BASE 0xB0010000
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#define AIC_BASE 0xB0020000
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#define ICDC_BASE 0xB0020000
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#define ICDC_BASE 0xB0020000
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#define MSC_BASE 0xB0021000
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#define UART0_BASE 0xB0030000
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#define UART0_BASE 0xB0030000
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#define I2C_BASE 0xB0042000
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#define SSI_BASE 0xB0043000
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#define SADC_BASE 0xB0070000
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#define SADC_BASE 0xB0070000
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#define EMC_BASE 0xB3010000
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#define DMAC_BASE 0xB3020000
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#define DMAC_BASE 0xB3020000
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#define UHC_BASE 0xB3030000
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#define UDC_BASE 0xB3040000
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#define LCD_BASE 0xB3050000
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#define SLCD_BASE 0xB3050000
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#define SLCD_BASE 0xB3050000
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#define CIM_BASE 0xB3060000
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#define ETH_BASE 0xB3100000
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@ -59,43 +95,43 @@
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*************************************************************************/
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#define INTC_ISR (INTC_BASE + 0x00)
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#define INTC_IMR (INTC_BASE + 0x04)
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#define INTC_IMSR (INTC_BASE + 0x08)
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#define INTC_IMCR (INTC_BASE + 0x0c)
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#define INTC_IMSR (INTC_BASE + 0x08)
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#define INTC_IMCR (INTC_BASE + 0x0c)
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#define INTC_IPR (INTC_BASE + 0x10)
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#define REG_INTC_ISR REG32(INTC_ISR)
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#define REG_INTC_IMR REG32(INTC_IMR)
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#define REG_INTC_IMSR REG32(INTC_IMSR)
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#define REG_INTC_IMCR REG32(INTC_IMCR)
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#define REG_INTC_IMSR REG32(INTC_IMSR)
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#define REG_INTC_IMCR REG32(INTC_IMCR)
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#define REG_INTC_IPR REG32(INTC_IPR)
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// 1st-level interrupts
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#define IRQ_I2C 1
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#define IRQ_EMC 2
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#define IRQ_EMC 2
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#define IRQ_UHC 3
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#define IRQ_UART0 9
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#define IRQ_SADC 12
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#define IRQ_UART0 9
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#define IRQ_SADC 12
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#define IRQ_MSC 14
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#define IRQ_RTC 15
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#define IRQ_SSI 16
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#define IRQ_CIM 17
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#define IRQ_AIC 18
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#define IRQ_ETH 19
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#define IRQ_DMAC 20
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#define IRQ_TCU2 21
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#define IRQ_TCU1 22
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#define IRQ_TCU0 23
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#define IRQ_UDC 24
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#define IRQ_GPIO3 25
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#define IRQ_GPIO2 26
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#define IRQ_GPIO1 27
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#define IRQ_GPIO0 28
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#define IRQ_DMAC 20
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#define IRQ_TCU2 21
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#define IRQ_TCU1 22
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#define IRQ_TCU0 23
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#define IRQ_UDC 24
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#define IRQ_GPIO3 25
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#define IRQ_GPIO2 26
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#define IRQ_GPIO1 27
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#define IRQ_GPIO0 28
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#define IRQ_IPU 29
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#define IRQ_LCD 30
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// 2nd-level interrupts
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#define IRQ_DMA_0 32 /* 32 to 37 for DMAC channel 0 to 5 */
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#define IRQ_GPIO_0 48 /* 48 to 175 for GPIO pin 0 to 127 */
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#define IRQ_DMA_0 32 /* 32 to 37 for DMAC channel 0 to 5 */
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#define IRQ_GPIO_0 48 /* 48 to 175 for GPIO pin 0 to 127 */
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/*************************************************************************
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@ -103,15 +139,15 @@
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*************************************************************************/
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#define RTC_RCR (RTC_BASE + 0x00) /* RTC Control Register */
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#define RTC_RSR (RTC_BASE + 0x04) /* RTC Second Register */
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#define RTC_RSAR (RTC_BASE + 0x08) /* RTC Second Alarm Register */
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#define RTC_RSAR (RTC_BASE + 0x08) /* RTC Second Alarm Register */
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#define RTC_RGR (RTC_BASE + 0x0c) /* RTC Regulator Register */
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#define RTC_HCR (RTC_BASE + 0x20) /* Hibernate Control Register */
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#define RTC_HWFCR (RTC_BASE + 0x24) /* Hibernate Wakeup Filter Counter Reg */
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#define RTC_HRCR (RTC_BASE + 0x28) /* Hibernate Reset Counter Register */
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#define RTC_HWCR (RTC_BASE + 0x2c) /* Hibernate Wakeup Control Register */
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#define RTC_HWRSR (RTC_BASE + 0x30) /* Hibernate Wakeup Status Register */
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#define RTC_HSPR (RTC_BASE + 0x34) /* Hibernate Scratch Pattern Register */
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#define RTC_HWFCR (RTC_BASE + 0x24) /* Hibernate Wakeup Filter Counter Reg */
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#define RTC_HRCR (RTC_BASE + 0x28) /* Hibernate Reset Counter Register */
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#define RTC_HWCR (RTC_BASE + 0x2c) /* Hibernate Wakeup Control Register */
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#define RTC_HWRSR (RTC_BASE + 0x30) /* Hibernate Wakeup Status Register */
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#define RTC_HSPR (RTC_BASE + 0x34) /* Hibernate Scratch Pattern Register */
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#define REG_RTC_RCR REG32(RTC_RCR)
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#define REG_RTC_RSR REG32(RTC_RSR)
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#define SSI_CR1_RTRG_120 (15<< SSI_CR1_RTRG_BIT)
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#define SSI_CR1_FLEN_BIT 4
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#define SSI_CR1_FLEN_MASK (0xf << SSI_CR1_FLEN_BIT)
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#define SSI_CR1_FLEN_2BIT (0x0 << SSI_CR1_FLEN_BIT)
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#define SSI_CR1_FLEN_3BIT (0x1 << SSI_CR1_FLEN_BIT)
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#define SSI_CR1_FLEN_4BIT (0x2 << SSI_CR1_FLEN_BIT)
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#define SSI_CR1_FLEN_5BIT (0x3 << SSI_CR1_FLEN_BIT)
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#define SSI_CR1_FLEN_6BIT (0x4 << SSI_CR1_FLEN_BIT)
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#define SSI_CR1_FLEN_7BIT (0x5 << SSI_CR1_FLEN_BIT)
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#define SSI_CR1_FLEN_8BIT (0x6 << SSI_CR1_FLEN_BIT)
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#define SSI_CR1_FLEN_9BIT (0x7 << SSI_CR1_FLEN_BIT)
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#define SSI_CR1_FLEN_2BIT (0x0 << SSI_CR1_FLEN_BIT)
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#define SSI_CR1_FLEN_3BIT (0x1 << SSI_CR1_FLEN_BIT)
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#define SSI_CR1_FLEN_4BIT (0x2 << SSI_CR1_FLEN_BIT)
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#define SSI_CR1_FLEN_5BIT (0x3 << SSI_CR1_FLEN_BIT)
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#define SSI_CR1_FLEN_6BIT (0x4 << SSI_CR1_FLEN_BIT)
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#define SSI_CR1_FLEN_7BIT (0x5 << SSI_CR1_FLEN_BIT)
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#define SSI_CR1_FLEN_8BIT (0x6 << SSI_CR1_FLEN_BIT)
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#define SSI_CR1_FLEN_9BIT (0x7 << SSI_CR1_FLEN_BIT)
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#define SSI_CR1_FLEN_10BIT (0x8 << SSI_CR1_FLEN_BIT)
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#define SSI_CR1_FLEN_11BIT (0x9 << SSI_CR1_FLEN_BIT)
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#define SSI_CR1_FLEN_12BIT (0xA << SSI_CR1_FLEN_BIT)
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@ -4945,4 +4981,175 @@ do{ \
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#endif /* !__ASSEMBLY__ */
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#ifndef _IPU_H_
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#define _IPU_H_
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// IPU_REG_BASE
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#define IPU_P_BASE 0x13080000
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#define IPU__OFFSET 0x13080000
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#define IPU__SIZE 0x00001000
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struct ipu_module
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{
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unsigned int reg_ctrl; // 0x0
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unsigned int reg_status; // 0x4
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unsigned int reg_d_fmt; // 0x8
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unsigned int reg_y_addr; // 0xc
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unsigned int reg_u_addr; // 0x10
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unsigned int reg_v_addr; // 0x14
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unsigned int reg_in_fm_gs; // 0x18
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unsigned int reg_y_stride; // 0x1c
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unsigned int reg_uv_stride; // 0x20
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unsigned int reg_out_addr; // 0x24
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unsigned int reg_out_gs; // 0x28
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unsigned int reg_out_stride; // 0x2c
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unsigned int rsz_coef_index; // 0x30
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unsigned int reg_csc_c0_coef; // 0x34
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unsigned int reg_csc_c1_coef; // 0x38
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unsigned int reg_csc_c2_coef; // 0x3c
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unsigned int reg_csc_c3_coef; // 0x40
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unsigned int reg_csc_c4_coef; // 0x44
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unsigned int hrsz_coef_lut[20]; // 0x48
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unsigned int vrsz_coef_lut[20]; // 0x98
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};
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typedef struct
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{
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unsigned int coef;
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unsigned short int in_n;
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unsigned short int out_n;
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} rsz_lut;
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struct Ration2m
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{
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float ratio;
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int n, m;
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};
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// Register offset
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#define REG_CTRL 0x0
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#define REG_STATUS 0x4
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#define REG_D_FMT 0x8
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#define REG_Y_ADDR 0xc
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#define REG_U_ADDR 0x10
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#define REG_V_ADDR 0x14
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#define REG_IN_FM_GS 0x18
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#define REG_Y_STRIDE 0x1c
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#define REG_UV_STRIDE 0x20
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#define REG_OUT_ADDR 0x24
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#define REG_OUT_GS 0x28
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#define REG_OUT_STRIDE 0x2c
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#define REG_RSZ_COEF_INDEX 0x30
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#define REG_CSC_C0_COEF 0x34
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#define REG_CSC_C1_COEF 0x38
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#define REG_CSC_C2_COEF 0x3c
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#define REG_CSC_C3_COEF 0x40
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#define REG_CSC_C4_COEF 0x44
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#define HRSZ_LUT_BASE 0x48
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#define VRSZ_LUT_BASE 0x98
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// REG_CTRL field define
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#define IPU_EN (1 << 0)
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#define RSZ_EN (1 << 1)
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#define FM_IRQ_EN (1 << 2)
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#define IPU_RESET (1 << 3)
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#define H_UP_SCALE (1 << 8)
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#define V_UP_SCALE (1 << 9)
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#define H_SCALE_SHIFT (8)
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#define V_SCALE_SHIFT (9)
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// REG_STATUS field define
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#define OUT_END (1 << 0)
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// REG_D_FMT field define
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#define INFMT_YUV420 (0 << 0)
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#define INFMT_YUV422 (1 << 0)
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#define INFMT_YUV444 (2 << 0)
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#define INFMT_YUV411 (3 << 0)
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#define INFMT_YCbCr420 (4 << 0)
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#define INFMT_YCbCr422 (5 << 0)
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#define INFMT_YCbCr444 (6 << 0)
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#define INFMT_YCbCr411 (7 << 0)
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#define OUTFMT_RGB555 (0 << 16)
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#define OUTFMT_RGB565 (1 << 16)
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#define OUTFMT_RGB888 (2 << 16)
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// REG_IN_FM_GS field define
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#define IN_FM_W(val) ((val) << 16)
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#define IN_FM_H(val) ((val) << 0)
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// REG_IN_FM_GS field define
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#define OUT_FM_W(val) ((val) << 16)
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#define OUT_FM_H(val) ((val) << 0)
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// REG_UV_STRIDE field define
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#define U_STRIDE(val) ((val) << 16)
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#define V_STRIDE(val) ((val) << 0)
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#define VE_IDX_SFT 0
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#define HE_IDX_SFT 16
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// RSZ_LUT_FIELD
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#define OUT_N_SFT 0
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#define OUT_N_MSK 0x1
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#define IN_N_SFT 1
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#define IN_N_MSK 0x1
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#define W_COEF_SFT 2
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#define W_COEF_MSK 0xFF
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// function about REG_CTRL
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#define stop_ipu(IPU_V_BASE) \
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REG32(IPU_V_BASE + REG_CTRL) &= ~IPU_EN;
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#define run_ipu(IPU_V_BASE) \
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REG32(IPU_V_BASE + REG_CTRL) |= IPU_EN;
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#define reset_ipu(IPU_V_BASE) \
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REG32(IPU_V_BASE + REG_CTRL) |= IPU_RESET;
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#define disable_irq(IPU_V_BASE) \
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REG32(IPU_V_BASE + REG_CTRL) &= ~FM_IRQ_EN;
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#define disable_rsize(IPU_V_BASE) \
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REG32(IPU_V_BASE + REG_CTRL) &= ~RSZ_EN;
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#define enable_rsize(IPU_V_BASE) \
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REG32(IPU_V_BASE + REG_CTRL) |= RSZ_EN;
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#define ipu_is_enable(IPU_V_BASE) \
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(REG32(IPU_V_BASE + REG_CTRL) & IPU_EN)
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// function about REG_STATUS
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#define clear_end_flag(IPU_V_BASE) \
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REG32(IPU_V_BASE + REG_STATUS) &= ~OUT_END;
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#define polling_end_flag(IPU_V_BASE) \
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(REG32(IPU_V_BASE + REG_STATUS) & OUT_END)
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/* parameter
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R = 1.164 * (Y - 16) + 1.596 * (cr - 128) {C0, C1}
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G = 1.164 * (Y - 16) - 0.392 * (cb -128) - 0.813 * (cr - 128) {C0, C2, C3}
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B = 1.164 * (Y - 16) + 2.017 * (cb - 128) {C0, C4}
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*/
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#if 1
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#define YUV_CSC_C0 0x4A8 /* 1.164 * 1024 */
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#define YUV_CSC_C1 0x662 /* 1.596 * 1024 */
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#define YUV_CSC_C2 0x191 /* 0.392 * 1024 */
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#define YUV_CSC_C3 0x341 /* 0.813 * 1024 */
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#define YUV_CSC_C4 0x811 /* 2.017 * 1024 */
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#else
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#define YUV_CSC_C0 0x400
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#define YUV_CSC_C1 0x59C
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#define YUV_CSC_C2 0x161
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#define YUV_CSC_C3 0x2DC
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#define YUV_CSC_C4 0x718
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#endif
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#endif /* _IPU_H_ */
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#endif /* __JZ4740_H__ */
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