pp5020: use ipod firmware timings for ATA PIO.
Some mSATA adapters seem to have trouble working with Rockbox using our normal PIO timings; the timing value we use is probably out of spec and is different to the OF. Switch to using the OF's timings according to which PIO mode we select. This may not completely resolve problems with these adapters but allows Rockbox to boot and play audio. Change-Id: If73210700eb4af01864b373709ee1d15c775fb11
This commit is contained in:
Torne Wuff
Solomon Peachy
parent
090bd9592d
commit
5db83c155a
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@ -332,7 +332,7 @@ static ICODE_ATTR void copy_write_sectors(const unsigned char* buf,
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}
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#endif /* !ATA_OPTIMIZED_WRITING */
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static inline int ata_disk_isssd(void)
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int ata_disk_isssd(void)
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{
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/* offset 217 is "Nominal Rotation rate"
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0x0000 == Not reported
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@ -165,6 +165,9 @@ int ata_num_drives(int first_drive);
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long ata_last_disk_activity(void);
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int ata_spinup_time(void); /* ticks */
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/* Returns 1 if drive is solid-state */
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int ata_disk_isssd(void);
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#ifdef HAVE_ATA_DMA
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/* Returns current DMA mode */
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int ata_get_dma_mode(void);
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@ -25,8 +25,9 @@
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#include "system.h"
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#include "kernel.h"
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#include "ata-driver.h"
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#include "ata.h"
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void ata_reset()
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void ata_reset()
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{
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}
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@ -43,6 +44,17 @@ bool ata_is_coldstart()
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/* TODO: Implement coldstart variable */
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}
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/* These are PIO timings for 80 Mhz. At 24 Mhz, the first value is 0 but the
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rest are the same. They go in IDE0_PRI_TIMING0.
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Rockbox used to use 0x10, and test_disk shows that leads to faster PIO.
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However on some disks connected with mSATA adapters this causes corrupt data
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so we now just use these timings from the OF.
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*/
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static const unsigned long pio80mhz[] = {
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0xC293, 0x43A2, 0x11A1, 0x7232, 0x3131
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};
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void ata_device_init()
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{
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#ifdef SAMSUNG_YH920
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@ -52,7 +64,7 @@ void ata_device_init()
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IDE_DMA_CONTROL |= 2;
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IDE_DMA_CONTROL &= ~1;
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IDE0_CFG &= ~0x8010;
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IDE0_CFG |= 0x20;
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IDE0_CFG |= 0x20;
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#else
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/* From ipod-ide.c:ipod_ide_register() */
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@ -64,33 +76,31 @@ void ata_device_init()
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#endif
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#endif
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IDE0_PRI_TIMING0 = 0x10;
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IDE0_PRI_TIMING0 = pio80mhz[0];
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IDE0_PRI_TIMING1 = 0x80002150;
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}
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/* These are PIO timings for 80 Mhz. At 24 Mhz,
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the first value is 0 but the rest are the same.
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They go in IDE0_PRI_TIMING0.
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Rockbox used 0x10, and test_disk shows that leads to faster PIO.
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If 0x10 is incorrect, these timings may be needed with some devices.
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static const unsigned long pio80mhz[] = {
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0xC293, 0x43A2, 0x11A1, 0x7232, 0x3131
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};
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*/
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/* Setup the timing for PIO mode */
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void ata_set_pio_timings(int mode)
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{
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if (ata_disk_isssd())
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IDE0_PRI_TIMING0 = pio80mhz[mode];
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else
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IDE0_PRI_TIMING0 = 0x10;
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}
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#ifdef HAVE_ATA_DMA
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/* Timings for multi-word and ultra DMA modes.
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These go in IDE0_PRI_TIMING1
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*/
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static const unsigned long tm_mwdma[] = {
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0xF9F92, 0x56562, 0x45451
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0xF9F92, 0x56562, 0x45451
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};
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static const unsigned long tm_udma[] = {
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0x800037C1, 0x80003491, 0x80003371,
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#if ATA_MAX_UDMA > 2
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0x80003271, 0x80003071
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static const unsigned long tm_udma[] = {
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0x800037C1, 0x80003491, 0x80003371,
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#if ATA_MAX_UDMA > 2
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0x80003271, 0x80003071
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#endif
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};
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@ -126,7 +136,7 @@ void ata_dma_set_mode(unsigned char mode) {
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#if !defined(IPOD_NANO)
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IDE0_CFG |= 0x20000000; /* >= 50 Mhz */
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#endif
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}
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}
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#define IDE_CFG_INTRQ 8
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#define IDE_DMA_CONTROL_READ 8
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@ -137,8 +147,8 @@ void ata_dma_set_mode(unsigned char mode) {
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static ICODE_ATTR int ata_wait_intrq(void)
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{
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long timeout = current_tick + HZ*10;
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do
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do
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{
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if (IDE0_CFG & IDE_CFG_INTRQ)
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return 1;
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@ -149,11 +159,11 @@ static ICODE_ATTR int ata_wait_intrq(void)
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return 0; /* timeout */
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}
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/* This function checks if parameters are appropriate for DMA,
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/* This function checks if parameters are appropriate for DMA,
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and if they are, it sets up for DMA.
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If return value is false, caller may use PIO for this transfer.
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If return value is true, caller must issue a DMA ATA command
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and then call ata_dma_finish().
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*/
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@ -217,18 +227,18 @@ bool ata_dma_setup(void *addr, unsigned long bytes, bool write) {
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/* This function waits for a DMA transfer to end.
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It must be called to finish what ata_dma_setup started.
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Return value is true if DMA completed before the timeout, and false
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if a timeout happened.
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*/
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bool ata_dma_finish(void) {
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bool res;
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/* It may be okay to put this at the end of setup */
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IDE_DMA_CONTROL |= 1;
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/* Wait for end of transfer.
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Reading standard ATA status while DMA is in progress causes
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Reading standard ATA status while DMA is in progress causes
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failures and hangs. Because of that, another wait is used.
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*/
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res = ata_wait_intrq();
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@ -49,6 +49,8 @@
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#define ATA_OPTIMIZED_READING
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#define ATA_OPTIMIZED_WRITING
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#define ATA_SET_PIO_TIMING
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#endif /* CONFIG_CPU */
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#ifdef HAVE_ATA_DMA
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