as3525v2: use the new USB DesignWare driver

Targets: sansaclipplus, samsaclipv2, sansaclipzip, sansafuzev2.

Change-Id: I7773528a4e26707dd33fe9cb8948750d49570701

firmware/export/as3525v2.h

@@ -37,7 +37,7 @@
 #define CGU_SDSLOT         (*(volatile unsigned long *)(CGU_BASE + 0x3C))
 
 #undef USB_NUM_ENDPOINTS
-
+/* 7 available EPs (0b00000000010101010000000000101011), 6 used */
 #define USB_NUM_ENDPOINTS   6
 
 #define CCU_USB         (*(volatile unsigned long *)(CCU_BASE + 0x20))
@@ -45,4 +45,8 @@
 #undef USB_DEVBSS_ATTR
 #define USB_DEVBSS_ATTR __attribute__((aligned(32)))
 
+/* Define this if the DWC implemented on this SoC does not support
+   DMA or you want to disable it. */
+// #define USB_DW_ARCH_SLAVE
+
 #endif /* __AS3525V2_H__ */

firmware/export/config/sansaclipplus.h

@@ -183,7 +183,9 @@
 #define CONFIG_LCD LCD_SSD1303
 
 /* USB On-the-go */
-#define CONFIG_USBOTG USBOTG_S3C6400X
+#define CONFIG_USBOTG USBOTG_DESIGNWARE
+/* logf() over USB serial (http://www.rockbox.org/wiki/PortalPlayerUsb) */
+//#define USB_ENABLE_SERIAL
 
 /* enable these for the experimental usb stack */
 #define HAVE_USBSTACK

firmware/export/config/sansaclipv2.h

@@ -179,7 +179,9 @@
 #define CONFIG_LCD LCD_SSD1303
 
 /* USB On-the-go */
-#define CONFIG_USBOTG USBOTG_S3C6400X
+#define CONFIG_USBOTG USBOTG_DESIGNWARE
+/* logf() over USB serial (http://www.rockbox.org/wiki/PortalPlayerUsb) */
+//#define USB_ENABLE_SERIAL
 
 /* enable these for the experimental usb stack */
 #define HAVE_USBSTACK

firmware/export/config/sansaclipzip.h

@@ -182,7 +182,9 @@
 #define CONFIG_LCD LCD_CLIPZIP
 
 /* USB On-the-go */
-#define CONFIG_USBOTG USBOTG_S3C6400X
+#define CONFIG_USBOTG USBOTG_DESIGNWARE
+/* logf() over USB serial (http://www.rockbox.org/wiki/PortalPlayerUsb) */
+//#define USB_ENABLE_SERIAL
 
 /* enable these for the experimental usb stack */
 #define HAVE_USBSTACK

firmware/export/config/sansafuzev2.h

@@ -203,7 +203,9 @@
 #endif
 
 /* USB On-the-go */
-#define CONFIG_USBOTG USBOTG_S3C6400X
+#define CONFIG_USBOTG USBOTG_DESIGNWARE
+/* logf() over USB serial (http://www.rockbox.org/wiki/PortalPlayerUsb) */
+//#define USB_ENABLE_SERIAL
 
 /* enable these for the experimental usb stack */
 #define HAVE_USBSTACK

firmware/target/arm/as3525/system-as3525.c

@@ -50,7 +50,9 @@
 #define default_interrupt(name) \
   extern __attribute__((weak,alias("UIRQ"))) void name (void)
 
+#if CONFIG_USBOTG != USBOTG_DESIGNWARE
 static void UIRQ (void) __attribute__((interrupt ("IRQ")));
+#endif
 void irq_handler(void) __attribute__((naked, interrupt ("IRQ")));
 void fiq_handler(void) __attribute__((interrupt ("FIQ")));
 
@@ -105,6 +107,11 @@ static void UIRQ(void)
     if(status == 0)
     {
         status = VIC_RAW_INTR; /* masked interrupts */
+#if CONFIG_USBOTG == USBOTG_DESIGNWARE
+        /* spurious interrupts from USB are expected */
+        if (status & INTERRUPT_USB)
+            return;
+#endif
         masked = true;
     }
 

firmware/target/arm/as3525/usb-as3525.c

@@ -27,6 +27,26 @@
 #include "power.h"
 #include "as3525.h"
 #include "usb_drv.h"
+#if CONFIG_USBOTG == USBOTG_DESIGNWARE
+#include "usb-designware.h"
+
+const struct usb_dw_config usb_dw_config =
+{
+    .phytype = DWC_PHYTYPE_UTMI_16,
+
+    /* Available FIFO memory: 0x535 words */
+    .rx_fifosz   = 0x215,
+    .nptx_fifosz = 0x20,   /* 1 dedicated FIFO for IN0 */
+    .ptx_fifosz  = 0x100,  /* 3 dedicated FIFOs for IN1,IN3,IN5 */
+
+#ifdef USB_DW_ARCH_SLAVE
+    .disable_double_buffering = false,
+#else
+    .ahb_burst_len = HBSTLEN_INCR8,
+    .ahb_threshold = 8,
+#endif
+};
+#endif /* USBOTG_DESIGNWARE */
 
 static int usb_status = USB_EXTRACTED;
 
@@ -68,4 +88,53 @@ int usb_detect(void)
 
 void usb_init_device(void)
 {
+#if CONFIG_USBOTG == USBOTG_DESIGNWARE
+    /* Power up the core clocks to allow writing
+       to some registers needed to power it down */
+    usb_dw_target_disable_irq();
+    usb_dw_target_enable_clocks();
+
+    usb_drv_exit();
+}
+
+void usb_dw_target_enable_clocks()
+{
+    bitset32(&CGU_PERI, CGU_USB_CLOCK_ENABLE);
+    CCU_USB = (CCU_USB & ~(3<<24)) | (1 << 24); /* ?? */
+    /* PHY clock */
+    CGU_USB = 1<<5  /* enable */
+        | 0 << 2
+        | 0; /* source = ? (24MHz crystal?) */
+
+    /* Do something that is probably CCU related but undocumented*/
+    CCU_USB |= 0x1000;
+    CCU_USB &= ~0x300000;
+
+    udelay(400);
+}
+
+void usb_dw_target_disable_clocks()
+{
+    CGU_USB = 0;
+    bitclr32(&CGU_PERI, CGU_USB_CLOCK_ENABLE);
+
+    /* reset USB_PHY to prevent power consumption */
+    CCU_SRC = CCU_SRC_USB_PHY_EN;
+    CCU_SRL = CCU_SRL_MAGIC_NUMBER;
+    CCU_SRL = 0;
+}
+
+void usb_dw_target_enable_irq()
+{
+    VIC_INT_ENABLE = INTERRUPT_USB;
+}
+
+void usb_dw_target_disable_irq()
+{
+    VIC_INT_EN_CLEAR = INTERRUPT_USB;
+}
+
+void usb_dw_target_clear_irq()
+{
+#endif /* USBOTG_DESIGNWARE */
 }