Split ARMv6 code from mmu-arm.S
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@23244 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Rafaël Carré
parent
b424b852e5
commit
735b522929
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@ -831,7 +831,7 @@ target/arm/s3c2440/gigabeat-fx/wmcodec-meg-fx.c
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#ifdef GIGABEAT_S
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#ifndef SIMULATOR
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target/arm/lcd-as-memframe.S
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target/arm/mmu-arm.S
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target/arm/mmu-armv6.S
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target/arm/imx31/ccm-imx31.c
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target/arm/imx31/debug-imx31.c
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target/arm/imx31/rolo_restart.S
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@ -21,140 +21,8 @@
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#include "config.h"
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#include "cpu.h"
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#if CONFIG_CPU == IMX31L
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/* TTB routines not used */
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/** Cache coherency **/
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/*
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* Invalidate DCache for this range
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* will do write back
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* void invalidate_dcache_range(const void *base, unsigned int size)
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*/
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.section .text, "ax", %progbits
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.align 2
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.global invalidate_dcache_range
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.type invalidate_dcache_range, %function
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@ MVA format: 31:5 = Modified virtual address, 4:0 = Ignored
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invalidate_dcache_range:
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add r1, r0, r1 @ size -> end
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cmp r1, r0 @ end <= start?
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subhi r1, r1, #1 @ round it down
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movhi r2, #0 @
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mcrrhi p15, 0, r1, r0, c14 @ Clean and invalidate DCache range
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mcrhi p15, 0, r2, c7, c10, 4 @ Data synchronization barrier
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bx lr @
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.size invalidate_dcache_range, .-invalidate_dcache_range
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/*
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* clean DCache for this range
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* forces DCache writeback for the specified range
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* void clean_dcache_range(const void *base, unsigned int size);
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*/
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.section .text, "ax", %progbits
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.align 2
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.global clean_dcache_range
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.type clean_dcache_range, %function
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@ MVA format: 31:5 = Modified virtual address, 4:0 = Ignored
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clean_dcache_range:
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add r1, r0, r1 @ size -> end
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cmp r1, r0 @ end <= start?
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subhi r1, r1, #1 @ round it down
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movhi r2, #0 @
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mcrrhi p15, 0, r1, r0, c12 @ Clean DCache range
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mcrhi p15, 0, r2, c7, c10, 4 @ Data synchronization barrier
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bx lr @
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.size clean_dcache_range, .-clean_dcache_range
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/*
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* Dump DCache for this range
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* will *NOT* do write back except for buffer edges not on a line boundary
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* void dump_dcache_range(const void *base, unsigned int size);
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*/
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.section .text, "ax", %progbits
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.align 2
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.global dump_dcache_range
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.type dump_dcache_range, %function
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@ MVA format (mcr): 31:5 = Modified virtual address, 4:0 = SBZ
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@ MVA format (mcrr): 31:5 = Modified virtual address, 4:0 = Ignored
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dump_dcache_range:
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add r1, r0, r1 @ size -> end
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cmp r1, r0 @ end <= start?
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bxls lr @
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tst r0, #31 @ Check first line for bits set
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bicne r0, r0, #31 @ Clear low five bits (down)
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mcrne p15, 0, r0, c7, c14, 1 @ Clean and invalidate line by MVA
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@ if not cache aligned
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addne r0, r0, #32 @ Move to the next cache line
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@
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tst r1, #31 @ Check last line for bits set
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bicne r1, r1, #31 @ Clear low five bits (down)
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mcrne p15, 0, r1, c7, c14, 1 @ Clean and invalidate line by MVA
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@ if not cache aligned
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sub r1, r1, #32 @ Move to the previous cache line
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cmp r1, r0 @ end < start now?
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mcrrhs p15, 0, r1, r0, c6 @ Invalidate DCache range
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mov r0, #0 @
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mcr p15, 0, r0, c7, c10, 4 @ Data synchronization barrier
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bx lr @
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.size dump_dcache_range, .-dump_dcache_range
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/*
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* Cleans entire DCache
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* void clean_dcache(void);
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*/
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.section .text, "ax", %progbits
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.align 2
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.global clean_dcache
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.type clean_dcache, %function
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.global cpucache_flush @ Alias
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clean_dcache:
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cpucache_flush:
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mov r0, #0 @
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mcr p15, 0, r0, c7, c10, 0 @ Clean entire DCache
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mcr p15, 0, r0, c7, c10, 4 @ Data synchronization barrier
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bx lr @
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.size clean_dcache, .-clean_dcache
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/*
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* Invalidate entire DCache
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* will do writeback
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* void invalidate_dcache(void);
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*/
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.section .text, "ax", %progbits
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.align 2
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.global invalidate_dcache
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.type invalidate_dcache, %function
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invalidate_dcache:
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mov r0, #0 @
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mcr p15, 0, r0, c7, c14, 0 @ Clean and invalidate entire DCache
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mcr p15, 0, r0, c7, c10, 4 @ Data synchronization barrier
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bx lr @
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.size invalidate_dcache, .-invalidate_dcache
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/*
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* Invalidate entire ICache and DCache
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* will do writeback
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* void invalidate_idcache(void);
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*/
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.section .text, "ax", %progbits
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.align 2
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.global invalidate_idcache
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.type invalidate_idcache, %function
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.global cpucache_invalidate @ Alias
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invalidate_idcache:
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cpucache_invalidate:
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mov r0, #0 @
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mcr p15, 0, r0, c7, c14, 0 @ Clean and invalidate entire DCache
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mcr p15, 0, r0, c7, c5, 0 @ Invalidate entire ICache
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@ Also flushes the branch target cache
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mcr p15, 0, r0, c7, c10, 4 @ Data synchronization barrier
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mcr p15, 0, r0, c7, c5, 4 @ Flush prefetch buffer (IMB)
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bx lr @
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.size invalidate_idcache, .-invalidate_idcache
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#else /* !IMX31L */
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/* Used by ARMv4 & ARMv5 CPUs with cp15 register and MMU */
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/* WARNING : assume size of a data cache line == 32 bytes */
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/** MMU setup **/
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@ -483,6 +351,3 @@ cpucache_invalidate:
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mcr p15, 0, r0, c7, c5, 0 @ Invalidate ICache (r0=0 from call)
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mov pc, r1 @
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.size invalidate_idcache, .-invalidate_idcache
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#endif /* !IMX31L */
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@ -0,0 +1,154 @@
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/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2006,2007 by Greg White
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include "config.h"
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#include "cpu.h"
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/* TTB routines not used */
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/** Cache coherency **/
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/*
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* Invalidate DCache for this range
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* will do write back
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* void invalidate_dcache_range(const void *base, unsigned int size)
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*/
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.section .text, "ax", %progbits
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.align 2
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.global invalidate_dcache_range
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.type invalidate_dcache_range, %function
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@ MVA format: 31:5 = Modified virtual address, 4:0 = Ignored
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invalidate_dcache_range:
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add r1, r0, r1 @ size -> end
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cmp r1, r0 @ end <= start?
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subhi r1, r1, #1 @ round it down
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movhi r2, #0 @
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mcrrhi p15, 0, r1, r0, c14 @ Clean and invalidate DCache range
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mcrhi p15, 0, r2, c7, c10, 4 @ Data synchronization barrier
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bx lr @
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.size invalidate_dcache_range, .-invalidate_dcache_range
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/*
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* clean DCache for this range
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* forces DCache writeback for the specified range
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* void clean_dcache_range(const void *base, unsigned int size);
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*/
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.section .text, "ax", %progbits
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.align 2
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.global clean_dcache_range
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.type clean_dcache_range, %function
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@ MVA format: 31:5 = Modified virtual address, 4:0 = Ignored
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clean_dcache_range:
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add r1, r0, r1 @ size -> end
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cmp r1, r0 @ end <= start?
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subhi r1, r1, #1 @ round it down
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movhi r2, #0 @
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mcrrhi p15, 0, r1, r0, c12 @ Clean DCache range
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mcrhi p15, 0, r2, c7, c10, 4 @ Data synchronization barrier
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bx lr @
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.size clean_dcache_range, .-clean_dcache_range
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/*
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* Dump DCache for this range
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* will *NOT* do write back except for buffer edges not on a line boundary
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* void dump_dcache_range(const void *base, unsigned int size);
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*/
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.section .text, "ax", %progbits
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.align 2
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.global dump_dcache_range
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.type dump_dcache_range, %function
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@ MVA format (mcr): 31:5 = Modified virtual address, 4:0 = SBZ
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@ MVA format (mcrr): 31:5 = Modified virtual address, 4:0 = Ignored
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dump_dcache_range:
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add r1, r0, r1 @ size -> end
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cmp r1, r0 @ end <= start?
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bxls lr @
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tst r0, #31 @ Check first line for bits set
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bicne r0, r0, #31 @ Clear low five bits (down)
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mcrne p15, 0, r0, c7, c14, 1 @ Clean and invalidate line by MVA
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@ if not cache aligned
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addne r0, r0, #32 @ Move to the next cache line
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@
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tst r1, #31 @ Check last line for bits set
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bicne r1, r1, #31 @ Clear low five bits (down)
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mcrne p15, 0, r1, c7, c14, 1 @ Clean and invalidate line by MVA
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@ if not cache aligned
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sub r1, r1, #32 @ Move to the previous cache line
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cmp r1, r0 @ end < start now?
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mcrrhs p15, 0, r1, r0, c6 @ Invalidate DCache range
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mov r0, #0 @
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mcr p15, 0, r0, c7, c10, 4 @ Data synchronization barrier
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bx lr @
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.size dump_dcache_range, .-dump_dcache_range
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/*
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* Cleans entire DCache
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* void clean_dcache(void);
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*/
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.section .text, "ax", %progbits
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.align 2
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.global clean_dcache
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.type clean_dcache, %function
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.global cpucache_flush @ Alias
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clean_dcache:
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cpucache_flush:
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mov r0, #0 @
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mcr p15, 0, r0, c7, c10, 0 @ Clean entire DCache
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mcr p15, 0, r0, c7, c10, 4 @ Data synchronization barrier
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bx lr @
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.size clean_dcache, .-clean_dcache
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/*
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* Invalidate entire DCache
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* will do writeback
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* void invalidate_dcache(void);
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*/
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.section .text, "ax", %progbits
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.align 2
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.global invalidate_dcache
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.type invalidate_dcache, %function
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invalidate_dcache:
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mov r0, #0 @
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mcr p15, 0, r0, c7, c14, 0 @ Clean and invalidate entire DCache
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mcr p15, 0, r0, c7, c10, 4 @ Data synchronization barrier
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bx lr @
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.size invalidate_dcache, .-invalidate_dcache
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/*
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* Invalidate entire ICache and DCache
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* will do writeback
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* void invalidate_idcache(void);
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*/
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.section .text, "ax", %progbits
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.align 2
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.global invalidate_idcache
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.type invalidate_idcache, %function
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.global cpucache_invalidate @ Alias
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invalidate_idcache:
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cpucache_invalidate:
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mov r0, #0 @
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mcr p15, 0, r0, c7, c14, 0 @ Clean and invalidate entire DCache
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mcr p15, 0, r0, c7, c5, 0 @ Invalidate entire ICache
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@ Also flushes the branch target cache
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mcr p15, 0, r0, c7, c10, 4 @ Data synchronization barrier
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mcr p15, 0, r0, c7, c5, 4 @ Flush prefetch buffer (IMB)
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bx lr @
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.size invalidate_idcache, .-invalidate_idcache
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