From 74a3d1f5be2d364a33f37e0ad621538df1bfba4b Mon Sep 17 00:00:00 2001
From: Aidan MacDonald <amachronic@protonmail.com>
Date: Wed, 3 Mar 2021 17:54:38 +0000
Subject: [PATCH] Fix MIPS cache operations and enable HAVE_CPU_CACHE_ALIGN on
 MIPS

- The range-based cache operations on MIPS were broken and only worked
  properly when BOTH the address and size were multiples of the cache
  line size. If this was not the case, the last cache line of the range
  would not be touched!

  Fix is to align start/end pointers to cache lines before iterating.

- To my knowledge all MIPS processors have a cache, so I enabled
  HAVE_CPU_CACHE_ALIGN by default. This also allows mmu-mips.c to use
  the CACHEALIGN_UP/DOWN macros.

- Make jz4760/system-target.h define its cache line size properly.

Change-Id: I1fcd04a59791daa233b9699f04d5ac1cc6bacee7
---
 firmware/export/system.h                      |  4 ++
 .../mips/ingenic_jz47xx/system-target.h       |  2 +-
 firmware/target/mips/mmu-mips.c               | 39 ++++++++++++-------
 3 files changed, 29 insertions(+), 16 deletions(-)

diff --git a/firmware/export/system.h b/firmware/export/system.h
index f9a074349b..f554ac7cf1 100644
--- a/firmware/export/system.h
+++ b/firmware/export/system.h
@@ -253,6 +253,10 @@ static inline void cpu_boost_unlock(void)
     #define MIN_STACK_ALIGN 8
 #endif
 
+#ifdef CPU_MIPS
+    #define HAVE_CPU_CACHE_ALIGN
+#endif
+
 /* Define this if target has support for generating backtraces */
 #ifdef CPU_ARM
     #define HAVE_RB_BACKTRACE
diff --git a/firmware/target/mips/ingenic_jz47xx/system-target.h b/firmware/target/mips/ingenic_jz47xx/system-target.h
index 9dc1a5c8c8..862ec403d2 100644
--- a/firmware/target/mips/ingenic_jz47xx/system-target.h
+++ b/firmware/target/mips/ingenic_jz47xx/system-target.h
@@ -29,7 +29,7 @@
 #include "mipsregs.h"
 
 #define CACHE_SIZE       16*1024
-#define CACHE_LINE_SIZE  32
+#define CACHEALIGN_BITS  5
 #include "mmu-mips.h"
 
 #define CFG_UART_BASE    UART1_BASE      /* Base of the UART channel */
diff --git a/firmware/target/mips/mmu-mips.c b/firmware/target/mips/mmu-mips.c
index eb7004952e..f4ffbfa6ee 100644
--- a/firmware/target/mips/mmu-mips.c
+++ b/firmware/target/mips/mmu-mips.c
@@ -192,10 +192,11 @@ void commit_discard_dcache(void)
  */
 void commit_discard_dcache_range(const void *base, unsigned int size)
 {
-    register char *s;
+    char *ptr = CACHEALIGN_DOWN((char*)base);
+    char *end = CACHEALIGN_UP((char*)base + size);
 
-    for (s=(char *)base; s<(char *)base+size; s+=CACHEALIGN_SIZE)
-        __CACHE_OP(DCHitWBInv, s);
+    for(; ptr != end; ptr += CACHEALIGN_SIZE)
+        __CACHE_OP(DCHitWBInv, ptr);
 
     SYNC_WB();
 }
@@ -204,10 +205,11 @@ void commit_discard_dcache_range(const void *base, unsigned int size)
  */
 void commit_dcache_range(const void *base, unsigned int size)
 {
-    register char *s;
+    char *ptr = CACHEALIGN_DOWN((char*)base);
+    char *end = CACHEALIGN_UP((char*)base + size);
 
-    for (s=(char *)base; s<(char *)base+size; s+=CACHEALIGN_SIZE)
-        __CACHE_OP(DCHitWB, s);
+    for(; ptr != end; ptr += CACHEALIGN_SIZE)
+        __CACHE_OP(DCHitWB, ptr);
 
     SYNC_WB();
 }
@@ -217,17 +219,24 @@ void commit_dcache_range(const void *base, unsigned int size)
  */
 void discard_dcache_range(const void *base, unsigned int size)
 {
-    register char *s;
+    char *ptr = CACHEALIGN_DOWN((char*)base);
+    char *end = CACHEALIGN_UP((char*)base + size);
 
-    if (((int)base & CACHEALIGN_SIZE - 1) ||
-	(((int)base + size) & CACHEALIGN_SIZE - 1)) {
-            /* Overlapping sections, so we need to write back instead */
-            commit_discard_dcache_range(base, size);
-            return;
-    };
+    if(ptr != base) {
+        /* Start of region not cache aligned */
+        __CACHE_OP(DCHitWBInv, ptr);
+        ptr += CACHEALIGN_SIZE;
+    }
 
-    for (s=(char *)base; s<(char *)base+size; s+=CACHEALIGN_SIZE)
-        __CACHE_OP(DCHitInv, s);
+    if(base+size != end) {
+        /* End of region not cache aligned */
+        end -= CACHEALIGN_SIZE;
+        __CACHE_OP(DCHitWBInv, end);
+    }
+
+    /* Interior of region is safe to discard */
+    for(; ptr != end; ptr += CACHEALIGN_SIZE)
+        __CACHE_OP(DCHitInv, ptr);
 
     SYNC_WB();
 }