nihilazo
/
rockbox
1
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

Initial commit of work-in-progress iPod port 

git-svn-id: svn://svn.rockbox.org/rockbox/trunk@7781 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Dave Chapman 2005-11-07 23:07:19 +00:00
parent 3cd5c646d0
commit 77372d1218
24 changed files with 2178 additions and 21 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
firmware/SOURCES
View File

@ -57,6 +57,8 @@ bidi.c
drivers/lcd-h100.c
#elif LCD_DEPTH == 1
drivers/lcd-recorder.c
#elif LCD_DEPTH == 16
drivers/lcd-16bit.c
#endif
#endif
drivers/power.c
@ -85,6 +87,8 @@ tuner_philips.c
#endif
#if CONFIG_I2C == I2C_COLDFIRE
drivers/i2c-coldfire.c
#elif CONFIG_I2C == I2C_PP5020
drivers/i2c-pp5020.c
#else
drivers/i2c.c
#endif

44
firmware/app.lds
View File

@ -3,12 +3,17 @@
ENTRY(start)
#ifdef CPU_COLDFIRE
OUTPUT_FORMAT(elf32-m68k)
INPUT(crt0.o)
#elif CONFIG_CPU == TCC730
OUTPUT_FORMAT(elf32-calmrisc16)
INPUT(crt0.o)
#elif CONFIG_CPU == PP5020
OUTPUT_FORMAT(elf32-littlearm)
OUTPUT_ARCH(arm)
#else
OUTPUT_FORMAT(elf32-sh)
#endif
INPUT(crt0.o)
#endif
#if CONFIG_CPU == TCC730
MEMORY
@ -98,7 +103,44 @@ _audiobufend = 0;
_pluginbuf = 0;
}
#elif CONFIG_CPU==PP5020
SECTIONS
{
. = 0x10000000;
.text : {
*(.init.text)
*(.text)
}
__data_start__ = . ;
.data : { *(.data) }
__data_end__ = . ;
__stack_start__ = .;
.stack :
{
*(.stack)
_stackbegin = .;
stackbegin = .;
. += 0x2000;
_stackend = .;
stackend = .;
}
/* The bss section is too large for IRAM - we just move it at the
end of the regular RAM. */
. = 0x11c00000;
__bss_start__ = .;
.bss : {
*(.bss);
__bss_end__ = . ;
}
}
#else
#define PLUGINSIZE PLUGIN_BUFFER_SIZE

10
firmware/backlight.c
View File

@ -212,6 +212,10 @@ static void __backlight_off(void)
and_b(~0x40, &PADRH); /* drive it low */
#elif CONFIG_BACKLIGHT == BL_GMINI
P1 &= ~0x10;
#elif CONFIG_BACKLIGHT == BL_IPOD4G
/* fades backlight off on 4g */
outl(inl(0x70000084) & ~0x2000000, 0x70000084);
outl(0x80000000, 0x7000a010);
#endif
}
@ -235,6 +239,12 @@ static void __backlight_on(void)
or_b(0x40, &PADRH); /* drive it high */
#elif CONFIG_BACKLIGHT == BL_GMINI
P1 |= 0x10;
#elif CONFIG_BACKLIGHT == BL_IPOD4G
/* brightness full */
outl(0x80000000 | (0xff << 16), 0x7000a010);
/* set port b bit 3 on */
outl(((0x100 | 1) << 3), 0x6000d824);
#endif
}

55
firmware/boot.lds
View File

@ -3,10 +3,14 @@
ENTRY(start)
#ifdef CPU_COLDFIRE
OUTPUT_FORMAT(elf32-m68k)
INPUT(crt0.o)
#elif CONFIG_CPU == PP5020
OUTPUT_FORMAT(elf32-littlearm)
OUTPUT_ARCH(arm)
#else
OUTPUT_FORMAT(elf32-sh)
#endif
INPUT(crt0.o)
#endif
#if MEMORYSIZE >= 32
#define PLUGINSIZE 0xC0000
@ -22,6 +26,12 @@ INPUT(crt0.o)
#define IRAMSIZE 0x18000
#define FLASHORIG 0x001f0000
#define FLASHSIZE 2M
#elif CONFIG_CPU == PP5020
#define DRAMORIG 0x10000000
#define IRAMORIG 0x40000000
#define IRAMSIZE 0x18000
#define FLASHORIG 0x001f0000
#define FLASHSIZE 2M
#else
#define DRAMORIG 0x09000000
#define IRAMORIG 0x0f000000
@ -32,13 +42,55 @@ INPUT(crt0.o)
#define ENDADDR (IRAMORIG + IRAMSIZE)
#if CONFIG_CPU!=PP5020
MEMORY
{
DRAM : ORIGIN = DRAMORIG, LENGTH = DRAMSIZE
IRAM : ORIGIN = IRAMORIG, LENGTH = IRAMSIZE
FLASH : ORIGIN = FLASHORIG, LENGTH = FLASHSIZE
}
#endif
SECTIONS
#if CONFIG_CPU==PP5020
{
. = IRAMORIG;
.text : {
*(.init.text)
*(.text)
}
.data : {
*(.icode)
*(.irodata)
*(.idata)
*(.data)
_dataend = . ;
}
.stack :
{
*(.stack)
_stackbegin = .;
stackbegin = .;
. += 0x2000;
_stackend = .;
stackend = .;
}
/* The bss section is too large for IRAM - we just move it near the
end of the regular RAM. */
. = 0x11c00000;
.bss : {
_bssstart = .;
*(.bss);
*(.ibss);
_bssend = . ;
}
}
#else
{
.vectors :
{
@ -114,3 +166,4 @@ SECTIONS
_pluginbuf = .;
}
}
#endif

135
firmware/crt0.S
View File

@ -19,10 +19,136 @@
#include "config.h"
#include "cpu.h"
#if (CONFIG_CPU == PP5002) || (CONFIG_CPU == PP5020)
.section .init.text
#else
.section .init.text,"ax",@progbits
#endif
.global start
start:
#if CONFIG_CPU == TCC730
#if (CONFIG_CPU == PP5002) || (CONFIG_CPU == PP5020)
/* Based on startup.s from the iPodLinux loader
*
* Copyright (c) 2003, Daniel Palffy (dpalffy (at) rainstorm.org)
* Copyright (c) 2005, Bernard Leach <leachbj@bouncycastle.org>
*
*/
.equ PP5002_PROC_ID, 0xc4000000
.equ PP5002COP_CTRL, 0xcf004058
.equ PP5020_PROC_ID, 0x60000000
.equ PP5020_COP_CTRL, 0x60007004
start:
/* get the high part of our execute address */
ldr r0, =0xff000000
and r8, pc, r0 @ r8 is used later
#if CONFIG_CPU==PP5002
mov r0, #PP5002_PROC_ID
#else
mov r0, #PP5020_PROC_ID
#endif
ldr r0, [r0]
and r0, r0, #0xff
cmp r0, #0x55
beq 1f
/* put us (co-processor) to sleep */
#if CONFIG_CPU==PP5002
ldr r4, =PP5002_COP_CTRL
mov r3, #0xca
#else
ldr r4, =PP5020_COP_CTRL
mov r3, #0x80000000
#endif
str r3, [r4]
ldr pc, =cop_wake_start
cop_wake_start:
/* jump the COP to startup */
ldr r0, =startup_loc
ldr pc, [r0]
1:
/* setup some stack */
ldr sp, = _stackbegin
/* get the high part of our execute address */
ldr r2, =0xffffff00
and r4, pc, r2
/* Copy bootloader to safe area - 0x40000000 */
mov r5, #0x40000000
ldr r6, = _dataend
sub r0, r6, r5 /* length of loader */
add r0, r4, r0 /* r0 points to start of loader */
1:
cmp r5, r6
ldrcc r2, [r4], #4
strcc r2, [r5], #4
bcc 1b
ldr pc, =start_loc /* jump to the relocated start_loc: */
start_loc:
/* Initialise bss section to zero */
ldr r3, =_bssstart
ldr r1, =_bssend
mov r2, #0x0
1:
cmp r3, r1
strcc r2, [r3], #4
bcc 1b
/* execute the loader - this will load an image to 0x10000000 */
bl main
/* save the startup address for the COP */
ldr r1, =startup_loc
str r0, [r1]
#if CONFIG_CPU==PP5002
/* make sure COP is sleeping */
ldr r4, =0xcf004050
1:
ldr r3, [r4]
ands r3, r3, #0x4000
beq 1b
/* wake up COP */
ldr r4, =PP5002_COP_CTRL
mov r3, #0xce
strh r3, [r4]
#else
/* make sure COP is sleeping */
ldr r4, =PP5020_COP_CTRL
1:
ldr r3, [r4]
ands r3, r3, #0x80000000
beq 1b
/* wake up COP */
@ ldr r4, =PP5020_COP_CTRL
mov r3, #0x0
str r3, [r4]
#endif
/* jump to start location */
mov pc, r0
startup_loc:
.word 0x0
.align 8 /* starts at 0x100 */
.global boot_table
boot_table:
/* here comes the boot table, don't move its offset */
.space 400
#elif CONFIG_CPU == TCC730
/* Platform: Gmini 120/SP */
;; disable all interrupts
clrsr fe
@ -331,6 +457,13 @@ vectors:
/* Platform: iRiver H320/H340 */
/* Fill in code here */
#elif CONFIG_CPU == PP5020
/* Platform: iPod */
#warning TODO: Implement crt0.S
/* Fill in code here */
#else
/* Platform: Archos Jukebox */

14
firmware/drivers/adc.c
View File

@ -254,4 +254,18 @@ void adc_init(void)
sleep(2); /* Ensure valid readings when adc_init returns */
}
#elif CONFIG_CPU == PP5020
#warning Implement adc.c
unsigned short adc_read(int channel)
{
return 0;
}
void adc_init(void)
{
}
#endif

61
firmware/drivers/ata.c
View File

@ -71,6 +71,43 @@
#define SET_REG(reg,val) reg = ((val) << 8)
#define SET_16BITREG(reg,val) reg = (val)
#elif CONFIG_CPU == PP5020
/* don't use sh7034 assembler routines */
#define PREFER_C_READING
#define PREFER_C_WRITING
#define ATA_IOBASE 0xc30001e0
#define ATA_DATA (*((volatile unsigned short*)(ATA_IOBASE)))
#define ATA_ERROR (*((volatile unsigned char*)(ATA_IOBASE + 0x04)))
#define ATA_NSECTOR (*((volatile unsigned char*)(ATA_IOBASE + 0x08)))
#define ATA_SECTOR (*((volatile unsigned char*)(ATA_IOBASE + 0x0c)))
#define ATA_LCYL (*((volatile unsigned char*)(ATA_IOBASE + 0x10)))
#define ATA_HCYL (*((volatile unsigned char*)(ATA_IOBASE + 0x14)))
#define ATA_SELECT (*((volatile unsigned char*)(ATA_IOBASE + 0x18)))
#define ATA_COMMAND (*((volatile unsigned char*)(ATA_IOBASE + 0x1c)))
#define ATA_CONTROL (*((volatile unsigned char*)(0xc30003f8)))
#define STATUS_BSY 0x80
#define STATUS_RDY 0x40
#define STATUS_DF 0x20
#define STATUS_DRQ 0x08
#define STATUS_ERR 0x01
#define ERROR_ABRT 0x04
#define WRITE_PATTERN1 0xa5
#define WRITE_PATTERN2 0x5a
#define WRITE_PATTERN3 0xaa
#define WRITE_PATTERN4 0x55
#define READ_PATTERN1 0xa5
#define READ_PATTERN2 0x5a
#define READ_PATTERN3 0xaa
#define READ_PATTERN4 0x55
#define SET_REG(reg,val) reg = (val)
#define SET_16BITREG(reg,val) reg = (val)
#elif CONFIG_CPU == SH7034
#define SWAP_WORDS
@ -362,7 +399,7 @@ static void copy_read_sectors(unsigned char* buf, int wordcount)
{ /* loop compiles to 7 assembler instructions */
/* takes 12 clock cycles (2 pipeline stalls, 1 wait) */
#ifdef SWAP_WORDS
*wbuf = letoh16(ATA_DATA);
*wbuf = swap16(ATA_DATA);
#else
*wbuf = ATA_DATA;
#endif
@ -677,7 +714,7 @@ static void copy_write_sectors(const unsigned char* buf, int wordcount)
#ifdef SWAP_WORDS
/* loop compiles to 6 assembler instructions */
/* takes 10 clock cycles (2 pipeline stalls) */
SET_16BITREG(ATA_DATA, htole16(*wbuf));
SET_16BITREG(ATA_DATA, swap16(*wbuf));
#else
SET_16BITREG(ATA_DATA, *wbuf);
#endif
@ -1242,6 +1279,8 @@ void ata_enable(bool on)
or_l(0x00040000, &GPIO_FUNCTION);
#elif CONFIG_CPU == TCC730
#elif CONFIG_CPU == PP5020
#warning Implement ata_enable()
#endif
}
@ -1255,7 +1294,6 @@ static int identify(void)
DEBUGF("identify() - not RDY\n");
return -1;
}
SET_REG(ATA_COMMAND, CMD_IDENTIFY);
if (!wait_for_start_of_transfer())
@ -1267,10 +1305,11 @@ static int identify(void)
for (i=0; i<SECTOR_SIZE/2; i++) {
/* the IDENTIFY words are already swapped, so we need to treat
this info differently that normal sector data */
#ifdef SWAP_WORDS
identify_info[i] = ATA_DATA;
#if defined(ROCKBOX_IS_BIGENDIAN) && !defined(SWAP_WORDS)
#warning Swapping ATA identify data
identify_info[i] = swap16(ATA_DATA);
#else
identify_info[i] = letoh16(ATA_DATA);
identify_info[i] = ATA_DATA;
#endif
}
@ -1393,6 +1432,9 @@ int ata_init(void)
bool coldstart = (P1 & 0x80) == 0;
#elif CONFIG_CPU == MCF5249
bool coldstart = (GPIO_FUNCTION & 0x00080000) == 0;
#elif CONFIG_CPU == PP5020
bool coldstart = false;
#warning Implement coldstart variable
#else
bool coldstart = (PACR2 & 0x4000) != 0;
#endif
@ -1418,6 +1460,13 @@ int ata_init(void)
or_l(0x00080000, &GPIO_FUNCTION);
/* FYI: The IDECONFIGx registers are set by set_cpu_frequency() */
#elif CONFIG_CPU == PP5020
/* From ipod-ide.c:ipod_ide_register() */
outl(inl(0xc3000028) | (1 << 5), 0xc3000028);
outl(inl(0xc3000028) & ~0x10000000, 0xc3000028);
outl(0x10, 0xc3000000);
outl(0x80002150, 0xc3000004);
#endif
sleeping = false;

189
firmware/drivers/i2c-pp5020.c Normal file
View File

@ -0,0 +1,189 @@
/***************************************************************************
* __________ __ ___.
* Open \______ \ ____ ____ | | _\_ |__ _______ ___
* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
* \/ \/ \/ \/ \/
* $Id$
*
* Copyright (C) 2005 by Dave Chapman
*
* All files in this archive are subject to the GNU General Public License.
* See the file COPYING in the source tree root for full license agreement.
*
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
* KIND, either express or implied.
*
****************************************************************************/
#include "cpu.h"
#include "kernel.h"
#include "logf.h"
#include "system.h"
#include "i2c-pp5020.h"
#define I2C_DEVICE_1 ((volatile unsigned char *)0)
#define I2C_DEVICE_2 ((volatile unsigned char *)0)
/* Local functions definitions */
static int i2c_write_byte(int device, unsigned char data);
static int i2c_gen_start(int device);
static void i2c_gen_stop(int device);
static volatile unsigned char *i2c_get_addr(int device);
#define IPOD_I2C_BASE 0x7000c000
#define IPOD_I2C_CTRL (IPOD_I2C_BASE+0x00)
#define IPOD_I2C_ADDR (IPOD_I2C_BASE+0x04)
#define IPOD_I2C_DATA0 (IPOD_I2C_BASE+0x0c)
#define IPOD_I2C_DATA1 (IPOD_I2C_BASE+0x10)
#define IPOD_I2C_DATA2 (IPOD_I2C_BASE+0x14)
#define IPOD_I2C_DATA3 (IPOD_I2C_BASE+0x18)
#define IPOD_I2C_STATUS (IPOD_I2C_BASE+0x1c)
/* IPOD_I2C_CTRL bit definitions */
#define IPOD_I2C_SEND 0x80
/* IPOD_I2C_STATUS bit definitions */
#define IPOD_I2C_BUSY (1<<6)
#define POLL_TIMEOUT (HZ)
static int
ipod_i2c_wait_not_busy(void)
{
unsigned long timeout;
#if 0
timeout = jiffies + POLL_TIMEOUT;
while (time_before(jiffies, timeout)) {
if (!(inb(IPOD_I2C_STATUS) & IPOD_I2C_BUSY)) {
return 0;
}
yield();
}
return -ETIMEDOUT;
#endif
}
/* Public functions */
void i2c_init(void)
{
/* From ipodlinux */
outl(inl(0x6000600c) | 0x1000, 0x6000600c); /* enable 12 */
outl(inl(0x60006004) | 0x1000, 0x60006004); /* start reset 12 */
outl(inl(0x60006004) & ~0x1000, 0x60006004); /* end reset 12 */
outl(0x0, 0x600060a4);
outl(0x80 | (0 << 8), 0x600060a4);
i2c_readbyte(0x8, 0);
}
void i2c_close(void)
{
}
/**
* Writes bytes to the selected device.
*
* Returns number of bytes successfully send or -1 if START failed
*/
int i2c_write(int device, unsigned char *buf, int count)
{
/* From ipodlinux */
int data_addr;
int i;
if (count < 1 || count > 4) {
return -2;
}
if (ipod_i2c_wait_not_busy() < 0) {
return -1;
}
// clear top 15 bits, left shift 1
outb((device << 17) >> 16, IPOD_I2C_ADDR);
outb(inb(IPOD_I2C_CTRL) & ~0x20, IPOD_I2C_CTRL);
data_addr = IPOD_I2C_DATA0;
for ( i = 0; i < count; i++ ) {
outb(*buf++, data_addr);
data_addr += 4;
}
outb((inb(IPOD_I2C_CTRL) & ~0x26) | ((count-1) << 1), IPOD_I2C_CTRL);
outb(inb(IPOD_I2C_CTRL) | IPOD_I2C_SEND, IPOD_I2C_CTRL);
return 0x0;
return count;
}
/* Write a byte to the interface, returns 0 on success, -1 otherwise. */
int i2c_write_byte(int device, unsigned char data)
{
if (ipod_i2c_wait_not_busy() < 0) {
return -2;
}
// clear top 15 bits, left shift 1
outb((device << 17) >> 16, IPOD_I2C_ADDR);
outb(inb(IPOD_I2C_CTRL) & ~0x20, IPOD_I2C_CTRL);
outb(data, IPOD_I2C_DATA0);
outb((inb(IPOD_I2C_CTRL) & ~0x26), IPOD_I2C_CTRL);
outb(inb(IPOD_I2C_CTRL) | IPOD_I2C_SEND, IPOD_I2C_CTRL);
return 0;
}
/* Returns 0 on success, -1 on failure */
int i2c_gen_start(int device)
{
volatile unsigned char *regs = i2c_get_addr(device);
long count = 0;
/* Wait for bus to become free */
while ((regs[O_MBSR] & IBB) && (count < MAX_LOOP))
{
yield();
count++;
}
if (count >= MAX_LOOP)
return -1;
regs[O_MBCR] |= MSTA | MTX; /* Generate START */
return 0;
}
void i2c_gen_stop(int device)
{
volatile unsigned char *regs = i2c_get_addr(device);
regs[O_MBCR] &= ~MSTA; /* Clear MSTA to generate STOP */
}
volatile unsigned char *i2c_get_addr(int device)
{
if (device == 1)
return I2C_DEVICE_1;
return I2C_DEVICE_2;
}

1266
firmware/drivers/lcd-16bit.c Normal file
View File

File diff suppressed because it is too large Load Diff

9
firmware/drivers/power.c
View File

@ -73,6 +73,8 @@ void power_init(void)
#ifdef HAVE_SPDIF_POWER
spdif_power_enable(false);
#endif
#elif CONFIG_CPU == PP5020
#warning Implement power_init()
#else
#ifdef HAVE_POWEROFF_ON_PB5
PBCR2 &= ~0x0c00; /* GPIO for PB5 */
@ -163,6 +165,8 @@ void ide_power_enable(bool on)
and_l(~0x80000000, &GPIO_OUT);
else
or_l(0x80000000, &GPIO_OUT);
#elif CONFIG_CPU == PP5020
#warning Implement ide_power_enable()
#elif defined(GMINI_ARCH)
if(on)
P1 |= 0x08;
@ -213,6 +217,9 @@ bool ide_powered(void)
{
#if CONFIG_CPU == MCF5249
return (GPIO_OUT & 0x80000000)?false:true;
#elif CONFIG_CPU == PP5020
#warning Implement ide_powered()
return true;
#elif defined(GMINI_ARCH)
return (P1 & 0x08?true:false);
#else /* SH1 based archos */
@ -244,6 +251,8 @@ void power_off(void)
set_irq_level(HIGHEST_IRQ_LEVEL);
#if CONFIG_CPU == MCF5249
and_l(~0x00080000, &GPIO1_OUT);
#elif CONFIG_CPU == PP5020
#warning Implement power_off()
#elif defined(GMINI_ARCH)
P1 &= ~1;
P1CON &= ~1;

4
firmware/drivers/serial.c
View File

@ -27,8 +27,8 @@
#include "lcd.h"
#include "serial.h"
#if (CONFIG_CPU != MCF5249) && (CONFIG_CPU != TCC730)
/* FIX: this doesn't work on iRiver or Gmini yet */
#if (CONFIG_CPU != MCF5249) && (CONFIG_CPU != TCC730) && (CONFIG_CPU != PP5020)
/* FIX: this doesn't work on iRiver or Gmini or iPod yet */
#ifndef HAVE_MMC /* MMC takes serial port 1, so don't mess with it */

11
firmware/export/button.h
View File

@ -144,6 +144,17 @@ bool remote_button_hold(void);
#define BUTTON_DOWN 0x0020
#define BUTTON_MENU 0x0100
#elif (CONFIG_KEYPAD == IPOD_4G_PAD) || (CONFIG_KEYPAD == IPOD_NANO_PAD)
#warning Correct the IPOD definitions
#define BUTTON_ON 0x0001
#define BUTTON_OFF 0x0002
#define BUTTON_PLAY 0x0004
#define BUTTON_UP 0x0010
#define BUTTON_DOWN 0x0020
#define BUTTON_MENU 0x0100
#endif /* RECORDER/PLAYER/ONDIO/GMINI KEYPAD */
#endif /* _BUTTON_H_ */

87
firmware/export/config-ipodcolor.h Normal file
View File

@ -0,0 +1,87 @@
/* For Rolo and boot loader */
#define MODEL_NUMBER 3
/* define this if you have recording possibility */
/*#define HAVE_RECORDING 1*/
/* define this if you have a bitmap LCD display */
#define HAVE_LCD_BITMAP 1
/* define this if you have a colour LCD */
#define HAVE_LCD_COLOR 1
/* LCD dimensions */
#define LCD_WIDTH 220
#define LCD_HEIGHT 176
#define LCD_DEPTH 16 /* 65536 colours */
#define CONFIG_KEYPAD IPOD_4G_PAD
/* Define this if you do software codec */
#define CONFIG_CODEC SWCODEC
/* Define this if you have a software controlled poweroff */
#define HAVE_SW_POWEROFF
/* The number of bytes reserved for loadable codecs */
#define CODEC_SIZE 0x40000
/* The number of bytes reserved for loadable plugins */
#define PLUGIN_BUFFER_SIZE 0xC0000
//#define HAVE_UDA1380
#ifndef SIMULATOR
/* Define this if you have a PortalPlayer PP5020 */
#define CONFIG_CPU PP5020
/* Define this if you want to use the PP5020 i2c interface */
#define CONFIG_I2C I2C_PP5020
/* Type of mobile power */
//#define CONFIG_BATTERY BATT_LIPOL1300
#define BATTERY_SCALE_FACTOR 16665 /* FIX: this value is picked at random */
/* Define this if the platform can charge batteries */
//#define HAVE_CHARGING 1
/* define this if the hardware can be powered off while charging */
//#define HAVE_POWEROFF_WHILE_CHARGING
/* The start address index for ROM builds */
#define ROM_START 0x00000000
/* Define this for LCD backlight available */
#define CONFIG_BACKLIGHT BL_IPOD4G /* port controlled */
/* Define this to the CPU frequency */
#define CPU_FREQ 11289600
/* Define this if you have ATA power-off control */
#define HAVE_ATA_POWER_OFF
#define CONFIG_LCD LCD_IPODCOLOR
/* Offset ( in the firmware file's header ) to the file length */
#define FIRMWARE_OFFSET_FILE_LENGTH 0
/* Offset ( in the firmware file's header ) to the file CRC */
#define FIRMWARE_OFFSET_FILE_CRC 0
/* Offset ( in the firmware file's header ) to the real data */
#define FIRMWARE_OFFSET_FILE_DATA 8
#define USB_IPODSTYLE
/* Virtual LED (icon) */
#define CONFIG_LED LED_VIRTUAL
/* Define this if you have adjustable CPU frequency */
//#define HAVE_ADJUSTABLE_CPU_FREQ
#define BOOTFILE_EXT "ipodcolor"
#define BOOTFILE "rockbox." BOOTFILE_EXT
#endif

89
firmware/export/config-ipodnano.h Normal file
View File

@ -0,0 +1,89 @@
/* For Rolo and boot loader */
#define MODEL_NUMBER 4
/* define this if you have recording possibility */
/*#define HAVE_RECORDING 1*/
/* define this if you have a bitmap LCD display */
#define HAVE_LCD_BITMAP 1
/* define this if you have a colour LCD */
#define HAVE_LCD_COLOR 1
/* LCD dimensions */
#define LCD_WIDTH 176
#define LCD_HEIGHT 132
#define LCD_DEPTH 16 /* 65536 colours */
#define CONFIG_KEYPAD IPOD_NANO_PAD
/* Define this if you do software codec */
#define CONFIG_CODEC SWCODEC
/* Define this if you have a software controlled poweroff */
#define HAVE_SW_POWEROFF
/* The number of bytes reserved for loadable codecs */
#define CODEC_SIZE 0x40000
/* The number of bytes reserved for loadable plugins */
#define PLUGIN_BUFFER_SIZE 0xC0000
//#define HAVE_UDA1380
#ifndef SIMULATOR
/* The Nano actually has a PP5021 - but it's register compatible with
the 5020 so Rockbox doesn't care. */
/* Define this if you have a PortalPlayer PP5020 */
#define CONFIG_CPU PP5020
/* Define this if you want to use the PP5020 i2c interface */
#define CONFIG_I2C I2C_PP5020
/* Type of mobile power */
//#define CONFIG_BATTERY BATT_LIPOL1300
#define BATTERY_SCALE_FACTOR 16665 /* FIX: this value is picked at random */
/* Define this if the platform can charge batteries */
//#define HAVE_CHARGING 1
/* define this if the hardware can be powered off while charging */
//#define HAVE_POWEROFF_WHILE_CHARGING
/* The start address index for ROM builds */
#define ROM_START 0x00000000
/* Define this for LCD backlight available */
#define CONFIG_BACKLIGHT BL_IPODNANO /* port controlled */
/* Define this to the CPU frequency */
#define CPU_FREQ 11289600
/* Define this if you have ATA power-off control */
#define HAVE_ATA_POWER_OFF
#define CONFIG_LCD LCD_IPODCOLOR
/* Offset ( in the firmware file's header ) to the file length */
#define FIRMWARE_OFFSET_FILE_LENGTH 0
/* Offset ( in the firmware file's header ) to the file CRC */
#define FIRMWARE_OFFSET_FILE_CRC 0
/* Offset ( in the firmware file's header ) to the real data */
#define FIRMWARE_OFFSET_FILE_DATA 8
#define USB_IPODSTYLE
/* Virtual LED (icon) */
#define CONFIG_LED LED_VIRTUAL
/* Define this if you have adjustable CPU frequency */
//#define HAVE_ADJUSTABLE_CPU_FREQ
#define BOOTFILE_EXT "ipod"
#define BOOTFILE "rockbox." BOOTFILE_EXT
#endif

35
firmware/export/config.h
View File

@ -39,6 +39,8 @@
#define MCF5249 5249
#define MCF5250 5250
#define TCC730 730 /* lacking a proper abbrivation */
#define PP5002 5002
#define PP5020 5020
/* CONFIG_KEYPAD */
#define PLAYER_PAD 0
@ -48,6 +50,8 @@
#define GMINI100_PAD 4
#define IRIVER_H300_PAD 5
#define IAUDIO_X5_PAD 6
#define IPOD_4G_PAD 7
#define IPOD_NANO_PAD 8
/* CONFIG_REMOTE_KEYPAD */
#define H100_REMOTE 1
@ -61,14 +65,16 @@
#define BATT_LIPOL1300 1300 /* the type used in iRiver h1x0 models */
/* CONFIG_LCD */
#define LCD_GMINI100 0
#define LCD_SSD1815 1 /* as used by Archos Recorders and Ondios */
#define LCD_SSD1801 2 /* as used by Archos Player/Studio */
#define LCD_S1D15E06 3 /* as used by iRiver H100 series */
#define LCD_H300 4 /* as used by iRiver H300 series, exact model name is
unknown at the time of this writing */
#define LCD_X5 5 /* as used by iAudio X5 series, exact model name is
#define LCD_GMINI100 0
#define LCD_SSD1815 1 /* as used by Archos Recorders and Ondios */
#define LCD_SSD1801 2 /* as used by Archos Player/Studio */
#define LCD_S1D15E06 3 /* as used by iRiver H100 series */
#define LCD_H300 4 /* as used by iRiver H300 series, exact model name is
unknown at the time of this writing */
#define LCD_X5 5 /* as used by iAudio X5 series, exact model name is
unknown at the time of this writing */
#define LCD_IPODCOLOR 6 /* as used by iPod Color/Photo */
#define LCD_IPODNANO 7 /* as used by iPod Nano */
/* CONFIG_BACKLIGHT */
#define BL_PA14_LO 0 /* Player, PA14 low active */
@ -76,12 +82,15 @@
#define BL_PA14_HI 2 /* Ondio, PA14 high active */
#define BL_IRIVER 3 /* IRiver GPIO */
#define BL_GMINI 4 /* Archos GMini */
#define BL_IPOD4G 5 /* Apple iPod 4G */
#define BL_IPODNANO 6 /* Apple iPod Nano */
/* CONFIG_I2C */
#define I2C_PLAYREC 0 /* Archos Player/Recorder style */
#define I2C_ONDIO 1 /* Ondio style */
#define I2C_GMINI 2 /* Gmini style */
#define I2C_COLDFIRE 3 /* Coldfire style */
#define I2C_PP5020 4 /* PP5020 style */
/* CONFIG_LED */
#define LED_REAL 1 /* SW controlled LED (Archos recorders, player, Gmini) */
@ -113,6 +122,10 @@
#include "config-gminisp.h"
#elif defined(IAUDIO_X5)
#include "config-iaudiox5.h"
#elif defined(IPOD_COLOR)
#include "config-ipodcolor.h"
#elif defined(IPOD_NANO)
#include "config-ipodnano.h"
#else
/* no known platform */
#endif
@ -129,6 +142,11 @@
#define CPU_COLDFIRE
#endif
/* define for all cpus from ARM family */
#if (CONFIG_CPU == PP5020)
#define CPU_ARM
#endif
#ifndef CODEC_SIZE
#define CODEC_SIZE 0
#endif
@ -137,7 +155,8 @@
#if !defined(SIMULATOR) && /* Not for simulators */ \
(((CONFIG_CPU == SH7034) && !defined(PLUGIN)) || /* SH1 archos: core only */ \
(CONFIG_CPU == MCF5249) || /* Coldfire: core, plugins, codecs */ \
(CONFIG_CPU == TCC730)) /* CalmRISC16: core, (plugins, codecs) */
(CONFIG_CPU == PP5020) || /* iPod: core, plugins, codecs */ \
(CONFIG_CPU == TCC730)) /* CalmRISC16: core, (plugins, codecs) */
#define ICODE_ATTR __attribute__ ((section(".icode")))
#define ICONST_ATTR __attribute__ ((section(".irodata")))
#define IDATA_ATTR __attribute__ ((section(".idata")))

66
firmware/export/i2c-pp5020.h Normal file
View File

@ -0,0 +1,66 @@
/***************************************************************************
* __________ __ ___.
* Open \______ \ ____ ____ | | _\_ |__ _______ ___
* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
* \/ \/ \/ \/ \/
* $Id$
*
* Copyright (C) 2002 by Linus Nielsen Feltzing
*
* All files in this archive are subject to the GNU General Public License.
* See the file COPYING in the source tree root for full license agreement.
*
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
* KIND, either express or implied.
*
****************************************************************************/
/*
* Driver for ARM i2c driver
*
*
*/
#ifndef _I2C_ARM_H
#define _I2C_ARM_H
#warning Implement: i2c-pp5020.h
void i2c_init(void);
int i2c_write(int device, unsigned char *buf, int count);
void i2c_close(void);
#define MAX_LOOP 0x100 /* TODO: select a better value */
/* PLLCR control */
#define QSPISEL (1 << 11) /* Selects QSPI or I2C interface */
/* Offsets to I2C registers from base address */
#define O_MADR 0x00 /* Slave Address */
#define O_MFDR 0x04 /* Frequency divider */
#define O_MBCR 0x08 /* Control register */
#define O_MBSR 0x0c /* Status register */
#define O_MBDR 0x10 /* Data register */
/* MBSR - Status register */
#define ICF (1 << 7) /* Transfer Complete */
#define IAAS (1 << 6) /* Addressed As Alave */
#define IBB (1 << 5) /* Bus Busy */
#define IAL (1 << 4) /* Arbitration Lost */
#define SRW (1 << 2) /* Slave R/W */
#define IFF (1 << 1) /* I2C Interrupt */
#define RXAK (1 << 0) /* No Ack bit */
/* MBCR - Control register */
#define IEN (1 << 7) /* I2C Enable */
#define IIEN (1 << 6) /* Interrupt Enable */
#define MSTA (1 << 5) /* Master/Slave select */
#define MTX (1 << 4) /* Transmit/Receive */
#define TXAK (1 << 3) /* Transfer ACK */
#define RSTA (1 << 2) /* Restart.. */
#endif

6
firmware/export/kernel.h
View File

@ -20,6 +20,7 @@
#define _KERNEL_H_
#include <stdbool.h>
#include "config.h"
/* wrap-safe macros for tick comparison */
#define TIME_AFTER(a,b) ((long)(b) - (long)(a) < 0)
@ -65,7 +66,12 @@ struct mutex
};
/* global tick variable */
#if (CONFIG_CPU==PP5020)
/* A temporary hack until timer interrupt is enabled - use the RTC */
#define current_tick ((*((volatile unsigned long*)0x60005010))/10000)
#else
extern long current_tick;
#endif
#ifdef SIMULATOR
#define sleep(x) sim_sleep(x)

12
firmware/export/lcd.h
View File

@ -122,14 +122,24 @@ extern void lcd_jump_scroll_delay(int ms);
/* Low-level drawing function types */
typedef void lcd_pixelfunc_type(int x, int y);
#if LCD_DEPTH==16
typedef void lcd_blockfunc_type(unsigned char *address, unsigned mask, unsigned bits);
#else
typedef void lcd_blockfunc_type(unsigned char *address, unsigned mask, unsigned bits);
#endif
#ifdef HAVE_LCD_BITMAP
#ifdef HAVE_LCD_COLOR
#if LCD_DEPTH == 16
#define LCD_MAX_RED ((1 << 5) - 1)
#define LCD_MAX_GREEN ((1 << 6) - 1)
#define LCD_MAX_BLUE ((1 << 5) - 1)
#else
#define LCD_MAX_RED ((1 << (LCD_DEPTH/3)) - 1)
#define LCD_MAX_GREEN ((1 << (LCD_DEPTH/3)) - 1)
#define LCD_MAX_BLUE ((1 << (LCD_DEPTH/3)) - 1)
#endif
struct rgb {
unsigned char red;
unsigned char green;
@ -148,6 +158,8 @@ struct rgb {
extern unsigned char lcd_framebuffer[LCD_HEIGHT/8][LCD_WIDTH];
#elif LCD_DEPTH == 2
extern unsigned char lcd_framebuffer[LCD_HEIGHT/4][LCD_WIDTH];
#elif LCD_DEPTH == 16
extern unsigned char lcd_framebuffer[LCD_HEIGHT][LCD_WIDTH*2];
#endif
extern void lcd_set_invert_display(bool yesno);

44
firmware/export/system.h
View File

@ -29,6 +29,13 @@ extern void system_init(void);
extern long cpu_frequency;
#if CONFIG_CPU==PP5020
#define inl(a) (*(volatile unsigned long *) (a))
#define outl(a,b) (*(volatile unsigned long *) (b) = (a))
#define inb(a) (*(volatile unsigned char *) (a))
#define outb(a,b) (*(volatile unsigned char *) (b) = (a))
#endif
#ifdef HAVE_ADJUSTABLE_CPU_FREQ
#define FREQ cpu_frequency
void set_cpu_frequency(long frequency);
@ -285,6 +292,43 @@ static inline void invalidate_icache(void)
#define CPUFREQ_MAX_MULT 11
#define CPUFREQ_MAX (CPUFREQ_MAX_MULT * CPU_FREQ)
#elif CONFIG_CPU == PP5020
#warning Implement set_irq_level and check CPU frequencies
#define CPUFREQ_DEFAULT CPU_FREQ
#define CPUFREQ_NORMAL 37500000
#define CPUFREQ_MAX 75000000
static inline unsigned short swap16(unsigned short value)
/*
result[15..8] = value[ 7..0];
result[ 7..0] = value[15..8];
*/
{
return (value >> 8) | (value << 8);
}
static inline unsigned long swap32(unsigned long value)
/*
result[31..24] = value[ 7.. 0];
result[23..16] = value[15.. 8];
result[15.. 8] = value[23..16];
result[ 7.. 0] = value[31..24];
*/
{
unsigned long hi = swap16(value >> 16);
unsigned long lo = swap16(value & 0xffff);
return (lo << 16) | hi;
}
#define HIGHEST_IRQ_LEVEL (1)
static inline int set_irq_level(int level)
{
int result=level;
return result;
}
#elif CONFIG_CPU == TCC730
extern int smsc_version(void);

13
firmware/kernel.c
View File

@ -25,7 +25,9 @@
#include "system.h"
#include "panic.h"
#if (CONFIG_CPU != PP5020)
long current_tick = 0;
#endif
static void (*tick_funcs[MAX_NUM_TICK_TASKS])(void);
@ -65,6 +67,11 @@ void sleep(int ticks)
void yield(void)
{
#if CONFIG_CPU == PP5020
/* Threading not yet implemented */
#warning Enable yield()
return;
#endif
switch_thread();
wake_up_thread();
}
@ -315,6 +322,12 @@ void tick_start(unsigned int interval_in_ms)
IMR0 |= (1<<2);
}
#elif CONFIG_CPU == PP5020
void tick_start(unsigned int interval_in_ms) {
#warning Implement tick_start
}
#endif
int tick_add_task(void (*f)(void))

2
firmware/rolo.c
View File

@ -143,7 +143,7 @@ int rolo_load(const char* filename)
lcd_update();
set_irq_level(HIGHEST_IRQ_LEVEL);
#else
#elif CONFIG_CPU == SH7034
/* Read file length from header and compare to real file length */
lseek(fd, FIRMWARE_OFFSET_FILE_LENGTH, SEEK_SET);
if(read(fd, &file_length, 4) != 4) {

13
firmware/system.c
View File

@ -1094,5 +1094,18 @@ int system_memory_guard(int newmode)
return oldmode;
}
#elif CONFIG_CPU==PP5020
#warning TODO: Implement system.c
void system_init(void) {
}
void system_reboot(void) {
}
#endif /* CONFIG_CPU */

26
firmware/thread.c
View File

@ -41,6 +41,14 @@ struct regs
void *pr; /* Procedure register */
void *start; /* Thread start address, or NULL when started */
};
#elif CONFIG_CPU == PP5020
#warning TODO: define struct regs
struct regs
{
void *sp; /* Stack pointer (a15) */
void *start; /* Thread start address */
int started; /* 0 when not started */
};
#elif CONFIG_CPU == TCC730
struct regs
{
@ -70,7 +78,21 @@ void switch_thread(void) ICODE_ATTR;
static inline void store_context(void* addr) __attribute__ ((always_inline));
static inline void load_context(const void* addr) __attribute__ ((always_inline));
#ifdef CPU_COLDFIRE
#if CONFIG_CPU == PP5020
#warning TODO: Implement store_context and load_context
static inline void store_context(void* addr)
{
}
static inline void load_context(const void* addr)
{
}
#elif defined(CPU_COLDFIRE)
/*---------------------------------------------------------------------------
* Store non-volatile context.
*---------------------------------------------------------------------------
@ -341,6 +363,8 @@ void init_threads(void)
thread_contexts[0].start = 0; /* thread 0 already running */
#elif CONFIG_CPU == TCC730
thread_contexts[0].started = 1;
#elif CONFIG_CPU == PP5020
thread_contexts[0].start = 0; /* thread 0 already running */
#endif
num_sleepers = 0;
}

4
firmware/usb.c
View File

@ -145,6 +145,10 @@ static void usb_enable(bool on)
and_l(~0x01000000, &GPIO_OUT);
}
#elif defined(USB_IPODSTYLE)
#warning Implement USB_IPODSTYLE
#else
#ifdef HAVE_LCD_BITMAP
if(read_hw_mask() & USB_ACTIVE_HIGH)