rk27load - fix indentation
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@30460 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Marcin Bukat
parent
6d5671a8d8
commit
77a82ad56a
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@ -2,41 +2,41 @@
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.global start
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start:
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msr cpsr_c, #0xd3 /* enter supervisor mode, disable IRQ/FIQ */
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msr cpsr_c,#0xd3 /* enter supervisor mode, disable IRQ/FIQ */
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pll_setup:
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mov r0, #0x18000000
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add r0, r0, #0x1c000
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mov r0,#0x18000000
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add r0,r0,#0x1c000
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/* setup ARM core freq = 200MHz */
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/* AHB bus freq (HCLK) = 100MHz */
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/* APB bus freq (PCLK) = 50MHz */
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ldr r1, [r0,#0x14] /* SCU_DIVCON1 */
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orr r1, #9 /* ARM slow mode, HCLK:PCLK = 2:1 */
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str r1, [r0,#0x14]
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ldr r1,[r0,#0x14] /* SCU_DIVCON1 */
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orr r1,#9 /* ARM slow mode, HCLK:PCLK = 2:1 */
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str r1,[r0,#0x14]
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ldr r1,=0x01970c70 /* (1<<24) | (1<<23) | (23<<16) | (199<<4) */
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str r1, [r0,#0x08]
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ldr r1,=0x01970c70 /* (1<<24) | (1<<23) | (23<<16) | (199<<4) */
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str r1,[r0,#0x08]
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ldr r2,=0x40000
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ldr r2,=0x40000
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1:
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ldr r1, [r0,#0x2c] /* SCU_STATUS */
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tst r1, #1 /* ARM pll lock */
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bne 1f
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subs r2, #1
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bne 1b
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ldr r1,[r0,#0x2c] /* SCU_STATUS */
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tst r1,#1 /* ARM pll lock */
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bne 1f
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subs r2,#1
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bne 1b
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1:
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ldr r1, [r0,#0x14] /* SCU_DIVCON1 */
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bic r1, #5 /* leave ARM slow mode, ARMclk:HCLK = 2:1 */
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str r1, [r0,#0x14]
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ldr r1,[r0,#0x14] /* SCU_DIVCON1 */
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bic r1,#5 /* leave ARM slow mode, ARMclk:HCLK = 2:1 */
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str r1,[r0,#0x14]
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sdram_config:
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add r0, r0, #0x94000 /* SDRAM base */
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add r0,r0, #0x94000 /* SDRAM base */
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mov r1, #1
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str r1, [r0,#0x10c] /* MCSDR_BASIC Round-robin, SDRAM width 16bits */
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mov r1,#1
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str r1,[r0,#0x10c] /* MCSDR_BASIC Round-robin, SDRAM width 16bits */
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add r1, #0x10
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str r1, [r0,#0x108] /* MCSDR_ADDCFG 12 bits row/9 bits col addr */
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add r1,#0x10
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str r1,[r0,#0x108] /* MCSDR_ADDCFG 12 bits row/9 bits col addr */
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mov pc, lr /* we are done, return to bootrom code */
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mov pc,lr /* we are done, return to bootrom code */
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@ -1,55 +1,56 @@
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//
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// startup code
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//
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//
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/*
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* startup code
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*
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*/
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#define PSR_MODE 0x0000001f
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#define PSR_USR_MODE 0x00000010
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#define PSR_IRQ_MODE 0x00000012
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#define PSR_SVC_MODE 0x00000013
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#define PSR_MODE 0x0000001f
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#define PSR_USR_MODE 0x00000010
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#define PSR_IRQ_MODE 0x00000012
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#define PSR_SVC_MODE 0x00000013
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#define PSR_INT_MASK 0x000000c0
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#define PSR_FIQ_DIS 0x00000040
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#define PSR_IRQ_DIS 0x00000080
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#define PSR_INT_MASK 0x000000c0
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#define PSR_FIQ_DIS 0x00000040
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#define PSR_IRQ_DIS 0x00000080
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.section .init.text,"ax",%progbits
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.global start
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.extern _interrupt_disable
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// -----------------------------------------------------
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// startup code (setup stacks, branch to main)
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// -----------------------------------------------------
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/* -----------------------------------------------------
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* startup code (setup stacks, branch to main)
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* -----------------------------------------------------
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*/
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start:
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// setup IRQ stack
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mov r0, #(PSR_IRQ_MODE|PSR_FIQ_DIS|PSR_IRQ_DIS)
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msr cpsr, r0
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ldr sp,=irqstackend
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/* setup IRQ stack */
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mov r0,#(PSR_IRQ_MODE|PSR_FIQ_DIS|PSR_IRQ_DIS)
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msr cpsr,r0
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ldr sp,=irqstackend
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// setup SVC stack
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mov r0, #(PSR_SVC_MODE|PSR_FIQ_DIS|PSR_IRQ_DIS)
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msr cpsr, r0
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ldr sp,=stackend
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/* setup SVC stack */
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mov r0,#(PSR_SVC_MODE|PSR_FIQ_DIS|PSR_IRQ_DIS)
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msr cpsr,r0
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ldr sp,=stackend
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// disbale interrupts
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mrs r0, cpsr
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orr r0, r0, #0xc0
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msr cpsr_c, r0
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/* disbale interrupts */
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mrs r0,cpsr
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orr r0,r0,#0xc0
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msr cpsr_c, r0
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// remap
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mov r0, #0x18000000
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add r0, r0, #0x1C000
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ldr r1,=0xdeadbeef
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str r1, [r0, #4]
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/* remap */
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mov r0,#0x18000000
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add r0,r0,#0x1C000
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ldr r1,=0xdeadbeef
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str r1,[r0,#4]
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// relocate itself
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ldr r0,=_relocstart
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ldr r1,=_relocend
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ldr r2,=0x0
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/* relocate itself */
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ldr r0,=_relocstart
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ldr r1,=_relocend
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ldr r2,=0x0
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1:
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cmp r1,r0
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ldrhi r3,[r0],#4
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strhi r3,[r2],#4
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bhi 1b
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// continue running in SVC (supervisor mode)
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ldr pc,=0x0
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cmp r1,r0
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ldrhi r3,[r0],#4
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strhi r3,[r2],#4
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bhi 1b
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/* continue running in SVC (supervisor mode) */
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ldr pc,=0x0
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@ -1,103 +1,102 @@
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.section .text
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.align 4
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.section .text
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.align 4
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.global irq_handler
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#define BUFF_ADDR 0x60800000
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.global irq_handler
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#define BUFF_ADDR 0x60800000
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irq_handler:
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stmfd sp!, {r0-r7, ip, lr}
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stmfd sp!,{r0-r7,ip,lr}
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// get interrupt number
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mov r4, #0x18000000
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add r4, r4, #0x80000
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ldr r5, [r4, #0x104]
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and r5, r5, #0x1f
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cmp r5, #0x10 // UDC interrupt
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/* get interrupt number */
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mov r4,#0x18000000
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add r4,r4,#0x80000
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ldr r5,[r4,#0x104]
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and r5,r5,#0x1f
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cmp r5,#0x10 /* UDC interrupt */
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bleq udc_irq
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bleq udc_irq
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// clear pending interrupt
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mov r3, #1
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mov r2, r3, LSL r5
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str r2, [r4, #0x118]
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/* clear pending interrupt */
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mov r3,#1
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mov r2,r3,LSL r5
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str r2,[r4,#0x118]
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ldmfd sp!, {r0-r7, ip, lr}
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subs pc, lr, #4
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ldmfd sp!,{r0-r7,ip,lr}
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subs pc,lr,#4
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udc_irq:
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stmfd sp!, {r4-r8, lr}
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stmfd sp!,{r4-r8,lr}
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// handle usb interrupt
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ldr r4,=0x180A0000
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ldr r5, [r4, #0x18] // UDC_INTFLAG
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/* handle usb interrupt */
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ldr r4,=0x180A0000
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ldr r5,[r4,#0x18] /* UDC_INTFLAG */
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// ep0 in intr
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tst r5, #0x04
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beq bulk_recv_intr
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/* ep0 in intr */
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tst r5,#0x04
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beq bulk_recv_intr
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ep0:
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ldr r5,[r4,#0x40]
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mov r5,r5,lsr #10
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mov r5,r5,lsl #10 /* clear lower 10 bits in TX0STAT */
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str r5,[r4,#0x40]
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// write_reg32(UDC_TX0STAT, read_reg32(UDC_TX0STAT) & ~0x7FF);
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ldr r5, [r4, #0x40]
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mov r5, r5, lsr #10
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mov r5, r5, lsl #10 // clear clower 10 bits
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str r5, [r4, #0x40]
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/* set buffer addres in UDC_DMA0LM_OADDR */
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mov r5,#0x60000000
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str r5,[r4, #0x3c]
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// write_reg32(UDC_DMA0LM_OADDR, (uint32_t)(state.ctrlep_data));
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mov r5, #0x60000000
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str r5, [r4, #0x3c]
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/* write DMA_START in UDC_DMA0CTLO */
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mov r5,#1
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str r5,[r4,#0x38]
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// write_reg32(UDC_DMA0CTLO, read_reg32(UDC_DMA0CTLO) | ENP_DMA_START);
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mov r5, #1
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str r5, [r4, #0x38]
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ldmfd sp!,{r4-r8,pc}
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ldmfd sp!, {r4-r8, pc}
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// bulk out interrupt
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/* bulk out interrupt */
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bulk_recv_intr:
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tst r5, #0x100
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ldmeqfd sp!, {r4-r8, pc}
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tst r5,#0x100
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ldmeqfd sp!,{r4-r8,pc}
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// read UDC_RX1STAT
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ldr r5, [r4, #0x54]
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mov r5, r5, lsl #21
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mov r5, r5, lsr #21 // r5 = length
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/* read UDC_RX1STAT */
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ldr r5,[r4,#0x54]
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mov r5,r5,lsl #21
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mov r5,r5,lsr #21 /* r5 = length */
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ldr r6,=usb_sz
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ldr r6, [r6]
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ldr r7, [r6] // r7 = total_code_length expected
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ldr r6,=usb_sz
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ldr r6,[r6]
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ldr r7,[r6] /* r7 = total_code_length expected */
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subs r7, r7, r5
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bne usb_bulk_out1_recv
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subs r7,r7,r5
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bne usb_bulk_out1_recv
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// copy from buff to the begining of the ram
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ldr r0,=BUFF_ADDR
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ldr r1,[r0,#-4] // size
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/* copy from buff to the begining of the ram */
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ldr r0,=BUFF_ADDR
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ldr r1,[r0,#-4] /* size */
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ldr r1,=0x800000 // buffer size
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ldr r1,=0x800000 /* buffer size */
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add r1,r1,r0 // end address
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ldr r2,=0x60000000 // destination
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add r1,r1,r0 /* end address */
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ldr r2,=0x60000000 /* destination */
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1:
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cmp r1,r0
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ldrhi r3,[r0],#4
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strhi r3,[r2],#4
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bhi 1b
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cmp r1,r0
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ldrhi r3,[r0],#4
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strhi r3,[r2],#4
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bhi 1b
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// execute user code
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ldr r0,=0x60000000
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bx r0 // jump to 0x60000000
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/* execute user code */
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ldr r0,=0x60000000
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bx r0 /* jump to 0x60000000 */
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usb_bulk_out1_recv:
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str r7, [r6] // size = size - received
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str r7,[r6] /* size = size - received */
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ldr r6,=usb_write_addr
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ldr r7, [r6]
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ldr r6,=usb_write_addr
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ldr r7,[r6]
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add r7, r7, r5
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str r7, [r6] // usb_write_addr += length
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add r7,r7,r5
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str r7,[r6] /* usb_write_addr += length */
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str r7, [r4, #0x60] // DMA1LM_OADDR = usb_write_addr
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str r7,[r4,#0x60] /* DMA1LM_OADDR = usb_write_addr */
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mov r5, #1
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str r5, [r4, #0x5c] // DMA1_CTL0 = ENP_DMA_START
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mov r5,#1
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str r5,[r4,#0x5c] /* DMA1_CTL0 = ENP_DMA_START */
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ldmfd sp!, {r4-r8, pc}
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ldmfd sp!,{r4-r8,pc}
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@ -1,89 +1,92 @@
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.section .text
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.align 4
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.section .text
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.align 4
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.arm
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.global main
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.global _interrupt_disable
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.global _interrupt_enable
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.arm
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.global usb_write_addr
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.global usb_sz
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.global main
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.global _interrupt_disable
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.global _interrupt_enable
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#define BUFF_ADDR 0x60800000
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.global usb_write_addr
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.global usb_sz
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// -----------------------------------------------------
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// vector table
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// -----------------------------------------------------
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ldr pc, =main
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ldr pc, =main
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ldr pc, =main
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ldr pc, =main
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ldr pc, =main
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ldr pc, =main
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ldr pc, =irq_handler
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ldr pc, =main
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#define BUFF_ADDR 0x60800000
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// -----------------------------------------------------
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// main
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// -----------------------------------------------------
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/* -----------------------------------------------------
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* vector table
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* -----------------------------------------------------
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*/
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ldr pc,=main
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ldr pc,=main
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ldr pc,=main
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ldr pc,=main
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ldr pc,=main
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ldr pc,=main
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ldr pc,=irq_handler
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ldr pc,=main
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/* -----------------------------------------------------
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* main
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* -----------------------------------------------------
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*/
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main:
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// turn on usb interrupts
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mov r0, #0x18000000
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add r0, r0, #0x80000
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ldr r1, [r0, #0x10c]
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orr r1, r1, #0x10000
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str r1, [r0, #0x10c]
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/* turn on usb interrupts */
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mov r0,#0x18000000
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add r0,r0,#0x80000
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ldr r1,[r0,#0x10c]
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orr r1,r1,#0x10000
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str r1,[r0,#0x10c]
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// enable usb-bulk
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add r0, r0, #0x20000 // R0 = 0x180A0000 (UDC_BASE)
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/* enable usb-bulk */
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add r0,r0,#0x20000 /* R0 = 0x180A0000 (UDC_BASE) */
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// enable EP1, write_reg32(UDC_RX1CON, (0x1 << 8) | RxACKINTEN | RxEPEN);
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mov r1, #0x190 // bits 8,7,4 -> 0x190
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str r1, [r0, #0x58]
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// setup receive buffer (must be aligned on dword boundary)
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ldr r1,=usb_write_addr // write_reg32(UDC_DMA1LM_OADDR, (uint32_t)rx_buff);
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ldr r1, [r1]
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str r1, [r0, #0x60] // UDC_DMA1LM_OADDR = usb_write_addr
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// write_reg32(UDC_DMA1CTRLO, read_reg32(UDC_DMA1CTRLO) | ENP_DMA_START);
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ldr r1, [r0, #0x5c]
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orr r1, r1, #2
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str r1, [r0, #0x5c]
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/* enable EP1 */
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mov r1,#0x190 /* bits 8,7,4 -> 0x190 */
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str r1,[r0,#0x58]
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/* setup receive buffer (must be aligned on dword boundary) */
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ldr r1,=usb_write_addr
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ldr r1,[r1]
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str r1,[r0, #0x60] /* UDC_DMA1LM_OADDR = usb_write_addr */
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/* write DMA_START in UDC_DMA1CTRLO */
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ldr r1,[r0,#0x5c]
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orr r1,r1,#2
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str r1,[r0,#0x5c]
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// enable bulk_out1 interrupt
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ldr r1, [r0, #0x14] // UDC_ENINT
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orr r1, r1, #0x100 // EN_BOUT1_INTR
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str r1, [r0, #0x14]
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/* enable bulk_out1 interrupt */
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ldr r1,[r0,#0x14] /* UDC_ENINT */
|
||||
orr r1,r1,#0x100 /* EN_BOUT1_INTR */
|
||||
str r1,[r0,#0x14]
|
||||
|
||||
bl _interrupt_enable
|
||||
bl _interrupt_enable
|
||||
idle:
|
||||
b idle
|
||||
b idle
|
||||
|
||||
// -----------------------------------------------------
|
||||
// _interrupt_enable - enables interrupts
|
||||
// -----------------------------------------------------
|
||||
/* -----------------------------------------------------
|
||||
* _interrupt_enable - enables interrupts
|
||||
* -----------------------------------------------------
|
||||
*/
|
||||
_interrupt_enable:
|
||||
mrs r0, cpsr
|
||||
bic r0, r0, #0x80
|
||||
msr cpsr_c, r0
|
||||
mov pc, lr
|
||||
mrs r0,cpsr
|
||||
bic r0,r0,#0x80
|
||||
msr cpsr_c,r0
|
||||
mov pc,lr
|
||||
|
||||
// -----------------------------------------------------
|
||||
// _interrupt_disable - disables interrupts
|
||||
// -----------------------------------------------------
|
||||
/* -----------------------------------------------------
|
||||
* _interrupt_disable - disables interrupts
|
||||
* -----------------------------------------------------
|
||||
*/
|
||||
_interrupt_disable:
|
||||
mrs r0, cpsr
|
||||
orr r0, r0, #0xc0
|
||||
msr cpsr_c, r0
|
||||
mov pc, lr
|
||||
mrs r0,cpsr
|
||||
orr r0,r0,#0xc0
|
||||
msr cpsr_c,r0
|
||||
mov pc,lr
|
||||
|
||||
|
||||
.section .data
|
||||
.section .data
|
||||
usb_write_addr:
|
||||
.word (BUFF_ADDR-4)
|
||||
.word (BUFF_ADDR-4)
|
||||
|
||||
usb_sz:
|
||||
.word (BUFF_ADDR-4)
|
||||
.word (BUFF_ADDR-4)
|
||||
|
|
|
|||
Loading…
Reference in New Issue