DM320: Update boot linker script (right now it is linked against flash). Include board initialization for M:Robe 500.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@29225 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Karl Kurbjun
parent
9241210050
commit
9a8ff746f2
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@ -1003,6 +1003,7 @@ target/arm/ata-as-arm.S
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target/arm/lcd-as-memframe.S
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#endif
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target/arm/mmu-arm.S
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target/arm/tms320dm320/mrobe-500/crt0-board.S
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target/arm/tms320dm320/mrobe-500/adc-mr500.c
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target/arm/tms320dm320/mrobe-500/ata-mr500.c
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target/arm/tms320dm320/mrobe-500/backlight-mr500.c
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@ -1,6 +1,6 @@
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#include "config.h"
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ENTRY(start)
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ENTRY(_vectors)
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OUTPUT_FORMAT(elf32-littlearm)
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OUTPUT_ARCH(arm)
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@ -27,15 +27,19 @@ STARTUP(target/arm/tms320dm320/crt0.o)
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*/
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#define LCD_TTB_AREA 0x100000*((LCD_BUFFER_SIZE>>19)+1)
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#define BOOT_OFFSET 0x1000000
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/* Bootloader only uses/knows about the upper 32 M */
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#define DRAMORIG 0x02900000
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#define DRAMSIZE (MEMORYSIZE * 0x80000)
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#define DRAMSIZE (MEMORYSIZE * 0x100000) - BOOT_OFFSET
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#define DRAMORIG (0x00900000+BOOT_OFFSET) /* actually it's 0x00900000 */
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#define IRAMORIG 0x00000000
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#define IRAMSIZE 0x4000
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#define FLASHORIG 0x00100000
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#define FLASHSIZE 8M
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#define FLASHSIZE 0x00800000
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PRO_STACK_SIZE = 0x2000;
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IRQ_STACK_SIZE = 0x400;
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FIQ_STACK_SIZE = 0x400;
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/* End of the audio buffer, where the codec buffer starts */
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#define TTB_BEGIN (DRAMORIG + DRAMSIZE - LCD_TTB_AREA)
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@ -49,98 +53,121 @@ MEMORY
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SECTIONS
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{
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. = DRAMORIG;
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/* Set up variables needed for memory initialization */
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_sdram_start = DRAMORIG;
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_sdram_sizem = (DRAMSIZE / 0x100000);
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.text : {
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loadaddress = .;
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_loadaddress = .;
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*(.init.text)
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*(.text*)
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*(.glue_7)
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*(.glue_7t)
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. = ALIGN(0x4);
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} > DRAM
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_flash_start = FLASHORIG;
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_flash_sizem = (FLASHSIZE / 0x100000);
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.rodata :
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{
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*(.rodata) /* problems without this, dunno why */
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*(.rodata*)
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*(.rodata.str1.1)
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*(.rodata.str1.4)
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. = ALIGN(0x4);
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/* Pseudo-allocate the copies of the data sections */
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_datacopy = .;
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} > DRAM
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.data : {
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*(.data*)
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. = ALIGN(0x4);
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_dataend = . ;
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} > DRAM
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.vectors IRAMORIG :
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.vectors :
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{
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_vectorsstart = .;
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KEEP(*(.resetvectors));
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*(.resetvectors);
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KEEP(*(.vectors));
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*(.vectors);
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KEEP(*(.vectors))
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_vectorsend = .;
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} > IRAM AT > DRAM
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} > IRAM AT> FLASH
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_vectorscopy = LOADADDR(.vectors);
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/* crt0.S initialization */
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.init :
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{
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. = ALIGN(0x4);
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_loadaddress = .;
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*(.init)
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} > FLASH
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/* Program code */
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.text :
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{
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. = ALIGN(0x4);
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*(.text*)
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} > FLASH
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/* Thumb interworking sections - for some reason LD dies even if these
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* sections are empty.
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*/
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.glue :
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{
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. = ALIGN(0x4);
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*(.glue_7) /* ARM calling Thumb */
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*(.glue_7t) /* Thumb calling ARM */
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} > FLASH
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/* Read-only data */
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.rodata :
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{
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. = ALIGN(0x4);
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*(.rodata*)
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} > FLASH
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/* Dynamic data - this needs to be copied out of flash before it is used. */
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.data :
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{
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. = ALIGN(0x4);
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_dramstart = .;
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*(.data*)
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_dramend = .;
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} > DRAM AT> FLASH
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_dramcopy = LOADADDR(.data);
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.bss (NOLOAD) :
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{
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. = ALIGN(0x4);
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_bss_start = .;
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*(.bss*)
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*(COMMON)
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_bss_end = .;
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} > DRAM
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.iram :
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{
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. = ALIGN(0x4);
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_iramstart = .;
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*(.icode)
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*(.irodata*)
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*(.irodata)
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*(.idata)
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. = ALIGN(0x4);
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_iramend = .;
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} > IRAM AT> DRAM
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} > IRAM AT> FLASH
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_iramcopy = LOADADDR(.iram);
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.ibss (NOLOAD) :
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{
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_iedata = .;
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*(.ibss)
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. = ALIGN(0x4);
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_iend = .;
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_ibss_start = .;
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*(.ibss)
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_ibss_end = .;
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} > IRAM
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.stack (NOLOAD) :
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/* Program stack space */
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.pro_stack (NOLOAD):
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{
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*(.stack)
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stackbegin = .;
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. += 0x2000;
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stackend = .;
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} > IRAM
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.irqstack (NOLOAD) :
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{
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*(.stack)
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. += 0x400;
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irq_stack = .;
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} > IRAM
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.fiqstack (NOLOAD) :
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{
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*(.stack)
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. += 0x100;
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fiq_stack = .;
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} > IRAM
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.bss (NOLOAD) :
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{
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. = ADDR(.data) + SIZEOF(.data) + SIZEOF(.vectors) + SIZEOF(.iram);
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_edata = .;
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*(.bss*)
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*(COMMON)
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. = ALIGN(0x4);
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_end = .;
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} > DRAM
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*(.stack)
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stackbegin = .; /* Variable for thread.c */
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_pro_stack_end = .;
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. += PRO_STACK_SIZE;
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_pro_stack_start = .;
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stackend = .; /* Variable for tread.c */
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} > IRAM
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/* IRQ stack space */
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.irq_stack (NOLOAD):
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{
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. = ALIGN(0x4);
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_irq_stack_end = .;
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. += IRQ_STACK_SIZE;
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_irq_stack_start = .;
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} > IRAM
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/* FIQ stack space */
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.fiq_stack (NOLOAD):
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{
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. = ALIGN(0x4);
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_fiq_stack_end = .;
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. += FIQ_STACK_SIZE;
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_fiq_stack_start = .;
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} > IRAM
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.ttbtable TTB_BEGIN (NOLOAD) :
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{
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@ -0,0 +1,313 @@
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/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id: $
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*
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* Copyright (C) 2010 by Karl Kurbjun
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include "config.h"
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#include "cpu.h"
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#define SDRAM_MODE 0x9B00
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/* Macro for reading a register */
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.macro mrh register
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ldr r1, =\register
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ldrh r0, [r1]
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.endm
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/* Macro for writing a register */
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.macro mwh register, value
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ldr r0, =\value
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ldr r1, =\register
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strh r0, [r1]
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.endm
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/* This version uses a mov to save on the literal pool size. Otherwise it is
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* functionally equivalent.
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*/
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.macro mwhm register, value
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mov r0, #\value
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ldr r1, =\register
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strh r0, [r1]
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.endm
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/******************************************************************************
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* _init_board: *
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* This function initializes the specific baord this SoC is on. *
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******************************************************************************/
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.section .init, "ax"
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.code 32
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.align 0x04
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.global _init_board
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.type _init_board, %function
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_init_board:
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/* Setup the EMIF interface timings */
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/* FLASH interface:
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* These are based on the OF setup
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*/
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/* IO_EMIF_CS0CTRL1 and
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* IO_EMIF_CS0CTRL2
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*/
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mwh 0x30A00, 0x4488
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mwh 0x30A02, 0x1220
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/* ATA interface:
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* These are based on the OF setup
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*/
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/* IO_EMIF_CS3CTRL1 and
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* IO_EMIF_CS3CTRL2
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*/
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mwh 0x30A10, 0x77EF
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mwh 0x30A12, 0x5220
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/* USB interface:
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* The following EMIF timing values are from the OF:
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* IO_EMIF_CS4CTRL1 = 0x66AB;
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* IO_EMIF_CS4CTRL2 = 0x4220;
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*
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* More agressive numbers may be possible, but it depends on the clocking
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* setup.
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*/
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/* IO_EMIF_CS4CTRL1 and
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* IO_EMIF_CS4CTRL2
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*/
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mwh 0x30A14, 0x66AB
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mwh 0x30A16, 0x4220
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/* IO_EMIF_BUSCTRL */
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mwh 0x30A18, 0x0001
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_clock_setup:
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/* Clock initialization */
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/* Used for ES10 and unknown, slower clocks, but also uses more power
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* due to PLL setup and slow ARM clock speed.
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*/
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/* IO_CLK_BYP: Bypass the PLLs for the following changes */
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mwh 0x30894, 0x1111
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/* 27 MHz input clock:
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* IO_CLK_PLLA = 27 * 11 / 1 = 297 MHz
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* IO_CLK_PLLB = 27 * 13 / 1 = 351 MHz
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*/
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mwh 0x30880, 0x10A0
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mwh 0x30882, 0x10C0
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/* IO_CLK_SEL0: VLNQ is fed by PLLB, I2C from M48XI, MS from PLLA */
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mwh 0x30884, 0x17E
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/* IO_CLK_SEL1: VENC = MXI CLK, PLLA, PCLK, nodiv2 */
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mwhm 0x30886, 0x1000
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# IO_CLK_SEL2: ARM and AXL are from PLLB, SDRAM and DSP are PLLA */
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mwh 0x30888, 0x1001
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/* IO_CLK_DIV0: Set the slow clock speed for the ARM/AHB
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* Slow Setup:
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* ARM div = 4 ( 87.5 MHz )
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* AHB div = 1 ( 87.5 MHz )
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*/
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mwh 0x3088A, 0x0003 /* OF sets this to 0x0103 */
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/* IO_CLK_DIV1:
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* SDRAM div= 3 ( 99 MHz )
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* AXL div = 2 ( 175 MHz )
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*/
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mwh 0x3088C, 0x0102 /* OF sets this to 0x0103 */
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/* IO_CLK_DIV2:
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* MS div = 32 ( ~9 MHz )
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* DSP div = 3 ( 99 MHz )
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*/
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mwh 0x3088E, 0x020E
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/* IO_CLK_DIV3: (this comment is incorrect, (31 << 8) | 255;)
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* MMC div = 256 ( slow )
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* VENC div = 32 ( 843.75 KHz )
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*/
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mwhm 0x30890, 0x0003
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/* IO_CLK_DIV4: (this comment is incorrect, (31 << 8) | 0;)
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* I2C div = 1 (48 MHz if M48XI is running)
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* VLNQ div = 32
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*/
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mwhm 0x30892, 0x0200
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# PLLA &= ~0x1000 (BIC #0x1000)
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mrh 0x30880
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bic r0, r0, #0x1000
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strh r0, [r1]
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# PLLB &= ~0x1000
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mrh 0x30882
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bic r0, r0, #0x1000
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strh r0, [r1]
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/* Wait for PLLs to lock before feeding them to the downstream devices */
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_plla_wait:
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mrh 0x30880
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bic r0, r0, #0x7F
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tst r0, r0
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beq _plla_wait
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_pllb_wait:
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mrh 0x30882
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bic r0, r0, #0x7F
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tst r0, r0
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beq _plla_wait
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/* IO_CLK_BYP: Enable PLL feeds */
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mwhm 0x30894, 0x0
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/* IO_CLK_MOD0: Most off */
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mwh 0x30898, 0x0167
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/* IO_CLK_MOD1: All off */
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mwhm 0x3089A, 0x0
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/* IO_CLK_MOD2: Turn on the GPIO clock */
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mwhm 0x3089C, 0x20
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/* Setup the SDRAM range on the AHB bus */
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/* SDRAMSA */
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mov r0, #0x60000
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mov r1, #0x900000
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str r1, [r0, #0xF00]
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/* SDRAMEA: 64MB */
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mov r1, #0x4900000
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str r1, [r0, #0xF04]
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/* BUSCTRL */
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mov r1, #0x00000
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str r1, [r0, #0xF08]
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/* USBCTRL */
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str r1, [r0, #0xF20]
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/* Setup IO_SDRAM_SDMODE based on OF */
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mov r1, #0x00030000
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orr r1, r1, #0x900
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/* Pre-charge all banks */
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ldr r0, =(SDRAM_MODE | 0x82)
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strh r0, [r1, #0xA6]
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/* Setup auto refresh, OF uses 0x5F */
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ldr r0, =0x140
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strh r0, [r1, #0xA8]
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/* Issue 8 auto refresh cycles */
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ldr r0, =(SDRAM_MODE | 0x84)
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strh r0, [r1, #0xA6]
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strh r0, [r1, #0xA6]
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strh r0, [r1, #0xA6]
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strh r0, [r1, #0xA6]
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strh r0, [r1, #0xA6]
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strh r0, [r1, #0xA6]
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strh r0, [r1, #0xA6]
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strh r0, [r1, #0xA6]
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/* Set the mode register */
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ldr r0, =(SDRAM_MODE | 0x81)
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strh r0, [r1, #0xA6]
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/* Go back to the NOP state */
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ldr r0, =(SDRAM_MODE | 0x80)
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strh r0, [r1, #0xA6]
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/* Turn on auto power down */
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ldr r0, =(SDRAM_MODE | 0x40)
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strh r0, [r1, #0xA6]
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/* Go through the GPIO initialization */
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/* IO_GIO_FSEL0: Set up the GPIO pin functions 0-16 */
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mwh 0x305A4, 0x0000
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/* IO_GIO_FSEL1: 17-24 */
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mwh 0x305A6, 0x0000
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/* IO_GIO_FSEL2: 18-32 */
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mwh 0x305A8, 0x1450
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/* IO_GIO_FSEL3: 33-40 */
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mwh 0x305AA, 0x0404
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/* IO_GIO_DIR0 */
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mwh 0x30580, 0x6A0B
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/* IO_GIO_DIR1: Important note - pin 26 has control over the system power.
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* If this pin is not initialized the device will shut off immediately.
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*/
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mwh 0x30582, 0x8B00
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/* IO_GIO_DIR2 */
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mwh 0x30584, 0x0000
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|
||||
/* IO_GIO_INV0 */
|
||||
mwh 0x30586, 0x0000
|
||||
|
||||
/* IO_GIO_INV1 */
|
||||
mwh 0x30588, 0x0000
|
||||
|
||||
/* IO_GIO_INV2 */
|
||||
mwh 0x3058A, 0x0000
|
||||
|
||||
/* IO_GIO_BITCLR0 */
|
||||
mwh 0x30592, 0xFFFF
|
||||
|
||||
/* IO_GIO_BITCLR1 */
|
||||
mwh 0x30594, 0xFFFF
|
||||
|
||||
/* IO_GIO_BITCLR2 */
|
||||
mwh 0x30596, 0xFFFF
|
||||
|
||||
/* IO_GIO_BITSET0 */
|
||||
mwh 0x3058C, 0x0280
|
||||
|
||||
/* IO_GIO_BITSET1 */
|
||||
mwh 0x3058E, 0x2066
|
||||
|
||||
/* IO_GIO_BITSET2 */
|
||||
mwh 0x30590, 0x0025
|
||||
|
||||
/* IO_GIO_IRQPORT */
|
||||
mwh 0x30598, 0xD60B
|
||||
|
||||
/* IO_GIO_IRQEDGE */
|
||||
mwh 0x3059A, 0x0801
|
||||
|
||||
/* IO_GIO_CHAT0 */
|
||||
mwh 0x3059C, 0x0000
|
||||
|
||||
/* IO_GIO_CHAT1 */
|
||||
mwh 0x3059E, 0x0000
|
||||
|
||||
/* IO_GIO_CHAT2 */
|
||||
mwh 0x305A0, 0x0000
|
||||
|
||||
/* IO_GIO_NCHAT */
|
||||
mwh 0x305A2, 0x0000
|
||||
|
||||
bx lr
|
||||
|
||||
.ltorg
|
||||
.size _init_board, .-_init_board
|
||||
|
||||
Loading…
Reference in New Issue