Onda VX747:
* Add YUV support * Clean up LCD driver a bit and speed it up git-svn-id: svn://svn.rockbox.org/rockbox/trunk@20730 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Maurus Cuelenaere
parent
14a510aff2
commit
a54e0b6dba
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@ -1305,10 +1305,10 @@
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#define ICDC_CDCCR1_SUSPD (1 << 1)
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#define ICDC_CDCCR1_RST (1 << 0)
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#define ICDC_CDCCR2_AINVOL(n) ((n & 5) << 16)
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#define ICDC_CDCCR2_SMPR(n) ((n & 4) << 8)
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#define ICDC_CDCCR2_MICBG(n) ((n & 2) << 4)
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#define ICDC_CDCCR2_HPVOL(n) ((n & 2) << 0)
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#define ICDC_CDCCR2_AINVOL(n) ((n & 0x1F) << 16)
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#define ICDC_CDCCR2_SMPR(n) ((n & 0xF) << 8)
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#define ICDC_CDCCR2_MICBG(n) ((n & 0x3) << 4)
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#define ICDC_CDCCR2_HPVOL(n) ((n & 0x3) << 0)
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#define ICDC_CDCCR2_AINVOL_DB(n) ((n+34.5)/1.5)
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@ -1423,7 +1423,7 @@
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#define SSI_CR1_MULTS (1 << 22)
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#define SSI_CR1_FMAT_BIT 20
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#define SSI_CR1_FMAT_MASK (0x3 << SSI_CR1_FMAT_BIT)
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#define SSI_CR1_FMAT_SPI (0 << SSI_CR1_FMAT_BIT) /* Motorola¡¯s SPI format */
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#define SSI_CR1_FMAT_SPI (0 << SSI_CR1_FMAT_BIT) /* Motorola¡¯s SPI format */
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#define SSI_CR1_FMAT_SSP (1 << SSI_CR1_FMAT_BIT) /* TI's SSP format */
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#define SSI_CR1_FMAT_MW1 (2 << SSI_CR1_FMAT_BIT) /* National Microwire 1 format */
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#define SSI_CR1_FMAT_MW2 (3 << SSI_CR1_FMAT_BIT) /* National Microwire 2 format */
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@ -4984,7 +4984,7 @@ do{ \
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// IPU_REG_BASE
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#define IPU_P_BASE 0x13080000
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#define IPU__OFFSET 0x13080000
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#define IPU_V_BASE 0xB3080000
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#define IPU__SIZE 0x00001000
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struct ipu_module
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@ -5069,10 +5069,12 @@ struct Ration2m
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#define INFMT_YCbCr422 (5 << 0)
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#define INFMT_YCbCr444 (6 << 0)
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#define INFMT_YCbCr411 (7 << 0)
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#define INFMT_MASK (7)
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#define OUTFMT_RGB555 (0 << 16)
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#define OUTFMT_RGB565 (1 << 16)
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#define OUTFMT_RGB888 (2 << 16)
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#define OUTFMT_MASK (3 << 16)
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// REG_IN_FM_GS field define
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#define IN_FM_W(val) ((val) << 16)
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@ -5086,7 +5088,6 @@ struct Ration2m
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#define U_STRIDE(val) ((val) << 16)
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#define V_STRIDE(val) ((val) << 0)
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#define VE_IDX_SFT 0
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#define HE_IDX_SFT 16
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@ -5099,53 +5100,106 @@ struct Ration2m
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#define W_COEF_MSK 0xFF
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// function about REG_CTRL
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#define IPU_STOP_IPU(IPU_V_BASE) \
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#define IPU_STOP_IPU() \
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REG32(IPU_V_BASE + REG_CTRL) &= ~IPU_EN;
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#define IPU_RUN_IPU(IPU_V_BASE) \
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#define IPU_RUN_IPU() \
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REG32(IPU_V_BASE + REG_CTRL) |= IPU_EN;
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#define IPU_RESET_IPU(IPU_V_BASE) \
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#define IPU_RESET_IPU() \
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REG32(IPU_V_BASE + REG_CTRL) |= IPU_RESET;
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#define IPU_DISABLE_IRQ(IPU_V_BASE) \
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#define IPU_DISABLE_IRQ() \
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REG32(IPU_V_BASE + REG_CTRL) &= ~FM_IRQ_EN;
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#define IPU_DISABLE_RSIZE(IPU_V_BASE) \
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#define IPU_DISABLE_RSIZE() \
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REG32(IPU_V_BASE + REG_CTRL) &= ~RSZ_EN;
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#define IPU_ENABLE_RSIZE(IPU_V_BASE) \
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#define IPU_ENABLE_RSIZE() \
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REG32(IPU_V_BASE + REG_CTRL) |= RSZ_EN;
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#define IPU_IS_ENABLED(IPU_V_BASE) \
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#define IPU_IS_ENABLED() \
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(REG32(IPU_V_BASE + REG_CTRL) & IPU_EN)
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// function about REG_STATUS
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#define IPU_CLEAR_END_FLAG(IPU_V_BASE) \
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#define IPU_CLEAR_END_FLAG() \
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REG32(IPU_V_BASE + REG_STATUS) &= ~OUT_END;
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#define IPU_POLLING_END_FLAG(IPU_V_BASE) \
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#define IPU_POLLING_END_FLAG() \
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(REG32(IPU_V_BASE + REG_STATUS) & OUT_END)
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#define IPU_SET_INFMT(fmt) \
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REG32(IPU_V_BASE + REG_D_FMT) = (REG32(IPU_V_BASE + REG_D_FMT) & ~INFMT_MASK) | (fmt);
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#define IPU_SET_OUTFMT(fmt) \
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REG32(IPU_V_BASE + REG_D_FMT) = (REG32(IPU_V_BASE + REG_D_FMT) & ~OUTFMT_MASK) | (fmt);
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#define IPU_SET_IN_FM(w, h) \
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REG32(IPU_V_BASE + REG_IN_FM_GS) = IN_FM_W(w) | IN_FM_H(h);
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#define IPU_SET_Y_STRIDE(stride) \
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REG32(IPU_V_BASE + REG_Y_STRIDE) = (stride);
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#define IPU_SET_UV_STRIDE(u, v) \
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REG32(IPU_V_BASE + REG_UV_STRIDE) = U_STRIDE(u) | V_STRIDE(v);
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#define IPU_SET_Y_ADDR(addr) \
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REG32(IPU_V_BASE + REG_Y_ADDR) = (addr);
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#define IPU_SET_U_ADDR(addr) \
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REG32(IPU_V_BASE + REG_U_ADDR) = (addr);
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#define IPU_SET_V_ADDR(addr) \
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REG32(IPU_V_BASE + REG_V_ADDR) = (addr);
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#define IPU_SET_OUT_ADDR(addr) \
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REG32(IPU_V_BASE + REG_OUT_ADDR) = (addr);
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#define IPU_SET_OUT_FM(w, h) \
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REG32(IPU_V_BASE + REG_OUT_GS) = OUT_FM_W(w) | OUT_FM_H(h);
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#define IPU_SET_OUT_STRIDE(stride) \
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REG32(IPU_V_BASE + REG_OUT_STRIDE) = (stride);
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#define IPU_SET_CSC_C0_COEF(coef) \
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REG32(IPU_V_BASE + REG_CSC_C0_COEF) = (coef);
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#define IPU_SET_CSC_C1_COEF(coef) \
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REG32(IPU_V_BASE + REG_CSC_C1_COEF) = (coef);
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#define IPU_SET_CSC_C2_COEF(coef) \
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REG32(IPU_V_BASE + REG_CSC_C2_COEF) = (coef);
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#define IPU_SET_CSC_C3_COEF(coef) \
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REG32(IPU_V_BASE + REG_CSC_C3_COEF) = (coef);
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#define IPU_SET_CSC_C4_COEF(coef) \
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REG32(IPU_V_BASE + REG_CSC_C4_COEF) = (coef);
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/* YCbCr */
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/* parameter
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R = 1.164 * (Y - 16) + 1.596 * (cr - 128) {C0, C1}
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G = 1.164 * (Y - 16) - 0.392 * (cb -128) - 0.813 * (cr - 128) {C0, C2, C3}
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B = 1.164 * (Y - 16) + 2.017 * (cb - 128) {C0, C4}
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*/
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#define YCBCR_CSC_C0 0x4A8 /* 1.164 * 1024 */
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#define YCBCR_CSC_C1 0x662 /* 1.596 * 1024 */
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#define YCBCR_CSC_C2 0x191 /* 0.392 * 1024 */
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#define YCBCR_CSC_C3 0x341 /* 0.813 * 1024 */
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#define YCBCR_CSC_C4 0x811 /* 2.017 * 1024 */
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#if 1
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#define YUV_CSC_C0 0x4A8 /* 1.164 * 1024 */
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#define YUV_CSC_C1 0x662 /* 1.596 * 1024 */
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#define YUV_CSC_C2 0x191 /* 0.392 * 1024 */
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#define YUV_CSC_C3 0x341 /* 0.813 * 1024 */
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#define YUV_CSC_C4 0x811 /* 2.017 * 1024 */
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#else
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/* YUV */
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/* parameter
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R = 1 * (Y – 0) + 1.4026 * (V - 128) {C0, C1}
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G = 1 * (Y – 0) – 0.3444 * (U - 128) – 0.7144 * (V - 128) {C0, C2, C3}
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B = 1 * (Y – 0) + 1.7730 * (U - 128) {C0, C4}
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*/
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#define YUV_CSC_C0 0x400
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#define YUV_CSC_C1 0x59C
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#define YUV_CSC_C2 0x161
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#define YUV_CSC_C3 0x2DC
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#define YUV_CSC_C4 0x718
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#endif
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#endif /* _IPU_H_ */
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@ -26,6 +26,7 @@
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#define __R61509_H
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/* Register list */
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#define REG_DEVICE_CODE 0x000
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#define REG_DRIVER_OUTPUT 0x001
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#define REG_LCD_DR_WAVE_CTRL 0x002
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#define REG_ENTRY_MODE 0x003
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@ -71,7 +71,14 @@ bool lcd_active(void)
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/* Update a fraction of the display. */
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void lcd_update_rect(int x, int y, int width, int height)
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{
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x=0;y=0;width=LCD_WIDTH;height=LCD_HEIGHT; /* HACK! */
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/* Currently only do full updates.
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* DMA can't handle partial updates and CPU is too slow compared
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* to full DMA updates */
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x = 0;
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y = 0;
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width = LCD_WIDTH;
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height = LCD_HEIGHT;
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mutex_lock(&lcd_mtx);
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__cpm_start_lcd();
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@ -82,12 +89,12 @@ x=0;y=0;width=LCD_WIDTH;height=LCD_HEIGHT; /* HACK! */
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REG_DMAC_DCCSR(DMA_LCD_CHANNEL) = DMAC_DCCSR_NDES;
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REG_DMAC_DSAR(DMA_LCD_CHANNEL) = PHYSADDR((unsigned long)&lcd_framebuffer[y][x]);
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REG_DMAC_DRSR(DMA_LCD_CHANNEL) = DMAC_DRSR_RS_SLCD; /* source = SLCD */
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REG_DMAC_DRSR(DMA_LCD_CHANNEL) = DMAC_DRSR_RS_SLCD;
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REG_DMAC_DTAR(DMA_LCD_CHANNEL) = PHYSADDR(SLCD_FIFO);
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REG_DMAC_DTCR(DMA_LCD_CHANNEL) = width*height;
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REG_DMAC_DTCR(DMA_LCD_CHANNEL) = (width * height) >> 3;
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REG_DMAC_DCMD(DMA_LCD_CHANNEL) = ( DMAC_DCMD_SAI | DMAC_DCMD_RDIL_IGN | DMAC_DCMD_SWDH_32
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| DMAC_DCMD_DWDH_16 | DMAC_DCMD_DS_16BIT );
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| DMAC_DCMD_DWDH_16 | DMAC_DCMD_DS_16BYTE );
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__dcache_writeback_all(); /* Size of framebuffer is way bigger than cache size.
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We need to find a way to make the framebuffer uncached, so this statement can get removed. */
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@ -101,7 +108,6 @@ x=0;y=0;width=LCD_WIDTH;height=LCD_HEIGHT; /* HACK! */
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wakeup_wait(&lcd_wkup, TIMEOUT_BLOCK); /* Sleeping in lcd_update() should be safe */
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REG_DMAC_DCCSR(DMA_LCD_CHANNEL) &= ~DMAC_DCCSR_EN; /* Disable DMA channel */
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dma_disable();
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while(REG_SLCD_STATE & SLCD_STATE_BUSY);
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@ -139,17 +145,54 @@ void lcd_update(void)
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lcd_update_rect(0, 0, LCD_WIDTH, LCD_HEIGHT);
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}
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/* TODO: use IPU */
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/* (Mis)use LCD framebuffer as a temporary buffer */
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void lcd_blit_yuv(unsigned char * const src[3],
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int src_x, int src_y, int stride,
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int x, int y, int width, int height)
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{
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(void)src;
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(void)src_x;
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(void)src_y;
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(void)stride;
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(void)x;
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(void)y;
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(void)width;
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(void)height;
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__dcache_writeback_all();
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__cpm_start_ipu();
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IPU_STOP_IPU();
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IPU_RESET_IPU()
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IPU_CLEAR_END_FLAG();
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IPU_DISABLE_RSIZE();
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IPU_DISABLE_IRQ();
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IPU_SET_INFMT(INFMT_YUV420);
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IPU_SET_OUTFMT(OUTFMT_RGB565);
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IPU_SET_IN_FM(width, height);
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IPU_SET_Y_STRIDE(stride);
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IPU_SET_UV_STRIDE(stride, stride);
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IPU_SET_Y_ADDR((unsigned long)src[0]);
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IPU_SET_U_ADDR((unsigned long)src[2]);
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IPU_SET_V_ADDR((unsigned long)src[3]);
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IPU_SET_OUT_ADDR(PHYSADDR((unsigned long)&lcd_framebuffer[y][x]));
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IPU_SET_OUT_FM(width, height);
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IPU_SET_OUT_STRIDE(stride);
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IPU_SET_CSC_C0_COEF(YUV_CSC_C0);
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IPU_SET_CSC_C1_COEF(YUV_CSC_C1);
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IPU_SET_CSC_C2_COEF(YUV_CSC_C2);
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IPU_SET_CSC_C2_COEF(YUV_CSC_C3);
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IPU_SET_CSC_C4_COEF(YUV_CSC_C4);
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IPU_RUN_IPU();
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while(!(IPU_POLLING_END_FLAG()) && IPU_IS_ENABLED());
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IPU_CLEAR_END_FLAG();
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IPU_STOP_IPU();
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//__cpm_stop_ipu();
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__dcache_invalidate_all();
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/* YUV speed is limited by LCD speed */
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lcd_update_rect(x, y, width, height);
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}
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@ -29,7 +29,7 @@ void lcd_init_device(void);
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void lcd_init_controller(void);
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void lcd_set_target(short x, short y, short width, short height);
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void lcd_set_target(int x, int y, int width, int height);
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void lcd_on(void);
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void lcd_off(void);
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@ -25,23 +25,22 @@
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#include "lcd.h"
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#include "lcd-target.h"
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#define PIN_CS_N (32*1+17) /* Chip select */
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#define PIN_RESET_N (32*1+18) /* Reset */
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#define LCD_PCLK (20000000) /* LCD PCLK */
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#define PIN_CS_N (32*1+17) /* Chip select */
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#define PIN_RESET_N (32*1+18) /* Reset */
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#define LCD_PCLK (20000000) /* LCD PCLK */
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#define my__gpio_as_lcd_16bit() \
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do { \
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REG_GPIO_PXFUNS(2) = 0x001cffff; \
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REG_GPIO_PXSELC(2) = 0x001cffff; \
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REG_GPIO_PXPES(2) = 0x001cffff; \
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REG_GPIO_PXPES(2) = 0x001cffff; \
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} while (0)
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#define SLEEP(x) for(i=0; i<x; i++) asm("nop"); asm("nop");
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#define SLEEP(x) { register int __i; for(__i=0; __i<x; __i++) {asm("nop"); asm("nop");} }
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#define DELAY SLEEP(700000);
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static void _display_pin_init(void)
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{
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int i;
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my__gpio_as_lcd_16bit();
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__gpio_as_output(PIN_CS_N);
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__gpio_as_output(PIN_RESET_N);
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@ -61,8 +60,6 @@ static void _display_pin_init(void)
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#define SLCD_SEND_COMMAND(cmd,val) SLCD_SET_COMMAND(cmd); SLCD_SET_DATA(val);
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static void _display_init(void)
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{
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int i;
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SLCD_SEND_COMMAND(REG_SOFT_RESET, SOFT_RESET(1));
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SLEEP(700000);
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SLCD_SEND_COMMAND(REG_SOFT_RESET, SOFT_RESET(0));
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@ -72,9 +69,9 @@ static void _display_init(void)
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SLCD_SEND_COMMAND(REG_DRIVER_OUTPUT, 0x100);
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SLCD_SEND_COMMAND(REG_LCD_DR_WAVE_CTRL, 0x100);
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#if CONFIG_ORIENTATION == SCREEN_PORTRAIT
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SLCD_SEND_COMMAND(REG_ENTRY_MODE, (ENTRY_MODE_BGR | ENTRY_MODE_VID | ENTRY_MODE_HID | ENTRY_MODE_HWM));
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SLCD_SEND_COMMAND(REG_ENTRY_MODE, (ENTRY_MODE_BGR | ENTRY_MODE_VID | ENTRY_MODE_HID));
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#else
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SLCD_SEND_COMMAND(REG_ENTRY_MODE, (ENTRY_MODE_BGR | ENTRY_MODE_VID | ENTRY_MODE_AM | ENTRY_MODE_HWM));
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SLCD_SEND_COMMAND(REG_ENTRY_MODE, (ENTRY_MODE_BGR | ENTRY_MODE_VID | ENTRY_MODE_AM));
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#endif
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SLCD_SEND_COMMAND(REG_DISP_CTRL2, 0x503);
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SLCD_SEND_COMMAND(REG_DISP_CTRL3, 1);
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@ -95,19 +92,6 @@ static void _display_init(void)
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SLCD_SEND_COMMAND(REG_PWR_CTRL4, 0x2f00);
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SLCD_SEND_COMMAND(REG_PWR_CTRL5, 0);
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SLCD_SEND_COMMAND(REG_PWR_CTRL6, 1);
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SLCD_SEND_COMMAND(REG_RAM_HADDR_SET, 0); /* set cursor at x_start */
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SLCD_SEND_COMMAND(REG_RAM_VADDR_SET, 0); /* set cursor at y_start */
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#if CONFIG_ORIENTATION == SCREEN_PORTRAIT
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SLCD_SEND_COMMAND(REG_RAM_HADDR_START, 0); /* y_start*/
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SLCD_SEND_COMMAND(REG_RAM_HADDR_END, 239); /* y_end */
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SLCD_SEND_COMMAND(REG_RAM_VADDR_START, 0); /* x_start */
|
||||
SLCD_SEND_COMMAND(REG_RAM_VADDR_END, 399); /* x_end */
|
||||
#else
|
||||
SLCD_SEND_COMMAND(REG_RAM_HADDR_START, 0); /* y_start*/
|
||||
SLCD_SEND_COMMAND(REG_RAM_HADDR_END, 399); /* y_end */
|
||||
SLCD_SEND_COMMAND(REG_RAM_VADDR_START, 0); /* x_start */
|
||||
SLCD_SEND_COMMAND(REG_RAM_VADDR_END, 239); /* x_end */
|
||||
#endif
|
||||
SLCD_SEND_COMMAND(REG_RW_NVM, 0);
|
||||
SLCD_SEND_COMMAND(REG_VCOM_HVOLTAGE1, 6);
|
||||
SLCD_SEND_COMMAND(REG_VCOM_HVOLTAGE2, 0);
|
||||
|
|
@ -144,42 +128,34 @@ static void _display_init(void)
|
|||
SLCD_SEND_COMMAND(0x7f5, 1);
|
||||
SLCD_SEND_COMMAND(0x7f0, 0);
|
||||
|
||||
/* LCD ON: */
|
||||
SLCD_SEND_COMMAND(REG_DISP_CTRL1, (DISP_CTRL1_BASEE | DISP_CTRL1_VON
|
||||
| DISP_CTRL1_GON | DISP_CTRL1_DTE | DISP_CTRL1_D(3))
|
||||
);
|
||||
/* LCD ON */
|
||||
SLCD_SEND_COMMAND(REG_DISP_CTRL1, (DISP_CTRL1_BASEE | DISP_CTRL1_VON |
|
||||
DISP_CTRL1_GON | DISP_CTRL1_DTE | DISP_CTRL1_D(3)));
|
||||
SLEEP(3500000);
|
||||
SLCD_SEND_COMMAND(REG_DISP_CTRL1, (DISP_CTRL1_BASEE | DISP_CTRL1_VON
|
||||
| DISP_CTRL1_GON | DISP_CTRL1_DTE | DISP_CTRL1_D(2))
|
||||
);
|
||||
SLCD_SEND_COMMAND(REG_DISP_CTRL1, (DISP_CTRL1_BASEE | DISP_CTRL1_VON |
|
||||
DISP_CTRL1_GON | DISP_CTRL1_DTE | DISP_CTRL1_D(2)));
|
||||
SLEEP(3500000);
|
||||
SLCD_SEND_COMMAND(REG_DISP_CTRL1, (DISP_CTRL1_BASEE | DISP_CTRL1_VON
|
||||
| DISP_CTRL1_GON | DISP_CTRL1_DTE | DISP_CTRL1_D(3))
|
||||
);
|
||||
SLCD_SEND_COMMAND(REG_DISP_CTRL1, (DISP_CTRL1_BASEE | DISP_CTRL1_VON |
|
||||
DISP_CTRL1_GON | DISP_CTRL1_DTE | DISP_CTRL1_D(3)));
|
||||
SLEEP(3500000);
|
||||
}
|
||||
|
||||
static void _display_on(void)
|
||||
{
|
||||
int i;
|
||||
SLCD_SEND_COMMAND(REG_PWR_CTRL1, (PWR_CTRL1_SAPE | PWR_CTRL1_BT(6) | PWR_CTRL1_APE | PWR_CTRL1_AP(3)));
|
||||
SLEEP(3500000);
|
||||
SLCD_SEND_COMMAND(REG_DISP_CTRL1, (DISP_CTRL1_VON | DISP_CTRL1_GON
|
||||
| DISP_CTRL1_D(1))
|
||||
);
|
||||
SLCD_SEND_COMMAND(REG_DISP_CTRL1, (DISP_CTRL1_VON | DISP_CTRL1_GON |
|
||||
DISP_CTRL1_D(1)));
|
||||
SLEEP(3500000);
|
||||
SLCD_SEND_COMMAND(REG_DISP_CTRL1, (DISP_CTRL1_VON | DISP_CTRL1_GON
|
||||
| DISP_CTRL1_DTE | DISP_CTRL1_D(3)
|
||||
| DISP_CTRL1_BASEE)
|
||||
);
|
||||
SLCD_SEND_COMMAND(REG_DISP_CTRL1, (DISP_CTRL1_VON | DISP_CTRL1_GON |
|
||||
DISP_CTRL1_DTE | DISP_CTRL1_D(3) |
|
||||
DISP_CTRL1_BASEE));
|
||||
}
|
||||
|
||||
static void _display_off(void)
|
||||
{
|
||||
int i;
|
||||
SLCD_SEND_COMMAND(REG_DISP_CTRL1, (DISP_CTRL1_VON | DISP_CTRL1_GON
|
||||
| DISP_CTRL1_DTE | DISP_CTRL1_D(2))
|
||||
);
|
||||
SLCD_SEND_COMMAND(REG_DISP_CTRL1, (DISP_CTRL1_VON | DISP_CTRL1_GON |
|
||||
DISP_CTRL1_DTE | DISP_CTRL1_D(2)));
|
||||
SLEEP(3500000);
|
||||
SLCD_SEND_COMMAND(REG_DISP_CTRL1, DISP_CTRL1_D(1));
|
||||
SLEEP(3500000);
|
||||
|
|
@ -193,9 +169,9 @@ static void _set_lcd_bus(void)
|
|||
REG_LCD_CFG &= ~LCD_CFG_LCDPIN_MASK;
|
||||
REG_LCD_CFG |= LCD_CFG_LCDPIN_SLCD;
|
||||
|
||||
REG_SLCD_CFG = (SLCD_CFG_BURST_8_WORD | SLCD_CFG_DWIDTH_16 | SLCD_CFG_CWIDTH_16BIT
|
||||
| SLCD_CFG_CS_ACTIVE_LOW | SLCD_CFG_RS_CMD_LOW | SLCD_CFG_CLK_ACTIVE_FALLING
|
||||
| SLCD_CFG_TYPE_PARALLEL);
|
||||
REG_SLCD_CFG = (SLCD_CFG_BURST_8_WORD | SLCD_CFG_DWIDTH_16 | SLCD_CFG_CWIDTH_16BIT |
|
||||
SLCD_CFG_CS_ACTIVE_LOW | SLCD_CFG_RS_CMD_LOW | SLCD_CFG_CLK_ACTIVE_FALLING |
|
||||
SLCD_CFG_TYPE_PARALLEL);
|
||||
}
|
||||
|
||||
static void _set_lcd_clock(void)
|
||||
|
|
@ -204,8 +180,7 @@ static void _set_lcd_clock(void)
|
|||
|
||||
__cpm_stop_lcd();
|
||||
|
||||
val = __cpm_get_pllout2() / LCD_PCLK;
|
||||
val--;
|
||||
val = (__cpm_get_pllout2() / LCD_PCLK) - 1;
|
||||
if ( val > 0x1ff )
|
||||
val = 0x1ff; /* CPM_LPCDR is too large, set it to 0x1ff */
|
||||
__cpm_set_pixdiv(val);
|
||||
|
|
@ -215,7 +190,6 @@ static void _set_lcd_clock(void)
|
|||
|
||||
void lcd_init_controller(void)
|
||||
{
|
||||
int i;
|
||||
_display_pin_init();
|
||||
_set_lcd_bus();
|
||||
_set_lcd_clock();
|
||||
|
|
@ -223,37 +197,37 @@ void lcd_init_controller(void)
|
|||
_display_init();
|
||||
}
|
||||
|
||||
void lcd_set_target(short x, short y, short width, short height)
|
||||
void lcd_set_target(int x, int y, int width, int height)
|
||||
{
|
||||
#if CONFIG_ORIENTATION == SCREEN_PORTRAIT
|
||||
SLCD_SEND_COMMAND(REG_RAM_HADDR_START, y); /* y_start */
|
||||
SLCD_SEND_COMMAND(REG_RAM_HADDR_END, y+width-1); /* y_end */
|
||||
SLCD_SEND_COMMAND(REG_RAM_VADDR_START, x); /* x_start */
|
||||
SLCD_SEND_COMMAND(REG_RAM_VADDR_END, x+height-1); /* x_end */
|
||||
SLCD_SEND_COMMAND(REG_RAM_HADDR_START, x);
|
||||
SLCD_SEND_COMMAND(REG_RAM_HADDR_END, x + width - 1);
|
||||
SLCD_SEND_COMMAND(REG_RAM_VADDR_START, y);
|
||||
SLCD_SEND_COMMAND(REG_RAM_VADDR_END, y + height - 1);
|
||||
SLCD_SEND_COMMAND(REG_RAM_HADDR_SET, x);
|
||||
SLCD_SEND_COMMAND(REG_RAM_VADDR_SET, y);
|
||||
#else
|
||||
SLCD_SEND_COMMAND(REG_RAM_HADDR_START, y); /* y_start */
|
||||
SLCD_SEND_COMMAND(REG_RAM_HADDR_END, y+height-1); /* y_end */
|
||||
SLCD_SEND_COMMAND(REG_RAM_VADDR_START, x); /* x_start */
|
||||
SLCD_SEND_COMMAND(REG_RAM_VADDR_END, x+width-1); /* x_end */
|
||||
SLCD_SEND_COMMAND(REG_RAM_HADDR_START, y);
|
||||
SLCD_SEND_COMMAND(REG_RAM_HADDR_END, y + height - 1);
|
||||
SLCD_SEND_COMMAND(REG_RAM_VADDR_START, x);
|
||||
SLCD_SEND_COMMAND(REG_RAM_VADDR_END, x + width - 1);
|
||||
SLCD_SEND_COMMAND(REG_RAM_HADDR_SET, y);
|
||||
SLCD_SEND_COMMAND(REG_RAM_VADDR_SET, x);
|
||||
#endif
|
||||
SLCD_SEND_COMMAND(REG_RAM_HADDR_SET, y); /* set cursor at x_start */
|
||||
SLCD_SEND_COMMAND(REG_RAM_VADDR_SET, x); /* set cursor at y_start */
|
||||
SLCD_SET_COMMAND(REG_RW_GRAM); /* write data to GRAM */
|
||||
}
|
||||
|
||||
void lcd_set_flip(bool yesno)
|
||||
{
|
||||
int i;
|
||||
|
||||
__cpm_start_lcd();
|
||||
#if CONFIG_ORIENTATION == SCREEN_PORTRAIT
|
||||
if(yesno)
|
||||
{
|
||||
SLCD_SEND_COMMAND(REG_ENTRY_MODE, (ENTRY_MODE_BGR | ENTRY_MODE_HWM));
|
||||
SLCD_SEND_COMMAND(REG_ENTRY_MODE, ENTRY_MODE_BGR);
|
||||
}
|
||||
else
|
||||
{
|
||||
SLCD_SEND_COMMAND(REG_ENTRY_MODE, (ENTRY_MODE_BGR | ENTRY_MODE_VID | ENTRY_MODE_HID | ENTRY_MODE_HWM));
|
||||
SLCD_SEND_COMMAND(REG_ENTRY_MODE, (ENTRY_MODE_BGR | ENTRY_MODE_VID | ENTRY_MODE_HID));
|
||||
}
|
||||
#else
|
||||
if(yesno)
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user