Add some defines for pp502x. No guarantee as to full accuracy yet but that's not really too important. Use them in the code.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@14912 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Michael Sevakis
parent
1ed54f4302
commit
e760ba5a04
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@ -38,6 +38,7 @@
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#define COP_MESSAGE (*(volatile unsigned long *)(0x60001004))
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#define CPU_REPLY (*(volatile unsigned long *)(0x60001008))
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#define COP_REPLY (*(volatile unsigned long *)(0x6000100c))
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#define MBOX_CONTROL (*(volatile unsigned long *)(0x60001010))
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/* Interrupts */
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#define CPU_INT_STAT (*(volatile unsigned long*)(0x60004000))
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@ -170,12 +171,24 @@
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*/
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/* Cache Control */
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#define CACHE_PRIORITY (*(volatile unsigned long *)(0x60006044))
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#define CACHE_CTL (*(volatile unsigned long *)(0x6000c000))
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#define CACHE_MASK (*(volatile unsigned long *)(0xf000f040))
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#define CACHE_OPERATION (*(volatile unsigned long *)(0xf000f044))
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#define CACHE_FLUSH_MASK (*(volatile unsigned long *)(0xf000f048))
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/* CACHE_CTL bits */
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#define CACHE_CTL_DISABLE 0x0000
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#define CACHE_CTL_ENABLE 0x0001
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#define CACHE_CTL_RUN 0x0002
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#define CACHE_CTL_INIT 0x0004
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#define CACHE_CTL_VECT_REMAP 0x0010
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#define CACHE_CTL_READY 0x4000
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#define CACHE_CTL_BUSY 0x8000
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/* CACHE_OPERATION bits */
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#define CACHE_OP_FLUSH 0x0002
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#define CACHE_OP_INVALIDATE 0x0004
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#define CACHE_DISABLE 0
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#define CACHE_ENABLE 1
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#define CACHE_RUN 2
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#define CACHE_INIT 4
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/* GPIO Ports */
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#define GPIOA_ENABLE (*(volatile unsigned long *)(0x6000d000))
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@ -280,9 +293,17 @@
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/* Device initialization */
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#define PP_VER1 (*(volatile unsigned long *)(0x70000000))
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#define PP_VER2 (*(volatile unsigned long *)(0x70000004))
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#define STRAP_OPT_A (*(volatile unsigned long *)(0x70000008))
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#define STRAP_OPT_B (*(volatile unsigned long *)(0x7000000c))
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#define BUS_WIDTH_MASK 0x00000010
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#define RAM_TYPE_MASK 0x000000c0
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#define ROM_TYPE_MASK 0x00000008
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#define DEV_INIT (*(volatile unsigned long *)(0x70000020))
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/* some timing that needs to be handled during clock setup */
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#define DEV_TIMING1 (*(volatile unsigned long *)(0x70000034))
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#define XMB_NOR_CFG (*(volatile unsigned long *)(0x70000038))
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#define XMB_RAM_CFG (*(volatile unsigned long *)(0x7000003c))
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#define INIT_USB 0x80000000
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@ -324,19 +345,32 @@
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#define FIREWIRE_BASE 0xc6000000
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/* Memory controller */
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#define CACHE_BASE (*(volatile unsigned long*)(0xf0000000))
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#define CACHE_INIT_BASE (*(volatile unsigned long*)(0xf0004000))
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#define CACHE_FLUSH_BASE (*(volatile unsigned long*)(0xf0008000))
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#define CACHE_INVALID_BASE (*(volatile unsigned long*)(0xf000c000))
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#define MMAP0_LOGICAL (*(volatile unsigned long*)(0xf000f000))
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#define MMAP0_PHYSICAL (*(volatile unsigned long*)(0xf000f004))
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#define MMAP1_LOGICAL (*(volatile unsigned long*)(0xf000f008))
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#define MMAP1_PHYSICAL (*(volatile unsigned long*)(0xf000f00c))
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#define MMAP2_LOGICAL (*(volatile unsigned long*)(0xf000f010))
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#define MMAP2_PHYSICAL (*(volatile unsigned long*)(0xf000f014))
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#define MMAP3_LOGICAL (*(volatile unsigned long*)(0xf000f018))
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#define MMAP3_PHYSICAL (*(volatile unsigned long*)(0xf000f01c))
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#define CACHE_CTRL1 (*(volatile unsigned long*)(0xf000f020))
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#define CACHE_CTRL2 (*(volatile unsigned long*)(0xf000f024))
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#define CACHE_BASE (*(volatile unsigned long*)(0xf0000000))
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/* 0xf0000000-0xf0001fff */
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#define CACHE_DATA_BASE (*(volatile unsigned long*)(0xf0000000))
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/* 0xf0002000-0xf0003fff */
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#define CACHE_DATA_MIRROR_BASE (*(volatile unsigned long*)(0xf0002000))
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/* 0xf0004000-0xf0007fff */
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#define CACHE_STATUS_BASE (*(volatile unsigned long*)(0xf0004000))
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#define CACHE_FLUSH_BASE (*(volatile unsigned long*)(0xf0008000))
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#define CACHE_INVALID_BASE (*(volatile unsigned long*)(0xf000c000))
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#define MMAP_FIRST (*(volatile unsigned long*)(0xf000f000))
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#define MMAP_LAST (*(volatile unsigned long*)(0xf000f03c))
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#define MMAP0_LOGICAL (*(volatile unsigned long*)(0xf000f000))
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#define MMAP0_PHYSICAL (*(volatile unsigned long*)(0xf000f004))
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#define MMAP1_LOGICAL (*(volatile unsigned long*)(0xf000f008))
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#define MMAP1_PHYSICAL (*(volatile unsigned long*)(0xf000f00c))
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#define MMAP2_LOGICAL (*(volatile unsigned long*)(0xf000f010))
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#define MMAP2_PHYSICAL (*(volatile unsigned long*)(0xf000f014))
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#define MMAP3_LOGICAL (*(volatile unsigned long*)(0xf000f018))
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#define MMAP3_PHYSICAL (*(volatile unsigned long*)(0xf000f01c))
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#define MMAP4_LOGICAL (*(volatile unsigned long*)(0xf000f020))
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#define MMAP4_PHYSICAL (*(volatile unsigned long*)(0xf000f024))
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#define MMAP5_LOGICAL (*(volatile unsigned long*)(0xf000f028))
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#define MMAP5_PHYSICAL (*(volatile unsigned long*)(0xf000f02c))
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#define MMAP6_LOGICAL (*(volatile unsigned long*)(0xf000f030))
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#define MMAP6_PHYSICAL (*(volatile unsigned long*)(0xf000f034))
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#define MMAP7_LOGICAL (*(volatile unsigned long*)(0xf000f038))
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#define MMAP7_PHYSICAL (*(volatile unsigned long*)(0xf000f03c))
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#endif
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#endif /* __PP5020_H__ */
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@ -74,7 +74,7 @@ void rolo_restart_cop(void)
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invalidate_icache();
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/* Disable cache */
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CACHE_CTL = CACHE_DISABLE;
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CACHE_CTL = CACHE_CTL_DISABLE;
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/* Tell the main core that we're ready to reload */
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cpu_reply = 1;
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@ -123,9 +123,6 @@ void rolo_restart(const unsigned char* source, unsigned char* dest,
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{
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long i;
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unsigned char* localdest = dest;
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#ifdef CPU_PP502x
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unsigned long* memmapregs = (unsigned long*)0xf000f000;
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#endif
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/* This is the equivalent of a call to memcpy() but this must be done from
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iram to avoid overwriting itself and we don't want to depend on memcpy()
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@ -148,11 +145,14 @@ void rolo_restart(const unsigned char* source, unsigned char* dest,
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flush_icache();
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/* Disable cache */
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CACHE_CTL = CACHE_DISABLE;
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CACHE_CTL = CACHE_CTL_DISABLE;
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/* Reset the memory mapping registers to zero */
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for (i=0;i<8;i++)
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memmapregs[i]=0;
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{
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volatile unsigned long *mmap_reg;
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for (mmap_reg = &MMAP_FIRST; mmap_reg <= &MMAP_LAST; mmap_reg++)
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*mmap_reg = 0;
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}
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#if NUM_CORES > 1
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/* Tell the COP it's safe to continue rebooting */
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@ -86,21 +86,21 @@ void irq(void)
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void flush_icache(void) ICODE_ATTR;
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void flush_icache(void)
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{
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if (CACHE_CTL & CACHE_ENABLE)
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if (CACHE_CTL & CACHE_CTL_ENABLE)
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{
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outl(inl(0xf000f044) | 0x2, 0xf000f044);
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while ((CACHE_CTL & 0x8000) != 0);
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CACHE_OPERATION |= CACHE_OP_FLUSH;
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while ((CACHE_CTL & CACHE_CTL_BUSY) != 0);
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}
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}
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void invalidate_icache(void) ICODE_ATTR;
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void invalidate_icache(void)
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{
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if (CACHE_CTL & CACHE_ENABLE)
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if (CACHE_CTL & CACHE_CTL_ENABLE)
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{
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unsigned i;
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outl(inl(0xf000f044) | 0x6, 0xf000f044);
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while ((CACHE_CTL & 0x8000) != 0);
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CACHE_OPERATION |= CACHE_OP_FLUSH | CACHE_OP_INVALIDATE;
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while ((CACHE_CTL & CACHE_CTL_BUSY) != 0);
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for (i = 0x10000000; i < 0x10002000; i += 16)
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inb(i);
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}
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@ -112,17 +112,16 @@ static void init_cache(void)
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unsigned i;
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/* cache init mode? */
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CACHE_CTL |= CACHE_INIT;
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CACHE_CTL |= CACHE_CTL_INIT;
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/* what's this do? */
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outl(inl(0x60006044) | (CURRENT_CORE == CPU ? 0x10 : 0x20),
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0x60006044);
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CACHE_PRIORITY |= CURRENT_CORE == CPU ? 0x10 : 0x20;
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outl(0xc00, 0xf000f040);
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outl(0xfc0, 0xf000f044);
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CACHE_MASK = 0xc00;
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CACHE_OPERATION = 0xfc0;
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/* enable cache */
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CACHE_CTL |= CACHE_INIT | CACHE_ENABLE | CACHE_RUN;
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CACHE_CTL |= CACHE_CTL_INIT | CACHE_CTL_ENABLE | CACHE_CTL_RUN;
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/* fill cache from physical address - do we have a better candidate for
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an 8KB unchanging memory range? */
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@ -285,14 +284,14 @@ void system_reboot(void)
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{
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/* Reboot */
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#ifdef SANSA_C200
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CACHE_CTL &= ~0x10;
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CACHE_CTL &= ~CACHE_CTL_VECT_REMAP;
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pp_i2c_send( 0x46, 0x23, 0x0); /* backlight off */
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/* Magic used by the c200 OF: 0x23066000
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Magic used by the c200 BL: 0x23066b7b
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In both cases, the OF executes these 2 commands from iram. */
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outl(0x23066b7b, 0x70000008);
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outl(0x23066b7b, STRAP_OPT_A);
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DEV_RS = DEV_SYSTEM;
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#else
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DEV_RS |= DEV_SYSTEM;
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