s5l870x : use mmu-arm.S
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25634 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Rafaël Carré
parent
680fcd827d
commit
f6ae574ac6
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@ -1369,7 +1369,7 @@ target/arm/tcc780x/cowond2/audio-cowond2.c
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#ifdef CPU_S5L870X
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target/arm/s5l8700/system-s5l8700.c
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target/arm/s5l8700/mmu-s5l8700.S
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target/arm/mmu-arm.S
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#ifndef SIMULATOR
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#ifndef BOOTLOADER
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target/arm/s5l8700/timer-s5l8700.c
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@ -20,6 +20,8 @@
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#ifndef __AS3525_H__
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#define __AS3525_H__
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#define CACHEALIGN_BITS (5)
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#define UART_CHANNELS 1
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@ -21,6 +21,8 @@
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#ifndef __S3C2440_H__
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#define __S3C2440_H__
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#define CACHEALIGN_BITS (5)
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#define LCD_BUFFER_SIZE (320*240*2)
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#define TTB_SIZE (0x4000)
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/* must be 16Kb (0x4000) aligned */
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@ -22,7 +22,6 @@
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#include "cpu.h"
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/* Used by ARMv4 & ARMv5 CPUs with cp15 register and MMU */
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/* WARNING : assume size of a data cache line == 32 bytes */
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#if CONFIG_CPU == TCC7801 || CONFIG_CPU == AT91SAM9260
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/* MMU present but unused */
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@ -40,19 +39,38 @@
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#define USE_MMU
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#define CACHE_SIZE 16
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#elif CONFIG_CPU == S5L8701
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/* MMU not present */
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#define CACHE_SIZE 4
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#else
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#error Cache settings unknown for this CPU !
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#endif /* CPU specific configuration */
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@ Index format: 31:26 = index, N:5 = segment, remainder = SBZ
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@ assume 64-way set associative separate I/D caches, 32B (2^5) cache line size
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@ assume 64-way set associative separate I/D caches
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@ CACHE_SIZE = N (kB) = N*2^10 B
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@ number of lines = N*2^(10-5) = N*2^(5)
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@ number of lines = N*2^(10-CACHEALIGN_BITS)
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@ Index bits = 6
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@ Segment loops = N*2^(5-6) = N*2^(-1) = N/2
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@ Segment loops = N*2^(10-CACHEALIGN_BITS-6) = N*2^(4-CACHEALIGN_BITS)
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@ Segment loops = N/2^(CACHEALIGN_BITS - 4)
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@ Segment loops = N/(1<<(CACHEALIGN_BITS - 4))
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#ifdef CACHE_SIZE
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#if CACHEALIGN_BITS == 4
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#define INDEX_STEPS CACHE_SIZE
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#elif CACHEALIGN_BITS == 5
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#define INDEX_STEPS (CACHE_SIZE/2)
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#endif /* CACHEALIGN_BITS */
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@ assume 64-way set associative separate I/D caches (log2(64) == 6)
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@ Index format: 31:26 = index, M:N = segment, remainder = SBZ
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@ Segment bits = log2(cache size in bytes / cache line size in byte) - Index bits (== 6)
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@ N = CACHEALIGN_BITS
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#endif /* CACHE_SIZE */
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#ifdef USE_MMU
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@ -318,15 +336,13 @@ cpucache_flush:
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bne clean_dcache
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mov r1, #0
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#else
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@ Index format: 31:26 = index, N:5 = segment, remainder = SBZ, assume 64-way set associative separate I/D caches
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@ N = log2(cache size in bytes / cache line size in bytes == 32) - 6 /* index bits */ + 4 /* start offset */
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mov r1, #0x00000000 @
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1: @ clean_start @
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mcr p15, 0, r1, c7, c10, 2 @ Clean entry by index
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add r0, r1, #0x00000020 @
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add r0, r1, #(1<<CACHEALIGN_BITS)
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mcr p15, 0, r0, c7, c10, 2 @ Clean entry by index
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.rept INDEX_STEPS - 2 /* 2 steps already executed */
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add r0, r0, #0x00000020 @
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add r0, r0, #(1<<CACHEALIGN_BITS)
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mcr p15, 0, r0, c7, c10, 2 @ Clean entry by index
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.endr
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adds r1, r1, #0x04000000 @ will wrap to zero at loop end
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@ -351,15 +367,13 @@ invalidate_dcache:
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bne invalidate_dcache
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mov r1, #0
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#else
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@ Index format: 31:26 = index, N:5 = segment, remainder = SBZ, assume 64-way set associative separate I/D caches
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@ N = log2(cache size in bytes / cache line size in bytes == 32) - 6 /* index bits */ + 4 /* start offset */
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mov r1, #0x00000000 @
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1: @ inv_start @
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mcr p15, 0, r1, c7, c14, 2 @ Clean and invalidate entry by index
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add r0, r1, #0x00000020 @
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add r0, r1, #(1<<CACHEALIGN_BITS)
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mcr p15, 0, r0, c7, c14, 2 @ Clean and invalidate entry by index
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.rept INDEX_STEPS - 2 /* 2 steps already executed */
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add r0, r0, #0x00000020 @
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add r0, r0, #(1<<CACHEALIGN_BITS)
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mcr p15, 0, r0, c7, c14, 2 @ Clean and invalidate entry by index
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.endr
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adds r1, r1, #0x04000000 @ will wrap to zero at loop end
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@ -1,95 +0,0 @@
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/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2006,2007 by Greg White
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include "config.h"
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#include "cpu.h"
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/** Cache coherency **/
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/*
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* Cleans entire DCache
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* void clean_dcache(void);
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*/
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.section .icode, "ax", %progbits
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.align 2
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.global clean_dcache
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.type clean_dcache, %function
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.global cpucache_flush @ Alias
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clean_dcache:
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cpucache_flush:
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@ Index format: 31:26 = index, 5:4 = segment, remainder = SBZ
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mov r1, #0x00000000 @
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1: @ clean_start @
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mcr p15, 0, r1, c7, c10, 2 @ Clean entry by index
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add r0, r1, #0x00000010 @
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mcr p15, 0, r0, c7, c10, 2 @ Clean entry by index
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add r0, r0, #0x00000010 @
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mcr p15, 0, r0, c7, c10, 2 @ Clean entry by index
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add r0, r0, #0x00000010 @
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mcr p15, 0, r0, c7, c10, 2 @ Clean entry by index
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adds r1, r1, #0x04000000 @ will wrap to zero at loop end
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bne 1b @ clean_start @
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mcr p15, 0, r1, c7, c10, 4 @ Drain write buffer
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bx lr @
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.size clean_dcache, .-clean_dcache
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/*
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* Invalidate entire DCache
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* will do writeback
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* void invalidate_dcache(void);
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*/
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.section .icode, "ax", %progbits
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.align 2
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.global invalidate_dcache
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.type invalidate_dcache, %function
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invalidate_dcache:
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@ Index format: 31:26 = index, 5:4 = segment, remainder = SBZ
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mov r1, #0x00000000 @
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1: @ inv_start @
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mcr p15, 0, r1, c7, c14, 2 @ Clean and invalidate entry by index
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add r0, r1, #0x00000010 @
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mcr p15, 0, r0, c7, c14, 2 @ Clean and invalidate entry by index
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add r0, r0, #0x00000010 @
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mcr p15, 0, r0, c7, c14, 2 @ Clean and invalidate entry by index
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add r0, r0, #0x00000010 @
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mcr p15, 0, r0, c7, c14, 2 @ Clean and invalidate entry by index
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adds r1, r1, #0x04000000 @ will wrap to zero at loop end
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bne 1b @ inv_start @
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mcr p15, 0, r1, c7, c10, 4 @ Drain write buffer
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bx lr @
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.size invalidate_dcache, .-invalidate_dcache
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/*
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* Invalidate entire ICache and DCache
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* will do writeback
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* void invalidate_idcache(void);
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*/
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.section .icode, "ax", %progbits
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.align 2
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.global invalidate_idcache
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.type invalidate_idcache, %function
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.global cpucache_invalidate @ Alias
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invalidate_idcache:
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cpucache_invalidate:
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mov r2, lr @ save lr to r2, call uses r0 and r1 only
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bl invalidate_dcache @ Clean and invalidate entire DCache
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mcr p15, 0, r1, c7, c5, 0 @ Invalidate ICache (r1=0 from call)
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mov pc, r2 @
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.size invalidate_idcache, .-invalidate_idcache
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@ -1,43 +0,0 @@
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/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2006,2007 by Greg White
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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/* This file MUST be included in your system-target.h file if you want arm
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* cache coherence functions to be called (I.E. during codec load, etc).
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*/
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#ifndef MMU_S5L8700_H
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#define MMU_S5L8700_H
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/* Cleans entire DCache */
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void clean_dcache(void) ICODE_ATTR;
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/* Invalidate entire DCache */
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/* will do writeback */
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void invalidate_dcache(void) ICODE_ATTR;
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/* Invalidate entire ICache and DCache */
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/* will do writeback */
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void invalidate_idcache(void) ICODE_ATTR;
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#define HAVE_CPUCACHE_INVALIDATE
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#define HAVE_CPUCACHE_FLUSH
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#endif /* MMU_S5L8700_H */
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