560 lines
24 KiB
C
560 lines
24 KiB
C
/*
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* (C) Copyright 2006
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* Copyright (C) 2006 Austriamicrosystems, by thomas.luo
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __AS3525_H__
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#define __AS3525_H__
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#define CACHEALIGN_BITS (5)
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#define UART_CHANNELS 1
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#if MEMORYSIZE <= 2
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/* we put the codec buffer in IRAM */
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#define AMS_LOWMEM
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#endif
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/* Virtual addresses */
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#define DRAM_ORIG 0x30000000
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#define IRAM_ORIG (DRAM_ORIG + DRAM_SIZE) /* IRAM is mapped just next to DRAM */
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#define DRAM_SIZE (MEMORYSIZE * 0x100000)
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#define IRAM_SIZE 0x50000
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/* AS352X only supports 512 Byte HW ECC */
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#define ECCSIZE 512
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#define ECCBYTES 3
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/* AS352X MMU Page Table Entries */
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#define TTB_SIZE 0x4000
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#define TTB_BASE_ADDR (DRAM_ORIG + DRAM_SIZE - TTB_SIZE)
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/* AS352X device base addresses */
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/*
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------------------------------------------------------------------------
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* AS352X Registers
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*
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------------------------------------------------------------------------
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*
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*/
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/* AHB */
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#define USB_BASE 0xC6000000
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#define OTGBASE USB_BASE
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#define VIC_BASE 0xC6010000
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#define DMAC_BASE 0xC6020000
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#define MPMC_BASE 0xC6030000
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#define MEMSTICK_BASE 0xC6040000
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#define CF_IDE_BASE 0xC6050000
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/* APB */
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#define NAND_FLASH_BASE 0xC8000000
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#define BIST_MANAGER_BASE 0xC8010000
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#define SD_MCI_BASE 0xC8020000
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#define TIMER_BASE 0xC8040000
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#define WDT_BASE 0xC8050000
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#define I2C_MS_BASE 0xC8060000
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#define I2C_AUDIO_BASE 0xC8070000
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#define SSP_BASE 0xC8080000
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#define I2SIN_BASE 0xC8090000
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#define I2SOUT_BASE 0xC80A0000
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#define GPIOA_BASE 0xC80B0000
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#define GPIOB_BASE 0xC80C0000
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#define GPIOC_BASE 0xC80D0000
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#define GPIOD_BASE 0xC80E0000
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#define CGU_BASE 0xC80F0000
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#define CCU_BASE 0xC8100000
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#define UART0_BASE 0xC8110000
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#define DBOP_BASE 0xC8120000
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/*
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------------------------------------------------------------------------
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* AS352X control registers
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*
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------------------------------------------------------------------------
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*/
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#define CCU_SRC (*(volatile unsigned long *)(CCU_BASE + 0x00))
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#define CCU_SRL (*(volatile unsigned long *)(CCU_BASE + 0x04))
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#define CCU_MEMMAP (*(volatile unsigned long *)(CCU_BASE + 0x08))
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#define CCU_IO (*(volatile unsigned long *)(CCU_BASE + 0x0C))
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#define CCU_SCON (*(volatile unsigned long *)(CCU_BASE + 0x10))
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#define CCU_VERS (*(volatile unsigned long *)(CCU_BASE + 0x14))
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#define CCU_SPARE1 (*(volatile unsigned long *)(CCU_BASE + 0x18))
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#define CCU_SPARE2 (*(volatile unsigned long *)(CCU_BASE + 0x1C))
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/* DBOP */
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#define DBOP_TIMPOL_01 (*(volatile unsigned long *)(DBOP_BASE + 0x00))
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#define DBOP_TIMPOL_23 (*(volatile unsigned long *)(DBOP_BASE + 0x04))
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#define DBOP_CTRL (*(volatile unsigned long *)(DBOP_BASE + 0x08))
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#define DBOP_STAT (*(volatile unsigned long *)(DBOP_BASE + 0x0C))
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/* default is 16bit, but we switch to 32bit for some targets for better speed */
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#define DBOP_DOUT8 (*(volatile unsigned char*)(DBOP_BASE + 0x10))
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#define DBOP_DOUT (*(volatile unsigned short*)(DBOP_BASE + 0x10))
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#define DBOP_DOUT16 (*(volatile unsigned short*)(DBOP_BASE + 0x10))
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#define DBOP_DOUT32 (*(volatile unsigned long *)(DBOP_BASE + 0x10))
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#define DBOP_DIN (*(volatile unsigned short*)(DBOP_BASE + 0x14))
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/**
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* Reset Control Lines in CCU_SRC register
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**/
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#define CCU_SRC_DBOP_EN ( 1 << 24 )
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#define CCU_SRC_SPDIF_EN ( 1 << 22 )
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#define CCU_SRC_TIMER_EN ( 1 << 21 )
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#define CCU_SRC_SSP_EN ( 1 << 20 )
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#define CCU_SRC_WDO_EN ( 1 << 19 )
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#define CCU_SRC_IDE_EN ( 1 << 18 )
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#define CCU_SRC_IDE_AHB_EN ( 1 << 17 )
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#define CCU_SRC_UART0 ( 1 << 16 )
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#define CCU_SRC_NAF_EN ( 1 << 15 )
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#define CCU_SRC_SDMCI_EN ( 1 << 14 )
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#define CCU_SRC_GPIO_EN ( 1 << 13 )
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#define CCU_SRC_I2C_AUDIO_EN ( 1 << 12 )
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#define CCU_SRC_I2C_EN ( 1 << 11 )
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#define CCU_SRC_MST_EN ( 1 << 10 )
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#define CCU_SRC_I2SIN ( 1 << 9 )
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#define CCU_SRC_I2SOUT ( 1 << 8 )
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#define CCU_SRC_USB_AHB_EN ( 1 << 7 )
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#define CCU_SRC_USB_PHY_EN ( 1 << 6 )
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#define CCU_SRC_DMAC_EN ( 1 << 5 )
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#define CCU_SRC_VIC_EN ( 1 << 4 )
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/**
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* Magic number for CCU_SRL for reset.
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**/
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#define CCU_SRL_MAGIC_NUMBER 0x1A720212
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/**
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* Chip select lines for NAF. Use these constants to select/deselct the
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CE lines
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* for NAND flashes in Register CCU_IO.
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**/
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#define CCU_IO_NAF_CE_LINE_0 ( 0 << 7 )
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#define CCU_IO_NAF_CE_LINE_1 ( 1 << 7 )
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#define CCU_IO_NAF_CE_LINE_2 ( 2 << 7 )
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#define CCU_IO_NAF_CE_LINE_3 ( 3 << 7 )
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/* CCU IO Select/Deselect IDE */
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#define CCU_IO_IDE ( 1 << 5 )
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/* CCU IO Select/desect I2C */
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#define CCU_IO_I2C_MASTER_SLAVE ( 1 << 1 )
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/* CCU IO Select/desect UART */
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#define CCU_IO_UART0 ( 1 << 0 )
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#define CCU_RESET_ALL_BUT_MEMORY \
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( CCU_SRC_DBOP_EN \
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| CCU_SRC_SPDIF_EN \
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| CCU_SRC_TIMER_EN \
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| CCU_SRC_SSP_EN \
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| CCU_SRC_WDO_EN \
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| CCU_SRC_IDE_EN \
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| CCU_SRC_IDE_AHB_EN \
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| CCU_SRC_UART0 \
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| CCU_SRC_NAF_EN \
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| CCU_SRC_SDMCI_EN \
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| CCU_SRC_GPIO_EN \
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| CCU_SRC_I2C_AUDIO_EN \
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| CCU_SRC_I2C_EN \
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| CCU_SRC_MST_EN \
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| CCU_SRC_I2SIN \
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| CCU_SRC_I2SOUT \
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| CCU_SRC_USB_AHB_EN \
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| CCU_SRC_USB_PHY_EN \
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| CCU_SRC_DMAC_EN \
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| CCU_SRC_VIC_EN \
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)
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#define CCU_IO_UART ( 1 << 0 )
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/*
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------------------------------------------------------------------------
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* AS352X clock control registers
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*
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------------------------------------------------------------------------
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*/
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#define CGU_PLLA (*(volatile unsigned long *)(CGU_BASE + 0x00))
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#define CGU_PLLB (*(volatile unsigned long *)(CGU_BASE + 0x04))
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#define CGU_PLLASUP (*(volatile unsigned long *)(CGU_BASE + 0x08))
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#define CGU_PLLBSUP (*(volatile unsigned long *)(CGU_BASE + 0x0C))
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#define CGU_PROC (*(volatile unsigned long *)(CGU_BASE + 0x10))
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#define CGU_PERI (*(volatile unsigned long *)(CGU_BASE + 0x14))
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#define CGU_AUDIO (*(volatile unsigned long *)(CGU_BASE + 0x18))
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#define CGU_USB (*(volatile unsigned long *)(CGU_BASE + 0x1C))
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#define CGU_INTCTRL (*(volatile unsigned long *)(CGU_BASE + 0x20))
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#define CGU_IRQ (*(volatile unsigned long *)(CGU_BASE + 0x24))
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#define CGU_COUNTA (*(volatile unsigned long *)(CGU_BASE + 0x28))
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#define CGU_COUNTB (*(volatile unsigned long *)(CGU_BASE + 0x2C))
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#define CGU_IDE (*(volatile unsigned long *)(CGU_BASE + 0x30))
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#define CGU_MEMSTICK (*(volatile unsigned long *)(CGU_BASE + 0x34))
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#define CGU_DBOP (*(volatile unsigned long *)(CGU_BASE + 0x38))
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#define CGU_VIC_CLOCK_ENABLE ( 1 << 23 ) /* vic */
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/* --- are disabled after reset --- */
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#define CGU_EXTMEM_CLOCK_ENABLE ( 1 << 27 ) /* external memory */
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#define CGU_EXTMEMIF_CLOCK_ENABLE ( 1 << 26 ) /* ext mem AHB IF */
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#define CGU_ROM_ENABLE ( 1 << 24 ) /* internal ROM */
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#define CGU_DMA_CLOCK_ENABLE ( 1 << 22 ) /* dma */
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#define CGU_USB_CLOCK_ENABLE ( 1 << 21 ) /* usb */
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#define CGU_I2SOUT_APB_CLOCK_ENABLE ( 1 << 20 ) /* i2sout */
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#define CGU_I2SIN_APB_CLOCK_ENABLE ( 1 << 19 ) /* i2sin */
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#define CGU_I2C_MASTER_SLAVE_CLOCK_ENABLE ( 1 << 18 ) /* i2c master/slave */
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#define CGU_I2C_AUDIO_MASTER_CLOCK_ENABLE ( 1 << 17 ) /* i2c audio master */
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#define CGU_GPIO_CLOCK_ENABLE ( 1 << 16 ) /* gpio */
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#define CGU_MCI_CLOCK_ENABLE ( 1 << 15 ) /* mmc + sd */
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#define CGU_NAF_CLOCK_ENABLE ( 1 << 14 ) /* naf */
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#define CGU_UART_APB_CLOCK_ENABLE ( 1 << 13 ) /* uart */
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#define CGU_WDOCNT_CLOCK_ENABLE ( 1 << 12 ) /* watchdog counter */
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#define CGU_WDOIF_CLOCK_ENABLE ( 1 << 11 ) /* watchdog timer module */
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#define CGU_SSP_CLOCK_ENABLE ( 1 << 10 ) /* ssp */
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#define CGU_TIMER1_CLOCK_ENABLE ( 1 << 9 ) /* timer 1 */
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#define CGU_TIMER2_CLOCK_ENABLE ( 1 << 8 ) /* timer 2 */
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#define CGU_TIMERIF_CLOCK_ENABLE ( 1 << 7 ) /* timer interface */
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/* CGU_PLL[AB]SUP bits */
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#define CGU_PLL_POWERDOWN ( 1 << 3 )
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/* CGU_INTCTRL bits */
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#define CGU_PLLA_LOCK ( 1 << 0 )
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#define CGU_PLLB_LOCK ( 1 << 1 )
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/** ------------------------------------------------------------------
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* Number of cycles to wait before cgu is safely locked.
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**/
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#define CGU_LOCK_CNT 0xFF
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/* FIFO depth is 16 for tx and rx fifo */
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#define UART_FIFO_DEPTH 16
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/* ------------------- UART Line Control Register bit fields -------------------- */
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#define UART_LNCTL_DLSEN (1 << 7) /* Device latch select bit */
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/* -------------- UART Interrupt Control Register bit fields --------------- */
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#define UART_INTR_RXDRDY 0x1 /* Data ready interrupt */
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#define UART_INTR_TXEMT 0x2 /* Transmit data empty interrupt */
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#define UART_INTR_RXLINESTATUS 0x4 /* Receive line status interrupt */
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/* ------------------- UART Line Status Register bit fields -------------------- */
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#define UART_ERRORBITS 0x1E
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#define UART_RX_DATA_READY (1 << 0)
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#define UART_TX_HOLD_EMPTY (1 << 5)
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/* ------------------- FIFO CNTL Register contants -------------------*/
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#define UART_FIFO_EN (1 << 0) /* Enable the UART FIFO */
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#define UART_TX_FIFO_RST (1 << 1) /* Enable the UART FIFO */
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#define UART_RX_FIFO_RST (1 << 2)
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#define UART_RXFIFO_TRIGLVL_1 (0 << 4) /* RX FIFO TRIGGER_LEVEL 1 */
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#define UART_RXFIFO_TRIGLVL_4 0x08 /* RX FIFO TRIGGER_LEVEL 4 */
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#define UART_RXFIFO_TRIGLVL_8 0x10 /* RX FIFO TRIGGER_LEVEL 8 */
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#define UART_RXFIFO_TRIGLVL_14 0x18 /* RX FIFO TRIGGER_LEVEL 14 */
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/* ------------------- FIFO status Register contants ------------------*/
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#define UART_TX_FIFO_FULL (1 << 0)
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#define UART_RX_FIFO_FULL (1 << 1)
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#define UART_TX_FIFO_EMPTY (1 << 2)
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#define UART_RX_FIFO_EMPTY (1 << 3)
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/* ----------------------- defines ---------------------------------------- */
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#define UART_DATA_REG (*(volatile unsigned long*)(UART0_BASE + 0x00)) /* Data register */
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#define UART_DLO_REG (*(volatile unsigned long*)(UART0_BASE + 0x00)) /* Clock divider(lower byte) register */
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#define UART_DHI_REG (*(volatile unsigned long*)(UART0_BASE + 0x04)) /* Clock divider(higher byte) register */
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#define UART_INTEN_REG (*(volatile unsigned long*)(UART0_BASE + 0x04)) /* Interrupt enable register */
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#define UART_INTSTATUS_REG (*(volatile unsigned long*)(UART0_BASE + 0x08)) /* Interrupt status register */
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#define UART_FCTL_REG (*(volatile unsigned long*)(UART0_BASE + 0x0C)) /* Fifo control register */
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#define UART_FSTATUS_REG (*(volatile unsigned long*)(UART0_BASE + 0x0C)) /* Fifo status register */
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#define UART_LNCTL_REG (*(volatile unsigned long*)(UART0_BASE + 0x10)) /* Line control register */
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#define UART_LNSTATUS_REG (*(volatile unsigned long*)(UART0_BASE + 0x14)) /* Line status register */
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#define SD_MCI_POWER (*(volatile unsigned long*)(SD_MCI_BASE + 0x0))
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#define TIMER1_LOAD (*(volatile unsigned long*)(TIMER_BASE + 0x00)) /* 32-bit width */
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#define TIMER1_VALUE (*(volatile unsigned long*)(TIMER_BASE + 0x04)) /* 32 bit width */
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#define TIMER1_CONTROL (*(volatile unsigned long*)(TIMER_BASE + 0x08)) /* 8 bit width */
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#define TIMER1_INTCLR (*(volatile unsigned long*)(TIMER_BASE + 0x0C)) /* clears ir by write access */
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#define TIMER1_RIS (*(volatile unsigned long*)(TIMER_BASE + 0x10)) /* 1 bit width */
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#define TIMER1_MIS (*(volatile unsigned long*)(TIMER_BASE + 0x14)) /* 1 bit width */
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#define TIMER1_BGLOAD (*(volatile unsigned long*)(TIMER_BASE + 0x18)) /* 32-bit width */
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#define TIMER2_LOAD (*(volatile unsigned long*)(TIMER_BASE + 0x20)) /* 32-bit width */
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#define TIMER2_VALUE (*(volatile unsigned long*)(TIMER_BASE + 0x24)) /* 32 bit width */
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#define TIMER2_CONTROL (*(volatile unsigned long*)(TIMER_BASE + 0x28)) /* 8 bit width */
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#define TIMER2_INTCLR (*(volatile unsigned long*)(TIMER_BASE + 0x2C)) /* clears ir by write access */
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#define TIMER2_RIS (*(volatile unsigned long*)(TIMER_BASE + 0x30)) /* 1 bit width */
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#define TIMER2_MIS (*(volatile unsigned long*)(TIMER_BASE + 0x34)) /* 1 bit width */
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#define TIMER2_BGLOAD (*(volatile unsigned long*)(TIMER_BASE + 0x38)) /* 32-bit width */
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/**
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* Counter/Timer control register bits
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**/
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#define TIMER_ENABLE 0x80
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#define TIMER_PERIODIC 0x40
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#define TIMER_INT_ENABLE 0x20
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#define TIMER_32_BIT 0x02
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#define TIMER_ONE_SHOT 0x01
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#define TIMER_PRESCALE_1 0x00
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#define TIMER_PRESCALE_16 0x04
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#define TIMER_PRESCALE_256 0x08
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/* Watchdog registers */
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#define WDT_LOAD (*(volatile unsigned long*)(WDT_BASE))
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#define WDT_CONTROL (*(volatile unsigned long*)(WDT_BASE+8))
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/* GPIO registers */
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#define GPIOA_DIR (*(volatile unsigned char*)(GPIOA_BASE+0x400))
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#define GPIOA_IS (*(volatile unsigned char*)(GPIOA_BASE+0x404))
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#define GPIOA_IBE (*(volatile unsigned char*)(GPIOA_BASE+0x408))
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#define GPIOA_IEV (*(volatile unsigned char*)(GPIOA_BASE+0x40C))
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#define GPIOA_IE (*(volatile unsigned char*)(GPIOA_BASE+0x410))
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#define GPIOA_RIS (*(volatile unsigned char*)(GPIOA_BASE+0x414))
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#define GPIOA_MIS (*(volatile unsigned char*)(GPIOA_BASE+0x418))
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#define GPIOA_IC (*(volatile unsigned char*)(GPIOA_BASE+0x41C))
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#define GPIOA_AFSEL (*(volatile unsigned char*)(GPIOA_BASE+0x420))
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#define GPIOA_PIN(a) (*(volatile unsigned char*)(GPIOA_BASE+(1<<((a)+2))))
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#define GPIOA_PIN_MASK(m) (*(volatile unsigned char *)(GPIOA_BASE+(((m)&0xff)<<2)))
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#define GPIOA_DATA (*(volatile unsigned char*)(GPIOA_BASE+(0xff<<2)))
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#define GPIOB_DIR (*(volatile unsigned char*)(GPIOB_BASE+0x400))
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#define GPIOB_IS (*(volatile unsigned char*)(GPIOB_BASE+0x404))
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#define GPIOB_IBE (*(volatile unsigned char*)(GPIOB_BASE+0x408))
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#define GPIOB_IEV (*(volatile unsigned char*)(GPIOB_BASE+0x40C))
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#define GPIOB_IE (*(volatile unsigned char*)(GPIOB_BASE+0x410))
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#define GPIOB_RIS (*(volatile unsigned char*)(GPIOB_BASE+0x414))
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#define GPIOB_MIS (*(volatile unsigned char*)(GPIOB_BASE+0x418))
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#define GPIOB_IC (*(volatile unsigned char*)(GPIOB_BASE+0x41C))
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#define GPIOB_AFSEL (*(volatile unsigned char*)(GPIOB_BASE+0x420))
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#define GPIOB_PIN(a) (*(volatile unsigned char*)(GPIOB_BASE+(1<<((a)+2))))
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#define GPIOB_PIN_MASK(m) (*(volatile unsigned char *)(GPIOB_BASE+(((m)&0xff)<<2)))
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#define GPIOB_DATA (*(volatile unsigned char*)(GPIOB_BASE+(0xff<<2)))
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#define GPIOC_DIR (*(volatile unsigned char*)(GPIOC_BASE+0x400))
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#define GPIOC_IS (*(volatile unsigned char*)(GPIOC_BASE+0x404))
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#define GPIOC_IBE (*(volatile unsigned char*)(GPIOC_BASE+0x408))
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#define GPIOC_IEV (*(volatile unsigned char*)(GPIOC_BASE+0x40C))
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#define GPIOC_IE (*(volatile unsigned char*)(GPIOC_BASE+0x410))
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#define GPIOC_RIS (*(volatile unsigned char*)(GPIOC_BASE+0x414))
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#define GPIOC_MIS (*(volatile unsigned char*)(GPIOC_BASE+0x418))
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#define GPIOC_IC (*(volatile unsigned char*)(GPIOC_BASE+0x41C))
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#define GPIOC_AFSEL (*(volatile unsigned char*)(GPIOC_BASE+0x420))
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#define GPIOC_PIN(a) (*(volatile unsigned char*)(GPIOC_BASE+(1<<((a)+2))))
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#define GPIOC_PIN_MASK(m) (*(volatile unsigned char *)(GPIOC_BASE+(((m)&0xff)<<2)))
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#define GPIOC_DATA (*(volatile unsigned char*)(GPIOC_BASE+(0xff<<2)))
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#define GPIOD_DIR (*(volatile unsigned char*)(GPIOD_BASE+0x400))
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#define GPIOD_IS (*(volatile unsigned char*)(GPIOD_BASE+0x404))
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#define GPIOD_IBE (*(volatile unsigned char*)(GPIOD_BASE+0x408))
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#define GPIOD_IEV (*(volatile unsigned char*)(GPIOD_BASE+0x40C))
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#define GPIOD_IE (*(volatile unsigned char*)(GPIOD_BASE+0x410))
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#define GPIOD_RIS (*(volatile unsigned char*)(GPIOD_BASE+0x414))
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#define GPIOD_MIS (*(volatile unsigned char*)(GPIOD_BASE+0x418))
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#define GPIOD_IC (*(volatile unsigned char*)(GPIOD_BASE+0x41C))
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#define GPIOD_AFSEL (*(volatile unsigned char*)(GPIOD_BASE+0x420))
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#define GPIOD_PIN(a) (*(volatile unsigned char*)(GPIOD_BASE+(1<<((a)+2))))
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#define GPIOD_PIN_MASK(m) (*(volatile unsigned char *)(GPIOD_BASE+(((m)&0xff)<<2)))
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#define GPIOD_DATA (*(volatile unsigned char*)(GPIOD_BASE+(0xff<<2)))
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/* ARM PL172 Memory Controller registers */
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#define MPMC_CONTROL (*(volatile unsigned long*)(MPMC_BASE+0x000))
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#define MPMC_STATUS (*(volatile unsigned long*)(MPMC_BASE+0x004))
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#define MPMC_CONFIG (*(volatile unsigned long*)(MPMC_BASE+0x008))
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#define MPMC_DYNAMIC_CONTROL (*(volatile unsigned long*)(MPMC_BASE+0x020))
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#define MPMC_DYNAMIC_REFRESH (*(volatile unsigned long*)(MPMC_BASE+0x024))
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#define MPMC_DYNAMIC_READ_CONFIG (*(volatile unsigned long*)(MPMC_BASE+0x028))
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#define MPMC_DYNAMIC_tRP (*(volatile unsigned long*)(MPMC_BASE+0x030))
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#define MPMC_DYNAMIC_tRAS (*(volatile unsigned long*)(MPMC_BASE+0x034))
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#define MPMC_DYNAMIC_tSREX (*(volatile unsigned long*)(MPMC_BASE+0x038))
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#define MPMC_DYNAMIC_tAPR (*(volatile unsigned long*)(MPMC_BASE+0x03C))
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#define MPMC_DYNAMIC_tDAL (*(volatile unsigned long*)(MPMC_BASE+0x040))
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#define MPMC_DYNAMIC_tWR (*(volatile unsigned long*)(MPMC_BASE+0x044))
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#define MPMC_DYNAMIC_tRC (*(volatile unsigned long*)(MPMC_BASE+0x048))
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#define MPMC_DYNAMIC_tRFC (*(volatile unsigned long*)(MPMC_BASE+0x04C))
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#define MPMC_DYNAMIC_tXSR (*(volatile unsigned long*)(MPMC_BASE+0x050))
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#define MPMC_DYNAMIC_tRRD (*(volatile unsigned long*)(MPMC_BASE+0x054))
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#define MPMC_DYNAMIC_tMRD (*(volatile unsigned long*)(MPMC_BASE+0x058))
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#define MPMC_STATIC_EXTENDED_WAIT (*(volatile unsigned long*)(MPMC_BASE+0x080))
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#define MPMC_DYNAMIC_CONFIG_0 (*(volatile unsigned long*)(MPMC_BASE+0x100))
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#define MPMC_DYNAMIC_CONFIG_1 (*(volatile unsigned long*)(MPMC_BASE+0x120))
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#define MPMC_DYNAMIC_CONFIG_2 (*(volatile unsigned long*)(MPMC_BASE+0x140))
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#define MPMC_DYNAMIC_CONFIG_3 (*(volatile unsigned long*)(MPMC_BASE+0x160))
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#define MPMC_DYNAMIC_RASCAS_0 (*(volatile unsigned long*)(MPMC_BASE+0x104))
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#define MPMC_DYNAMIC_RASCAS_1 (*(volatile unsigned long*)(MPMC_BASE+0x124))
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#define MPMC_DYNAMIC_RASCAS_2 (*(volatile unsigned long*)(MPMC_BASE+0x144))
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#define MPMC_DYNAMIC_RASCAS_3 (*(volatile unsigned long*)(MPMC_BASE+0x164))
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#define MPMC_PERIPH_ID2 (*(volatile unsigned long*)(MPMC_BASE+0xFE8))
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/* VIC controller (PL190) registers */
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#define VIC_IRQ_STATUS (*(volatile unsigned long*)(VIC_BASE+0x00))
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#define VIC_FIQ_STATUS (*(volatile unsigned long*)(VIC_BASE+0x04))
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#define VIC_RAW_INTR (*(volatile unsigned long*)(VIC_BASE+0x08))
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#define VIC_INT_SELECT (*(volatile unsigned long*)(VIC_BASE+0x0C))
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#define VIC_INT_ENABLE (*(volatile unsigned long*)(VIC_BASE+0x10))
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#define VIC_INT_EN_CLEAR (*(volatile unsigned long*)(VIC_BASE+0x14))
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#define VIC_SOFT_INT (*(volatile unsigned long*)(VIC_BASE+0x18))
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#define VIC_SOFT_INT_CLEAR (*(volatile unsigned long*)(VIC_BASE+0x1C))
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#define VIC_PROTECTION (*(volatile unsigned long*)(VIC_BASE+0x20))
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#define VIC_VECT_ADDR ((void (* volatile *) (void)) (VIC_BASE+0x30))
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#define VIC_DEF_VECT_ADDR ((void (* volatile *) (void)) (VIC_BASE+0x34))
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#define VIC_VECT_ADDRS ((void (* volatile *) (void)) (VIC_BASE+0x100))
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#define VIC_VECT_CNTLS ((volatile unsigned long*)(VIC_BASE+0x200))
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/* Interrupt sources (for vectors setup) */
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#define INT_SRC_WATCHDOG 0
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#define INT_SRC_TIMER1 1
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#define INT_SRC_TIMER2 2
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#define INT_SRC_USB 3
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#define INT_SRC_DMAC 4
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#define INT_SRC_NAND 5
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#define INT_SRC_IDE 6
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#define INT_SRC_MCI0 7
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#define INT_SRC_MCI1 8
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#define INT_SRC_AUDIO 9
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#define INT_SRC_SSP 10
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#define INT_SRC_I2C_MS 11
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#define INT_SRC_I2C_AUDIO 12
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#define INT_SRC_I2SIN 13
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#define INT_SRC_I2SOUT 14
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#define INT_SRC_UART 15
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#define INT_SRC_GPIOD 16
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/* 17 reserved */
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#define INT_SRC_CGU 18
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#define INT_SRC_MEMORY_STICK 19
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#define INT_SRC_DBOP 20
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/* 21-28 reserved */
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#define INT_SRC_GPIOA 29
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#define INT_SRC_GPIOB 30
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#define INT_SRC_GPIOC 31
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/* Interrupt sources bitmask */
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#define INTERRUPT_WATCHDOG (1<<0)
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#define INTERRUPT_TIMER1 (1<<1)
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#define INTERRUPT_TIMER2 (1<<2)
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#define INTERRUPT_USB (1<<3)
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#define INTERRUPT_DMAC (1<<4)
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#define INTERRUPT_NAND (1<<5)
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#define INTERRUPT_IDE (1<<6)
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#define INTERRUPT_MCI0 (1<<7)
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#define INTERRUPT_MCI1 (1<<8)
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#define INTERRUPT_AUDIO (1<<9)
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#define INTERRUPT_SSP (1<<10)
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#define INTERRUPT_I2C_MS (1<<11)
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#define INTERRUPT_I2C_AUDIO (1<<12)
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#define INTERRUPT_I2SIN (1<<13)
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#define INTERRUPT_I2SOUT (1<<14)
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#define INTERRUPT_UART (1<<15)
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#define INTERRUPT_GPIOD (1<<16)
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/* 17 reserved */
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#define INTERRUPT_CGU (1<<18)
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#define INTERRUPT_MEMORY_STICK (1<<19)
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#define INTERRUPT_DBOP (1<<20)
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/* 21-28 reserved */
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#define INTERRUPT_GPIOA (1<<29)
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#define INTERRUPT_GPIOB (1<<30)
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#define INTERRUPT_GPIOC (1<<31)
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/* I2SOUT registers */
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#define I2SOUT_CONTROL (*(volatile unsigned char*)(I2SOUT_BASE+0x00))
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#define I2SOUT_MASK (*(volatile unsigned char*)(I2SOUT_BASE+0x04))
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#define I2SOUT_RAW_STATUS (*(volatile unsigned char*)(I2SOUT_BASE+0x08))
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#define I2SOUT_STATUS (*(volatile unsigned char*)(I2SOUT_BASE+0x0C))
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#define I2SOUT_CLEAR (*(volatile unsigned char*)(I2SOUT_BASE+0x10))
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#define I2SOUT_DATA (volatile unsigned long*)(I2SOUT_BASE+0x14)
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/* SSP registers (PrimeCell PL022) */
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#define SSP_CR0 (*(volatile unsigned short*)(SSP_BASE+0x00))
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#define SSP_CR1 (*(volatile unsigned char*)(SSP_BASE+0x04))
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#define SSP_DATA (*(volatile unsigned short*)(SSP_BASE+0x08))
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#define SSP_SR (*(volatile unsigned char*)(SSP_BASE+0x0C))
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#define SSP_CPSR (*(volatile unsigned char*)(SSP_BASE+0x10))
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#define SSP_IMSC (*(volatile unsigned char*)(SSP_BASE+0x14))
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#define SSP_IRS (*(volatile unsigned char*)(SSP_BASE+0x18))
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#define SSP_MIS (*(volatile unsigned char*)(SSP_BASE+0x1C))
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#define SSP_ICR (*(volatile unsigned char*)(SSP_BASE+0x20))
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#define SSP_DMACR (*(volatile unsigned char*)(SSP_BASE+0x24))
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/* PCM addresses for obtaining buffers will be what DMA is using (physical) */
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#define HAVE_PCM_DMA_ADDRESS
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/* Timer frequency */
|
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#define TIMER_FREQ (24000000 / 16)
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/* USB */
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#define USB_NUM_ENDPOINTS 4
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#define USB_DEVBSS_ATTR
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/* I2SIN registers */
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#define I2SIN_CONTROL (*(volatile unsigned long*)(I2SIN_BASE+0x00))
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#define I2SIN_MASK (*(volatile unsigned char*)(I2SIN_BASE+0x04))
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#define I2SIN_RAW_STATUS (*(volatile unsigned char*)(I2SIN_BASE+0x08))
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#define I2SIN_STATUS (*(volatile unsigned char*)(I2SIN_BASE+0x0C))
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#define I2SIN_CLEAR (*(volatile unsigned char*)(I2SIN_BASE+0x10))
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#define I2SIN_DATA (volatile unsigned long*)(I2SIN_BASE+0x14)
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#define I2SIN_SPDIF_STATUS (*(volatile unsigned long*)(I2SIN_BASE+0x18))
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/* I2SIN_MASK */
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#define I2SIN_MASK_PUER ( 1<<6 ) /* push error */
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#define I2SIN_MASK_POE ( 1<<5 ) /* empty */
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#define I2SIN_MASK_POAE ( 1<<4 ) /* almost empty */
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#define I2SIN_MASK_POHF ( 1<<3 ) /* half full */
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#define I2SIN_MASK_POAF ( 1<<2 ) /* almost full */
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#define I2SIN_MASK_POF ( 1<<1 ) /* full */
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#define I2SIN_MASK_POER ( 1<<0 ) /* pop error */
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#endif /*__AS3525_H__*/
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