210 lines
7.1 KiB
C
210 lines
7.1 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2011 by Amaury Pouly
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#ifndef __IMX233_H__
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#define __IMX233_H__
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#ifndef IMX233_SUBTARGET
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#error You must define IMX233_SUBTARGET to select the chip family
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#endif
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#ifndef IMX233_PACKAGE
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#error You must IMX233_PACKAGE to select the chip package
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#endif
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/*
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* Chip Memory Map (stmp3700,imx233):
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* 0x00000000 - 0x00007fff: on chip ram
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* 0x40000000 - 0x5fffffff: dram (512Mb max)
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* 0x80000000 - 0x80100000: memory mapped registers
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* We use the following map:
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* 0x60000000 - 0x7fffffff: dram (cached)
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* 0x90000000 - 0xafffffff: dram (buffered)
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* everything else : identity mapped (uncached)
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*
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* Chip Memory Map (stmp3600):
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* 0x00000000 - 0x00007fff: on chip ram
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* 0x60000000 - 0x7fffffff: dram (512Mb max)
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* 0x80000000 - 0x80100000: memory mapped registers
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* We use the following map:
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* 0x40000000 - 0x5fffffff: dram (cached)
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* 0x90000000 - 0xafffffff: dram (buffered)
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* everything else : identity mapped (uncached)
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*
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* As a side note it's important to notice that uncached dram is identity mapped
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*/
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#define IRAM_ORIG 0
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#if IMX233_SUBTARGET >= 3780
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#define IRAM_SIZE (32 * 1024)
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#elif IMX233_SUBTARGET >= 3770
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#define IRAM_SIZE (512 * 1024)
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#else
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#define IRAM_SIZE (256 * 1024)
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#endif
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#if IMX233_SUBTARGET >= 3700
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#define DRAM_ORIG 0x40000000
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#else
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#define DRAM_ORIG 0x60000000
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#endif
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#define DRAM_SIZE (MEMORYSIZE * 0x100000)
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#if IMX233_SUBTARGET >= 3700
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#define UNCACHED_DRAM_ADDR 0x40000000
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#define CACHED_DRAM_ADDR 0x60000000
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#define BUFFERED_DRAM_ADDR 0x90000000
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#else
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#define UNCACHED_DRAM_ADDR 0x60000000
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#define CACHED_DRAM_ADDR 0x40000000
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#define BUFFERED_DRAM_ADDR 0x90000000
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#endif
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/* 32 bytes per cache line */
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#define CACHEALIGN_SIZE 32
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#define CACHEALIGN_BITS 5
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#define NOCACHE_BASE (UNCACHED_DRAM_ADDR - CACHED_DRAM_ADDR)
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#define __IN_RANGE(type, a) (type##_DRAM_ADDR <= (a) && (a) < (type##_DRAM_ADDR + DRAM_SIZE))
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#define PHYSICAL_ADDR(a) \
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((typeof(a))(__IN_RANGE(BUFFERED, (uintptr_t)(a)) ? \
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((uintptr_t)(a) - BUFFERED_DRAM_ADDR + UNCACHED_DRAM_ADDR) \
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:__IN_RANGE(CACHED, (uintptr_t)(a)) ? \
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((uintptr_t)(a) - CACHED_DRAM_ADDR + UNCACHED_DRAM_ADDR) \
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:(uintptr_t)(a)))
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#define UNCACHED_ADDR(a) PHYSICAL_ADDR(a)
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#define TTB_BASE_ADDR (DRAM_ORIG + DRAM_SIZE - TTB_SIZE)
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#define TTB_SIZE 0x4000
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#define TTB_BASE ((unsigned long *)TTB_BASE_ADDR)
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/* align to cache line */
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#ifndef IMX233_FRAMEBUFFER_SIZE
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#define IMX233_FRAMEBUFFER_SIZE (LCD_WIDTH * LCD_HEIGHT * LCD_DEPTH / 8)
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#endif
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#define FRAME_SIZE ((IMX233_FRAMEBUFFER_SIZE + CACHEALIGN_SIZE - 1) & ~(CACHEALIGN_SIZE - 1))
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#define FRAME_PHYS_ADDR (DRAM_ORIG + DRAM_SIZE - TTB_SIZE - FRAME_SIZE)
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#define FRAME ((void *)(FRAME_PHYS_ADDR - UNCACHED_DRAM_ADDR + BUFFERED_DRAM_ADDR))
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/* Timer runs at 32KHz, derived from clk32k@32KHz */
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#define TIMER_FREQ 32000
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/* USBOTG */
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#define USB_QHARRAY_ATTR __attribute__((section(".qharray"),nocommon,aligned(2048)))
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#define USB_NUM_ENDPOINTS 5
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/* STMP3600 doesn't have the bandwidth to put buffer in SDRAM */
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#if IMX233_SUBTARGET < 3700
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#define USB_DEVBSS_ATTR IBSS_ATTR
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#else
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#define USB_DEVBSS_ATTR NOCACHEBSS_ATTR
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#endif
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#define USB_BASE 0x80080000
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#define ___ENSURE_ZERO(line, x) static uint8_t __ensure_zero_##line[-(x)] __attribute__((unused));
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#define __ENSURE_ZERO(x) ___ENSURE_ZERO(__LINE__, x)
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#define __ENSURE_MULTIPLE(x, y) __ENSURE_ZERO((x) % (y))
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#define __ENSURE_CACHELINE_MULTIPLE(x) __ENSURE_MULTIPLE(x, 1 << CACHEALIGN_BITS)
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#define __ENSURE_STRUCT_CACHE_FRIENDLY(name) __ENSURE_CACHELINE_MULTIPLE(sizeof(name))
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#define __REG_SET(reg) (*((volatile uint32_t *)(® + 1)))
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#define __REG_CLR(reg) (*((volatile uint32_t *)(® + 2)))
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#define __REG_TOG(reg) (*((volatile uint32_t *)(® + 3)))
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#define __REG_SET_CLR(reg, set) \
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(*((volatile uint32_t *)(® + (set ? 1 : 2))))
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#define __BLOCK_SFTRST (1 << 31)
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#define __BLOCK_CLKGATE (1 << 30)
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#define __XTRACT(reg, field) ((reg & reg##__##field##_BM) >> reg##__##field##_BP)
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#define __XTRACT_EX(val, field) (((val) & field##_BM) >> field##_BP)
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#define __FIELD_SET(reg, field, val) reg = (reg & ~reg##__##field##_BM) | (val << reg##__##field##_BP)
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#define __FIELD_SET_CLR(reg, field, set) __REG_SET_CLR(reg, set) = reg##__##field
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/**
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* Register Naming Scheme
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*
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* => Devices
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*
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* Each device <dev> has its base address defined as REGS_<dev>_base:
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*
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* Example:
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* #define REGS_APBHBASE (0x80004000)
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* #define REGS_SSPBASE(i) ((i) == 1 ? 0x80010000 : 0x80034000)
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*
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* => Registers
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*
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* Each register <reg> in device <dev> has its address(es) defined as
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* HW_<dev>_<reg>[_{SET,CLR,TOG}]
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*
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* Examples:
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* #define HW_APBH_CTRL1 (*(volatile unsigned long *)(REGS_APBHBASE + 0x10 + 0))
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* #define HW_APBH_CHn_CURCMDAR(n) (*(volatile unsigned long *)(REGS_APBHBASE + 0x40+(n)*0x70))
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* #define HW_SSP_CTRL0_SET(d) (*(volatile unsigned long *)(REGS_SSPBASE(d) + 0 + 0x4))
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*
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* => Fields
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*
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* Each field <field> in register <reg> in device <dev> has its bit position
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* and bitmask defined as {BP,BM}_<dev>_<reg>_<field>
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*
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* Examples:
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*
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*
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*
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*/
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/**
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* Register macros:
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*
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* BF_SET(reg, field): equivalent to HW_reg_SET = BM_reg_field;
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* BF_CLR(reg, field): same with CLR
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* BF_TOG(reg, field): same with TOG
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*
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* BF_SETV(reg, field, v): equivalent to HW_reg_SET = BF_reg_field(v)
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* BF_CLRV(reg, field, v): same with CLR
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* BF_TOGV(reg, fielf, v): same with TOG
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*
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* BF_RD(reg, field): equivalent to (HW_reg & BM_reg_field) >> BP_reg_field
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* BF_WR(reg, field, v): equivalent to HW_reg = (HW_reg & ~BM_reg_field) | (((v << BP_reg_field) & BM_reg_field)
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* BF_WR_V(reg, field, sym): BF_WR(reg, field, BV_reg_field__sym)
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*
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* BF_{SET,CLR,TOG}[V]n(reg, n, field): same for multi registers
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*
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* The BF_RDX(val, reg, field) reads from the value provided instead of the register
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* Similarly for BF_WRX
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*
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*/
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/**
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* Handy macros for mutliple operations at once
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*
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* BF_ORp(reg, f1,, ..., fp) is equivalent to
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* BF_reg_f1 | ... | BF_reg_fp
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*
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* BM_ORp is similar with BM_
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*
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* There exist some variadic variants which do not need to write the number
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* of parameters, if supported by the compiler:
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*
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* BF_OR(reg, f1, ..., fn)
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* BM_OR(reg, f1, ..., fn)
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*/
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#endif /* __IMX233_H__ */
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