271 lines
9.8 KiB
C
271 lines
9.8 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2014 Cástor Muñoz
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#ifndef _PL080_H
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#define _PL080_H
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/*
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* ARM PrimeCell PL080 Multiple Master DMA controller
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*/
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#include <stdint.h>
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#include <stddef.h>
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#include <stdbool.h>
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/* general defines */
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#define DMAC_CH_COUNT 8
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#define DMAC_LLI_MAX_COUNT 0xfff
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#define DMAC_CH_PRIO(x) (x)
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#define DMAC_CH_BASE(dmac_ba,ch_n) ((dmac_ba) + 0x100 + ((ch_n) << 5))
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/* PL080 controller registers */
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#define DMACINTSTS(base) (*((uint32_t volatile*)((base) + 0x00)))
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#define DMACINTTCSTS(base) (*((uint32_t volatile*)((base) + 0x04)))
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#define DMACINTTCCLR(base) (*((uint32_t volatile*)((base) + 0x08)))
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#define DMACINTERRSTS(base) (*((uint32_t volatile*)((base) + 0x0c)))
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#define DMACINTERRCLR(base) (*((uint32_t volatile*)((base) + 0x10)))
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#define DMACRAWINTTCSTS(base) (*((uint32_t volatile*)((base) + 0x14)))
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#define DMACRAWINTERRSTS(base) (*((uint32_t volatile*)((base) + 0x18)))
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#define DMACENABLEDCHANS(base) (*((uint32_t volatile*)((base) + 0x1c)))
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#define DMACSOFTBREQ(base) (*((uint32_t volatile*)((base) + 0x20)))
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#define DMACSOFTSREQ(base) (*((uint32_t volatile*)((base) + 0x24)))
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#define DMACSOFTLBREQ(base) (*((uint32_t volatile*)((base) + 0x28)))
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#define DMACSOFTLSREQ(base) (*((uint32_t volatile*)((base) + 0x2c)))
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#define DMACCONFIG(base) (*((uint32_t volatile*)((base) + 0x30)))
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#define DMACSYNC(base) (*((uint32_t volatile*)((base) + 0x34)))
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/* PL080 controller channel registers */
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#define DMACCxSRCADDR(base) (*((void* volatile*)((base) + 0x00)))
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#define DMACCxDESTADDR(base) (*((void* volatile*)((base) + 0x04)))
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#define DMACCxLINK(base) (*((uint32_t volatile*)((base) + 0x08)))
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#define DMACCxCONTROL(base) (*((uint32_t volatile*)((base) + 0x0c)))
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#define DMACCxCONFIG(base) (*((uint32_t volatile*)((base) + 0x10)))
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/* PL080 controller channel LLI */
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#define DMACCxLLI(base) ((struct dmac_lli volatile*)(base))
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/* PL080 DMA controller configuration register */
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#define DMACCONFIG_E_POS 0 /* DMAC enable */
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#define DMACCONFIG_E_MSK 0x1
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#define DMACCONFIG_M1_POS 1 /* AHB Master 1 endianness */
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#define DMACCONFIG_M1_MSK 0x1
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#define DMACCONFIG_M2_POS 2 /* AHB Master 2 endianness */
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#define DMACCONFIG_M2_MSK 0x1
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#define DMACCONFIG_E_BIT (1 << DMACCONFIG_E_POS)
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#define DMACCONFIG_M1_BIT (1 << DMACCCONFI_M1_POS)
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#define DMACCONFIG_M2_BIT (1 << DMACCCONFI_M2_POS)
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#define DMACCONFIG_M_LITTLE_ENDIAN 0
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#define DMACCONFIG_M_BIG_ENDIAN 1
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/* PL080 DMA controller channel LLI register */
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#define DMACCxLINK_LM_POS 0
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#define DMACCxLINK_LM_MSK 0x1
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#define DMACCxLINK_NEXTLLI_POS 2
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#define DMACCxLINK_NEXTLLI_MSK 0x3fffffff
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/* PL080 channel control register */
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#define DMACCxCONTROL_I_POS 31 /* terminal count interrupt */
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#define DMACCxCONTROL_I_MSK 0x1
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#define DMACCxCONTROL_PROT_POS 28 /* protection bits */
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#define DMACCxCONTROL_PROT_MSK 0x7
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#define DMACCxCONTROL_DI_POS 27 /* destination addr increment */
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#define DMACCxCONTROL_DI_MSK 0x1
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#define DMACCxCONTROL_SI_POS 26 /* source addr increment */
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#define DMACCxCONTROL_SI_MSK 0x1
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#define DMACCxCONTROL_D_POS 25 /* destinantion AHB master */
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#define DMACCxCONTROL_D_MSK 0x1
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#define DMACCxCONTROL_S_POS 24 /* source AHB master */
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#define DMACCxCONTROL_S_MSK 0x1
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#define DMACCxCONTROL_DWIDTH_POS 21 /* destinantion transfer width */
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#define DMACCxCONTROL_DWIDTH_MSK 0x7
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#define DMACCxCONTROL_SWIDTH_POS 18 /* source transfer width */
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#define DMACCxCONTROL_SWIDTH_MSK 0x7
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#define DMACCxCONTROL_DBSIZE_POS 15 /* destinantion burst size */
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#define DMACCxCONTROL_DBSIZE_MSK 0x7
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#define DMACCxCONTROL_SBSIZE_POS 12 /* source burst size */
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#define DMACCxCONTROL_SBSIZE_MSK 0x7
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#define DMACCxCONTROL_COUNT_POS 0 /* n SWIDTH size transfers */
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#define DMACCxCONTROL_COUNT_MSK 0xfff
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#define DMACCxCONTROL_WIDTH_8 0
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#define DMACCxCONTROL_WIDTH_16 1
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#define DMACCxCONTROL_WIDTH_32 2
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#define DMACCxCONTROL_BSIZE_1 0
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#define DMACCxCONTROL_BSIZE_4 1
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#define DMACCxCONTROL_BSIZE_8 2
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#define DMACCxCONTROL_BSIZE_16 3
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#define DMACCxCONTROL_BSIZE_32 4
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#define DMACCxCONTROL_BSIZE_64 5
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#define DMACCxCONTROL_BSIZE_128 6
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#define DMACCxCONTROL_BSIZE_256 7
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#define DMACCxCONTROL_INC_DISABLE 0
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#define DMACCxCONTROL_INC_ENABLE 1
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#define DMACCxCONTROL_I_BIT (1 << DMACCxCONTROL_I_POS)
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/* protection bits */
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#define DMAC_PROT_PRIV (1 << 0)
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#define DMAC_PROT_BUFF (1 << 1)
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#define DMAC_PROT_CACH (1 << 2)
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/* bus */
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#define DMAC_MASTER_AHB1 0
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#define DMAC_MASTER_AHB2 1
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/* PL080 channel configuration register */
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#define DMACCxCONFIG_E_POS 0 /* enable */
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#define DMACCxCONFIG_E_MSK 0x1
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#define DMACCxCONFIG_SRCPERI_POS 1 /* source peripheral */
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#define DMACCxCONFIG_SRCPERI_MSK 0xf
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#define DMACCxCONFIG_DESTPERI_POS 6 /* destination peripheral */
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#define DMACCxCONFIG_DESTPERI_MSK 0xf
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#define DMACCxCONFIG_FLOWCNTRL_POS 11 /* DMA transfer type */
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#define DMACCxCONFIG_FLOWCNTRL_MSK 0x7
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#define DMACCxCONFIG_IE_POS 14 /* interrupt error mask */
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#define DMACCxCONFIG_IE_MSK 0x1
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#define DMACCxCONFIG_ITC_POS 15 /* interrupt terminal count mask */
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#define DMACCxCONFIG_ITC_MSK 0x1
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#define DMACCxCONFIG_L_POS 16 /* lock */
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#define DMACCxCONFIG_L_MSK 0x1
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#define DMACCxCONFIG_A_POS 17 /* active */
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#define DMACCxCONFIG_A_MSK 0x1
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#define DMACCxCONFIG_H_POS 18 /* halt */
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#define DMACCxCONFIG_H_MSK 0x1
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#define DMACCxCONFIG_E_BIT (1 << DMACCxCONFIG_E_POS)
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#define DMACCxCONFIG_IE_BIT (1 << DMACCxCONFIG_IE_POS)
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#define DMACCxCONFIG_ITC_BIT (1 << DMACCxCONFIG_ITC_POS)
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#define DMACCxCONFIG_L_BIT (1 << DMACCxCONFIG_L_POS)
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#define DMACCxCONFIG_A_BIT (1 << DMACCxCONFIG_A_POS)
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#define DMACCxCONFIG_H_BIT (1 << DMACCxCONFIG_H_POS)
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#define DMACCxCONFIG_FLOWCNTRL_MEMMEM_DMA 0
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#define DMACCxCONFIG_FLOWCNTRL_MEMPERI_DMA 1
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#define DMACCxCONFIG_FLOWCNTRL_PERIMEM_DMA 2
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#define DMACCxCONFIG_FLOWCNTRL_PERIPERI_DMA 3
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#define DMACCxCONFIG_FLOWCNTRL_PERIPERI_DSTPERI 4
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#define DMACCxCONFIG_FLOWCNTRL_MEMPERI_PERI 5
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#define DMACCxCONFIG_FLOWCNTRL_PERIMEM_PERI 6
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#define DMACCxCONFIG_FLOWCNTRL_PERIPERI_SRCPERI 7
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/*
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* types
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*/
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struct dmac_lli {
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void* srcaddr;
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void* dstaddr;
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uint32_t link;
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uint32_t control;
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} __attribute__((aligned(16)));
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struct dmac_tsk {
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struct dmac_lli volatile *start_lli;
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struct dmac_lli volatile *end_lli;
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uint32_t size;
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void *cb_data;
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};
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/* used when src/dst peri is memory */
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#define DMAC_PERI_NONE 0x80
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struct dmac_ch_cfg {
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uint8_t srcperi;
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uint8_t dstperi;
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uint8_t sbsize;
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uint8_t dbsize;
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uint8_t swidth;
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uint8_t dwidth;
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uint8_t sbus;
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uint8_t dbus;
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uint8_t sinc;
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uint8_t dinc;
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uint8_t prot;
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uint16_t lli_xfer_max_count;
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};
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struct dmac_ch {
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/** user configurable data **/
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struct dmac *dmac;
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unsigned int prio;
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void (*cb_fn)(void *cb_data);
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/* tsk circular buffer */
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struct dmac_tsk *tskbuf;
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uint32_t tskbuf_mask;
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uint32_t queue_mode;
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/* lli circular buffer */
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struct dmac_lli volatile *llibuf;
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uint32_t llibuf_mask;
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uint32_t llibuf_bus;
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/** private driver data **/
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uint32_t baddr;
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struct dmac_lli volatile *llibuf_top;
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uint32_t tasks_queued; /* roll-over counter */
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uint32_t tasks_done; /* roll-over counter */
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uint32_t control;
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struct dmac_ch_cfg *cfg;
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};
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struct dmac {
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/* user configurable data */
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const uint32_t baddr;
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const uint8_t m1;
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const uint8_t m2;
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/* driver private data */
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struct dmac_ch *ch_l[DMAC_CH_COUNT];
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uint32_t ch_run_status; /* channel running status mask */
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};
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/* dmac_ch->queue_mode */
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enum {
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QUEUE_NORMAL,
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QUEUE_LINK,
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};
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/*
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* prototypes
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*/
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void dmac_callback(struct dmac *dmac);
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void dmac_open(struct dmac *dmac);
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void dmac_ch_init(struct dmac_ch *ch, struct dmac_ch_cfg *cfg);
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void dmac_ch_lock_int(struct dmac_ch *ch);
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void dmac_ch_unlock_int(struct dmac_ch *ch);
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void dmac_ch_queue_2d(struct dmac_ch *ch, void *srcaddr, void *dstaddr,
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size_t size, size_t width, size_t stride, void *cb_data);
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#define dmac_ch_queue(ch, srcaddr, dstaddr, size, cb_data) \
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dmac_ch_queue_2d(ch, srcaddr, dstaddr, size, 0, 0, cb_data)
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void dmac_ch_stop(struct dmac_ch* ch);
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bool dmac_ch_running(struct dmac_ch *ch);
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void *dmac_ch_get_info(struct dmac_ch *ch,
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size_t *bytes, size_t *t_bytes);
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#endif /* _PL080_H */
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