78 lines
3.6 KiB
C
78 lines
3.6 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright © 2008 Rafaël Carré
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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/* Note: since the base address is not specified, you need to define DMAC_BASE
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* before including this file */
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/* ARM PrimeCell PL081 Single Master DMA controller */
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#define DMAC_INT_STATUS (*(volatile unsigned long*)(DMAC_BASE+0x000))
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#define DMAC_INT_TC_STATUS (*(volatile unsigned long*)(DMAC_BASE+0x004))
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#define DMAC_INT_TC_CLEAR (*(volatile unsigned long*)(DMAC_BASE+0x008))
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#define DMAC_INT_ERROR_STATUS (*(volatile unsigned long*)(DMAC_BASE+0x00C))
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#define DMAC_INT_ERR_CLEAR (*(volatile unsigned long*)(DMAC_BASE+0x010))
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#define DMAC_RAW_INT_TC_STATUS (*(volatile unsigned long*)(DMAC_BASE+0x014))
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#define DMAC_RAW_INT_ERROR_STATUS (*(volatile unsigned long*)(DMAC_BASE+0x018))
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#define DMAC_ENBLD_CHANS (*(volatile unsigned long*)(DMAC_BASE+0x01C))
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#define DMAC_SOFT_B_REQ (*(volatile unsigned long*)(DMAC_BASE+0x020))
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#define DMAC_SOFT_S_REQ (*(volatile unsigned long*)(DMAC_BASE+0x024))
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#define DMAC_SOFT_LB_REQ (*(volatile unsigned long*)(DMAC_BASE+0x028))
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#define DMAC_SOFT_LS_REQ (*(volatile unsigned long*)(DMAC_BASE+0x02C))
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#define DMAC_CONFIGURATION (*(volatile unsigned long*)(DMAC_BASE+0x030))
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#define DMAC_SYNC (*(volatile unsigned long*)(DMAC_BASE+0x034))
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/* Channel registers (0 & 1) */
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#define DMAC_CH_SRC_ADDR(c) (*(volatile unsigned long*)(DMAC_BASE+0x100+(0x20*c)))
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#define DMAC_CH_DST_ADDR(c) (*(volatile unsigned long*)(DMAC_BASE+0x104+(0x20*c)))
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#define DMAC_CH_LLI(c) (*(volatile unsigned long*)(DMAC_BASE+0x108+(0x20*c)))
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#define DMAC_CH_CONTROL(c) (*(volatile unsigned long*)(DMAC_BASE+0x10C+(0x20*c)))
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#define DMAC_CH_CONFIGURATION(c) (*(volatile unsigned long*)(DMAC_BASE+0x110+(0x20*c)))
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/* Test registers */
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#define DMAC_ITCR (*(volatile unsigned long*)(DMAC_BASE+0x500))
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#define DMAC_ITOP1 (*(volatile unsigned long*)(DMAC_BASE+0x504))
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#define DMAC_ITOP2 (*(volatile unsigned long*)(DMAC_BASE+0x508))
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#define DMAC_ITOP3 (*(volatile unsigned long*)(DMAC_BASE+0x50C))
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/* Flow controllers */
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/* Controller is DMAC */
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#define DMAC_FLOWCTRL_DMAC_MEM_TO_MEM 0
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#define DMAC_FLOWCTRL_DMAC_MEM_TO_PERI 1
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#define DMAC_FLOWCTRL_DMAC_PERI_TO_MEM 2
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#define DMAC_FLOWCTRL_DMAC_PERI_TO_PERI 3
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/* Controller is peripheral */
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#define DMAC_FLOWCTRL_SRC_PERI_PERI_TO_PERI 4
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#define DMAC_FLOWCTRL_PERI_MEM_TO_PERI 5
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#define DMAC_FLOWCTRL_PERI_PERI_TO_MEM 6
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#define DMAC_FLOWCTRL_DST_PERI_PERI_TO_PERI 7
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/* Transfer request sizes */
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#define DMA_S1 0
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#define DMA_S4 1
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#define DMA_S8 2
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#define DMA_S16 3
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#define DMA_S32 4
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#define DMA_S64 5
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#define DMA_S128 6
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#define DMA_S256 7
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