96 lines
3.4 KiB
C
96 lines
3.4 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright © 2008 Rafaël Carré
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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/* ARM PrimeCell PL180 SD/MMC controller */
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/* MCIStatus bits */
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/* bits 10:0 can be cleared by a write in MCIClear */
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#define MCI_CMD_CRC_FAIL (1<<0)
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#define MCI_DATA_CRC_FAIL (1<<1)
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#define MCI_CMD_TIMEOUT (1<<2)
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#define MCI_DATA_TIMEOUT (1<<3)
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#define MCI_TX_UNDERRUN (1<<4)
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#define MCI_RX_OVERRUN (1<<5)
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#define MCI_CMD_RESP_END (1<<6)
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#define MCI_CMD_SENT (1<<7)
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#define MCI_DATA_END (1<<8)
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#define MCI_START_BIT_ERR (1<<9)
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#define MCI_DATA_BLOCK_END (1<<10)
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/* bits 21:11 are only cleared by the hardware logic */
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#define MCI_CMD_ACTIVE (1<<11)
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#define MCI_TX_ACTIVE (1<<12)
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#define MCI_RX_ACTIVE (1<<13)
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#define MCI_TX_FIFO_HALF_EMPTY (1<<14)
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#define MCI_RX_FIFO_HALF_FULL (1<<15)
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#define MCI_TX_FIFO_FULL (1<<16)
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#define MCI_RX_FIFO_FULL (1<<17)
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#define MCI_TX_FIFO_EMPTY (1<<18)
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#define MCI_RX_FIFO_EMPTY (1<<19)
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#define MCI_TX_DATA_AVAIL (1<<20)
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#define MCI_RX_DATA_AVAIL (1<<21)
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/* MCIPower bits */
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#define MCI_POWER_OFF 0x0
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/* 0x1 is reserved */
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#define MCI_POWER_UP 0x2
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#define MCI_POWER_ON 0x3
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/* bits 5:2 are the voltage */
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#define MCI_VDD_2_0 (0<<2) /* 2.0 - 2.6 comm only */
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#define MCI_VDD_2_1 (1<<2)
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#define MCI_VDD_2_2 (2<<2)
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#define MCI_VDD_2_3 (3<<2)
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#define MCI_VDD_2_4 (4<<2)
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#define MCI_VDD_2_5 (5<<2)
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#define MCI_VDD_2_6 (6<<2)
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#define MCI_VDD_2_7 (7<<2) /* 2.7 - 3.6 Data Transfer */
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#define MCI_VDD_2_8 (8<<2)
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#define MCI_VDD_2_9 (9<<2)
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#define MCI_VDD_3_0 (10<<2)
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#define MCI_VDD_3_1 (11<<2)
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#define MCI_VDD_3_2 (12<<2)
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#define MCI_VDD_3_3 (13<<2)
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#define MCI_VDD_3_4 (14<<2)
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#define MCI_VDD_3_5 (15<<2)
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#define MCI_POWER_OPEN_DRAIN (1<<6)
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#define MCI_POWER_ROD (1<<7)
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/* MCIClock bits */
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/* bits 7:0 are the clock divider */
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#define MCI_CLOCK_ENABLE (1<<8)
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#define MCI_CLOCK_POWERSAVE (1<<9)
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#define MCI_CLOCK_BYPASS (1<<10)
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#define MCI_CLOCK_WIDEBUS (1<<11)
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/* MCICommand bits */
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/* bits 5:0 are the command index */
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#define MCI_COMMAND_RESPONSE (1<<6)
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#define MCI_COMMAND_LONG_RESPONSE (1<<7)
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#define MCI_COMMAND_INTERRUPT (1<<8)
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#define MCI_COMMAND_PENDING (1<<9)
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#define MCI_COMMAND_ENABLE (1<<10)
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