269 lines
8.5 KiB
C
269 lines
8.5 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2005 by Tomasz Malesinski
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#ifndef __PNX0101_H__
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#define __PNX0101_H__
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#define GPIO0_READ (*(volatile unsigned long *)0x80003000)
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#define GPIO0_SET (*(volatile unsigned long *)0x80003014)
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#define GPIO0_CLR (*(volatile unsigned long *)0x80003018)
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#define GPIO1_READ (*(volatile unsigned long *)0x80003040)
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#define GPIO1_SET (*(volatile unsigned long *)0x80003054)
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#define GPIO1_CLR (*(volatile unsigned long *)0x80003058)
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#define GPIO2_READ (*(volatile unsigned long *)0x80003080)
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#define GPIO2_SET (*(volatile unsigned long *)0x80003094)
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#define GPIO2_CLR (*(volatile unsigned long *)0x80003098)
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#define GPIO3_READ (*(volatile unsigned long *)0x800030c0)
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#define GPIO3_SET (*(volatile unsigned long *)0x800030d4)
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#define GPIO3_CLR (*(volatile unsigned long *)0x800030d8)
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#define GPIO4_READ (*(volatile unsigned long *)0x80003100)
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#define GPIO4_SET (*(volatile unsigned long *)0x80003114)
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#define GPIO4_CLR (*(volatile unsigned long *)0x80003118)
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#define GPIO5_READ (*(volatile unsigned long *)0x80003140)
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#define GPIO5_SET (*(volatile unsigned long *)0x80003154)
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#define GPIO5_CLR (*(volatile unsigned long *)0x80003158)
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#define GPIO6_READ (*(volatile unsigned long *)0x80003180)
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#define GPIO6_SET (*(volatile unsigned long *)0x80003194)
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#define GPIO6_CLR (*(volatile unsigned long *)0x80003198)
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#define GPIO7_READ (*(volatile unsigned long *)0x800031c0)
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#define GPIO7_SET (*(volatile unsigned long *)0x800031d4)
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#define GPIO7_CLR (*(volatile unsigned long *)0x800031d8)
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#define LCDREG04 (*(volatile unsigned long *)0x80104004)
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#define LCDSTAT (*(volatile unsigned long *)0x80104008)
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#define LCDREG10 (*(volatile unsigned long *)0x80104010)
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#define LCDCMD (*(volatile unsigned long *)0x80104020)
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#define LCDDATA (*(volatile unsigned long *)0x80104030)
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#define TIMERR00 (*(volatile unsigned long *)0x80020000)
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#define TIMERR08 (*(volatile unsigned long *)0x80020008)
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#define TIMERR0C (*(volatile unsigned long *)0x8002000c)
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#define ADCCH0 (*(volatile unsigned long *)0x80002400)
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#define ADCCH1 (*(volatile unsigned long *)0x80002404)
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#define ADCCH2 (*(volatile unsigned long *)0x80002408)
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#define ADCCH3 (*(volatile unsigned long *)0x8000240c)
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#define ADCCH4 (*(volatile unsigned long *)0x80002410)
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#define ADCST (*(volatile unsigned long *)0x80002420)
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#define ADCR24 (*(volatile unsigned long *)0x80002424)
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#define ADCR28 (*(volatile unsigned long *)0x80002428)
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#define DMAINTSTAT (*(volatile unsigned long *)0x80104c04)
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#define DMAINTEN (*(volatile unsigned long *)0x80104c08)
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#define DMASRC(n) (*(volatile unsigned long *)(0x80104800 + (n) * 0x20))
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#define DMADEST(n) (*(volatile unsigned long *)(0x80104804 + (n) * 0x20))
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#define DMALEN(n) (*(volatile unsigned long *)(0x80104808 + (n) * 0x20))
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#define DMAR0C(n) (*(volatile unsigned long *)(0x8010480c + (n) * 0x20))
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#define DMAR10(n) (*(volatile unsigned long *)(0x80104810 + (n) * 0x20))
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#define DMAR1C(n) (*(volatile unsigned long *)(0x8010481c + (n) * 0x20))
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#define MMUBLOCK(n) (*(volatile unsigned long *)(0x80105018 + (n) * 4))
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#define CODECVOL (*(volatile unsigned long *)0x80200398)
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#ifndef ASM
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/* Clock generation unit */
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struct pnx0101_cgu {
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unsigned long base_scr[12];
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unsigned long base_fs1[12];
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unsigned long base_fs2[12];
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unsigned long base_ssr[12];
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unsigned long clk_pcr[73];
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unsigned long clk_psr[73];
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unsigned long clk_esr[67];
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unsigned long base_bcr[3];
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unsigned long base_fdc[18];
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};
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#define CGU (*(volatile struct pnx0101_cgu *)0x80004000)
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#define PNX0101_SEL_STAGE_SYS 0
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#define PNX0101_SEL_STAGE_APB0 1
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#define PNX0101_SEL_STAGE_APB1 2
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#define PNX0101_SEL_STAGE_APB3 3
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#define PNX0101_SEL_STAGE_DAIO 9
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#define PNX0101_HIPREC_FDC 16
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#define PNX0101_FIRST_DIV_SYS 0
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#define PNX0101_N_DIV_SYS 7
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#define PNX0101_FIRST_DIV_APB0 7
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#define PNX0101_N_DIV_APB0 2
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#define PNX0101_FIRST_DIV_APB1 9
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#define PNX0101_N_DIV_APB1 1
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#define PNX0101_FIRST_DIV_APB3 10
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#define PNX0101_N_DIV_APB3 1
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#define PNX0101_FIRST_DIV_DAIO 12
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#define PNX0101_N_DIV_DAIO 6
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#define PNX0101_BCR_SYS 0
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#define PNX0101_BCR_APB0 1
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#define PNX0101_BCR_DAIO 2
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#define PNX0101_FIRST_ESR_SYS 0
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#define PNX0101_N_ESR_SYS 28
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#define PNX0101_FIRST_ESR_APB0 28
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#define PNX0101_N_ESR_APB0 9
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#define PNX0101_FIRST_ESR_APB1 37
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#define PNX0101_N_ESR_APB1 4
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#define PNX0101_FIRST_ESR_APB3 41
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#define PNX0101_N_ESR_APB3 16
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#define PNX0101_FIRST_ESR_DAIO 58
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#define PNX0101_N_ESR_DAIO 9
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#define PNX0101_ESR_APB1 0x25
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#define PNX0101_ESR_T0 0x26
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#define PNX0101_ESR_T1 0x27
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#define PNX0101_ESR_I2C 0x28
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#define PNX0101_CLOCK_APB1 0x25
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#define PNX0101_CLOCK_T0 0x26
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#define PNX0101_CLOCK_T1 0x27
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#define PNX0101_CLOCK_I2C 0x28
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#define PNX0101_MAIN_CLOCK_FAST 1
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#define PNX0101_MAIN_CLOCK_MAIN_PLL 9
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struct pnx0101_pll {
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unsigned long hpfin;
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unsigned long hpmdec;
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unsigned long hpndec;
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unsigned long hppdec;
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unsigned long hpmode;
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unsigned long hpstat;
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unsigned long hpack;
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unsigned long hpreq;
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unsigned long hppad1;
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unsigned long hppad2;
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unsigned long hppad3;
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unsigned long hpselr;
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unsigned long hpseli;
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unsigned long hpselp;
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unsigned long lpfin;
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unsigned long lppdn;
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unsigned long lpmbyp;
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unsigned long lplock;
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unsigned long lpdbyp;
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unsigned long lpmsel;
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unsigned long lppsel;
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};
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#define PLL (*(volatile struct pnx0101_pll *)0x80004cac)
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struct pnx0101_emc {
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unsigned long control;
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unsigned long status;
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};
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#define EMC (*(volatile struct pnx0101_emc *)0x80008000)
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struct pnx0101_emcstatic {
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unsigned long config;
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unsigned long waitwen;
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unsigned long waitoen;
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unsigned long waitrd;
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unsigned long waitpage;
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unsigned long waitwr;
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unsigned long waitturn;
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};
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#define EMCSTATIC0 (*(volatile struct pnx0101_emcstatic *)0x80008200)
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#define EMCSTATIC1 (*(volatile struct pnx0101_emcstatic *)0x80008220)
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#define EMCSTATIC2 (*(volatile struct pnx0101_emcstatic *)0x80008240)
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/* Timers */
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struct pnx0101_timer {
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unsigned long load;
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unsigned long value;
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unsigned long ctrl;
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unsigned long clr;
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};
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#define TIMER0 (*(volatile struct pnx0101_timer *)0x80020000)
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#define TIMER1 (*(volatile struct pnx0101_timer *)0x80020400)
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/* Interrupt controller */
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#define IRQ_TIMER0 5
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#define IRQ_TIMER1 6
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#define IRQ_DMA 28
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#define INTPRIOMASK ((volatile unsigned long *)0x80300000)
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#define INTVECTOR ((volatile unsigned long *)0x80300100)
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#define INTPENDING (*(volatile unsigned long *)0x80300200)
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#define INTFEATURES (*(volatile unsigned long *)0x80300300)
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#define INTREQ ((volatile unsigned long *)0x80300400)
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#define INTREQ_WEPRIO 0x10000000
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#define INTREQ_WETARGET 0x08000000
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#define INTREQ_WEENABLE 0x04000000
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#define INTREQ_WEACTVLO 0x02000000
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#define INTREQ_ENABLE 0x00010000
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/* General purpose DMA */
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struct pnx0101_dma_channel {
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unsigned long source;
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unsigned long dest;
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unsigned long length;
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unsigned long config;
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unsigned long enable;
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unsigned long pad1;
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unsigned long pad2;
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unsigned long count;
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};
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#define DMACHANNEL ((volatile struct pnx0101_dma_channel *)0x80104800)
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struct pnx0101_dma {
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unsigned long enable;
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unsigned long stat;
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unsigned long irqmask;
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unsigned long softint;
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};
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#define DMA (*(volatile struct pnx0101_dma *)0x80104c00)
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struct pnx0101_audio {
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unsigned long pad1;
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unsigned long siocr;
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unsigned long pad2;
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unsigned long pad3;
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unsigned long pad4;
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unsigned long pad5;
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unsigned long ddacctrl;
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unsigned long ddacstat;
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unsigned long ddacset;
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};
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#define AUDIO (*(volatile struct pnx0101_audio *)0x80200380)
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#endif /* ASM */
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/* Timer frequency */
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#define TIMER_FREQ 3000000
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#endif
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