140 lines
5.6 KiB
C
140 lines
5.6 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2008 by Maurus Cuelenaere
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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/*
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* Register definitions for the Renesas R61509 TFT Panel
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*/
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#ifndef __R61509_H
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#define __R61509_H
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/* Register list */
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#define REG_DEVICE_CODE 0x000
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#define REG_DRIVER_OUTPUT 0x001
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#define REG_LCD_DR_WAVE_CTRL 0x002
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#define REG_ENTRY_MODE 0x003
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#define REG_OUTL_SHARP_CTRL 0x006
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#define REG_DISP_CTRL1 0x007
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#define REG_DISP_CTRL2 0x008
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#define REG_DISP_CTRL3 0x009
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#define REG_LPCTRL 0x00B
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#define REG_EXT_DISP_CTRL1 0x00C
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#define REG_EXT_DISP_CTRL2 0x00F
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#define REG_PAN_INTF_CTRL1 0x010
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#define REG_PAN_INTF_CTRL2 0x011
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#define REG_PAN_INTF_CTRL3 0x012
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#define REG_PAN_INTF_CTRL4 0x020
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#define REG_PAN_INTF_CTRL5 0x021
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#define REG_PAN_INTF_CTRL6 0x022
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#define REG_FRM_MRKR_CTRL 0x090
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#define REG_PWR_CTRL1 0x100
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#define REG_PWR_CTRL2 0x101
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#define REG_PWR_CTRL3 0x102
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#define REG_PWR_CTRL4 0x103
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#define REG_PWR_CTRL5 0x107
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#define REG_PWR_CTRL6 0x110
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#define REG_PWR_CTRL7 0x112
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#define REG_RAM_HADDR_SET 0x200
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#define REG_RAM_VADDR_SET 0x201
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#define REG_RW_GRAM 0x202
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#define REG_RAM_HADDR_START 0x210
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#define REG_RAM_HADDR_END 0x211
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#define REG_RAM_VADDR_START 0x212
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#define REG_RAM_VADDR_END 0x213
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#define REG_RW_NVM 0x280
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#define REG_VCOM_HVOLTAGE1 0x281
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#define REG_VCOM_HVOLTAGE2 0x282
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#define REG_GAMMA_CTRL1 0x300
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#define REG_GAMMA_CTRL2 0x301
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#define REG_GAMMA_CTRL3 0x302
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#define REG_GAMMA_CTRL4 0x303
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#define REG_GAMMA_CTRL5 0x304
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#define REG_GAMMA_CTRL6 0x305
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#define REG_GAMMA_CTRL7 0x306
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#define REG_GAMMA_CTRL8 0x307
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#define REG_GAMMA_CTRL9 0x308
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#define REG_GAMMA_CTRL10 0x309
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#define REG_GAMMA_CTRL11 0x30A
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#define REG_GAMMA_CTRL12 0x30B
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#define REG_GAMMA_CTRL13 0x30C
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#define REG_GAMMA_CTRL14 0x30D
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#define REG_BIMG_NR_LINE 0x400
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#define REG_BIMG_DISP_CTRL 0x401
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#define REG_BIMG_VSCROLL_CTRL 0x404
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#define REG_PARTIMG1_POS 0x500
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#define REG_PARTIMG1_RAM_START 0x501
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#define REG_PARTIMG1_RAM_END 0x502
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#define REG_PARTIMG2_POS 0x503
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#define REG_PARTIMG2_RAM_START 0x504
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#define REG_PARTIMG2_RAM_END 0x505
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#define REG_SOFT_RESET 0x600
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#define REG_ENDIAN_CTRL 0x606
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#define REG_NVM_ACCESS_CTRL 0x6F0
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/* Bits */
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#define DRIVER_OUTPUT_SS_BIT (1 << 8)
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#define DRIVER_OUTPUT_SM_BIT (1 << 10)
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#define ENTRY_MODE_TRI (1 << 15)
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#define ENTRY_MODE_DFM (1 << 14)
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#define ENTRY_MODE_BGR (1 << 12)
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#define ENTRY_MODE_HWM (1 << 9)
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#define ENTRY_MODE_ORG (1 << 7)
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#define ENTRY_MODE_VID (1 << 5)
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#define ENTRY_MODE_HID (1 << 4)
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#define ENTRY_MODE_AM (1 << 3)
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#define ENTRY_MODE_EPF(n) (n & 3)
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#define OUTL_SHARP_CTRL_EGMODE (1 << 15)
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#define OUTL_SHARP_CTRL_AVST(n) ((n & 7) << 7)
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#define OUTL_SHARP_CTRL_ADST(n) ((n & 7) << 4)
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#define OUTL_SHARP_CTRL_DTHU(n) ((n & 3) << 2)
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#define OUTL_SHARP_CTRL_DTHL(n) (n & 3)
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#define DISP_CTRL1_PTDE(n) ((n & 4) << 12)
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#define DISP_CTRL1_BASEE (1 << 8)
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#define DISP_CTRL1_VON (1 << 6)
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#define DISP_CTRL1_GON (1 << 5)
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#define DISP_CTRL1_DTE (1 << 4)
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#define DISP_CTRL1_D(n) (n & 3)
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#define EXT_DISP_CTRL1_ENC(n) ((n & 7) << 12)
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#define EXT_DISP_CTRL1_RM(n) ((n & 1) << 8)
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#define EXT_DISP_CTRL1_DM(n) ((n & 3) << 4)
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#define EXT_DISP_CTRL1_RIM(n) (n & 3)
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#define PWR_CTRL1_SAP(n) ((n & 3) << 13)
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#define PWR_CTRL1_SAPE (1 << 12)
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#define PWR_CTRL1_BT(n) ((n & 7) << 8)
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#define PWR_CTRL1_APE (1 << 7)
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#define PWR_CTRL1_AP(n) ((n & 7) << 4)
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#define PWR_CTRL1_DSTB (1 << 2)
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#define PWR_CTRL1_SLP (1 << 1)
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#define SOFT_RESET(n) (n << 0)
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#endif /* __R61509_H */
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