532 lines
25 KiB
C
532 lines
25 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2009 Michael Sparmann
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#ifndef USB_S3C6400X_H
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#define USB_S3C6400X_H
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/* All multi-bit fields in the driver use the following convention.
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* If the register name is NAME, then there is one define NAME_bitp
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* which holds the bit position and one define NAME_bits which holds
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* a mask of the bits within the register (after shift).
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* These macros allow easy access and construction of such fields */
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/* Usage:
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* - extract(reg_name,field_name)
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* extract a field of the register
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* - bitm(reg_name,field_name)
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* build a bitmask for the field
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*/
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#define extract(reg_name, field_name) \
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((reg_name >> reg_name##_##field_name##_bitp) & reg_name##_##field_name##_bits)
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#define bitm(reg_name, field_name) \
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(reg_name##_##field_name##_bits << reg_name##_##field_name##_bitp)
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/*** OTG PHY CONTROL REGISTERS ***/
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#define OPHYPWR (*((uint32_t volatile*)(PHYBASE + 0x000)))
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#define OPHYCLK (*((uint32_t volatile*)(PHYBASE + 0x004)))
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#define ORSTCON (*((uint32_t volatile*)(PHYBASE + 0x008)))
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#define OPHYUNK3 (*((uint32_t volatile*)(PHYBASE + 0x018)))
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#define OPHYUNK1 (*((uint32_t volatile*)(PHYBASE + 0x01c)))
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#define OPHYUNK2 (*((uint32_t volatile*)(PHYBASE + 0x044)))
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/*** OTG LINK CORE REGISTERS ***/
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/* Core Global Registers */
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/** OTG Control and Status Register */
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#define GOTGCTL (*((uint32_t volatile*)(OTGBASE + 0x000)))
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/** OTG Interrupt Register */
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#define GOTGINT (*((uint32_t volatile*)(OTGBASE + 0x004)))
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/** Core AHB Configuration Register */
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#define GAHBCFG (*((uint32_t volatile*)(OTGBASE + 0x008)))
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#define GAHBCFG_glblintrmsk (1 << 0) /** Global interrupt mask */
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#define GAHBCFG_hburstlen_bitp 1
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#define GAHBCFG_hburstlen_bits 0xf
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#define GAHBCFG_INT_DMA_BURST_SINGLE 0
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#define GAHBCFG_INT_DMA_BURST_INCR 1 /** note: the linux patch has several other value, this is one picked for internal dma */
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#define GAHBCFG_INT_DMA_BURST_INCR4 3
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#define GAHBCFG_INT_DMA_BURST_INCR8 5
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#define GAHBCFG_INT_DMA_BURST_INCR16 7
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#define GAHBCFG_dma_enable (1 << 5) /** Enable DMA */
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/** Core USB Configuration Register */
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#define GUSBCFG (*((uint32_t volatile*)(OTGBASE + 0x00C)))
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#define GUSBCFG_toutcal_bitp 0
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#define GUSBCFG_toutcal_bits 0x7
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#define GUSBCFG_phy_if (1 << 3) /** select utmi bus width ? */
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#define GUSBCFG_ulpi_utmi_sel (1 << 4) /** select ulpi:1 or utmi:0 */
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#define GUSBCFG_fsintf (1 << 5)
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#define GUSBCFG_physel (1 << 6)
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#define GUSBCFG_ddrsel (1 << 7)
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#define GUSBCFG_srpcap (1 << 8)
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#define GUSBCFG_hnpcapp (1 << 9)
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#define GUSBCFG_usbtrdtim_bitp 10
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#define GUSBCFG_usbtrdtim_bits 0xf
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#define GUSBCFG_nptxfrwnden (1 << 14)
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#define GUSBCFG_phylpwrclksel (1 << 15)
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#define GUSBCFG_otgutmifssel (1 << 16)
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#define GUSBCFG_ulpi_fsls (1 << 17)
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#define GUSBCFG_ulpi_auto_res (1 << 18)
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#define GUSBCFG_ulpi_clk_sus_m (1 << 19)
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#define GUSBCFG_ulpi_ext_vbus_drv (1 << 20)
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#define GUSBCFG_ulpi_int_vbus_indicator (1 << 21)
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#define GUSBCFG_term_sel_dl_pulse (1 << 22)
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#define GUSBCFG_force_host_mode (1 << 29)
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#define GUSBCFG_force_device_mode (1 << 30)
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#define GUSBCFG_corrupt_tx_packet (1 << 31)
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/** Core Reset Register */
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#define GRSTCTL (*((uint32_t volatile*)(OTGBASE + 0x010)))
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#define GRSTCTL_csftrst (1 << 0) /** Core soft reset */
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#define GRSTCTL_hsftrst (1 << 1) /** Hclk soft reset */
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#define GRSTCTL_intknqflsh (1 << 3) /** In Token Sequence Learning Queue Flush */
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#define GRSTCTL_rxfflsh_flush (1 << 4) /** RxFIFO Flush */
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#define GRSTCTL_txfflsh_flush (1 << 5) /** TxFIFO Flush */
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#define GRSTCTL_txfnum_bitp 6 /** TxFIFO Number */
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#define GRSTCTL_txfnum_bits 0x1f
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#define GRSTCTL_ahbidle (1 << 31) /** AHB idle state*/
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/** Core Interrupt Register */
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#define GINTSTS (*((uint32_t volatile*)(OTGBASE + 0x014)))
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/* NOTE: GINTSTS bits are the same as in GINTMSK plus this one */
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#define GINTSTS_curmode (1 << 0) /** Current mode, 0 for device */
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/** Core Interrupt Mask Register */
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#define GINTMSK (*((uint32_t volatile*)(OTGBASE + 0x018)))
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#define GINTMSK_modemismatch (1 << 1) /** mode mismatch ? */
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#define GINTMSK_otgintr (1 << 2)
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#define GINTMSK_sofintr (1 << 3)
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#define GINTMSK_rxstsqlvl (1 << 4)
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#define GINTMSK_nptxfempty (1 << 5) /** Non-periodic TX fifo empty ? */
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#define GINTMSK_ginnakeff (1 << 6)
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#define GINTMSK_goutnakeff (1 << 7)
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#define GINTMSK_i2cintr (1 << 9)
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#define GINTMSK_erlysuspend (1 << 10)
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#define GINTMSK_usbsuspend (1 << 11) /** USB suspend */
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#define GINTMSK_usbreset (1 << 12) /** USB reset */
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#define GINTMSK_enumdone (1 << 13) /** Enumeration done */
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#define GINTMSK_isooutdrop (1 << 14)
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#define GINTMSK_eopframe (1 << 15)
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#define GINTMSK_epmismatch (1 << 17) /** endpoint mismatch ? */
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#define GINTMSK_inepintr (1 << 18) /** in pending ? */
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#define GINTMSK_outepintr (1 << 19) /** out pending ? */
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#define GINTMSK_incomplisoin (1 << 20) /** ISP in complete ? */
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#define GINTMSK_incomplisoout (1 << 21) /** ISO out complete ? */
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#define GINTMSK_portintr (1 << 24) /** Port status change ? */
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#define GINTMSK_hcintr (1 << 25)
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#define GINTMSK_ptxfempty (1 << 26) /** Periodic TX fifof empty ? */
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#define GINTMSK_conidstschng (1 << 28)
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#define GINTMSK_disconnect (1 << 29) /** Disconnect */
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#define GINTMSK_sessreqintr (1 << 30) /** Session request */
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#define GINTMSK_wkupintr (1 << 31) /** Wake up */
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/** Receive Status Debug Read Register (Read Only) */
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#define GRXSTSR (*((uint32_t volatile*)(OTGBASE + 0x01C)))
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/** Receive Status Read /Pop Register (Read Only) */
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#define GRXSTSP (*((uint32_t volatile*)(OTGBASE + 0x020)))
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/** Receive FIFO Size Register */
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#define GRXFSIZ (*((uint32_t volatile*)(OTGBASE + 0x024)))
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/** Periodic Transmit FIFO Size Register */
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#define GNPTXFSIZ (*((uint32_t volatile*)(OTGBASE + 0x028)))
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#define MAKE_FIFOSIZE_DATA(depth) ((depth) | ((depth) << 16))
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/** Non-Periodic Transmit FIFO/Queue Status Register */
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#define GNPTXSTS (*((uint32_t volatile*)(OTGBASE + 0x02C)))
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/** Device IN Endpoint Transmit FIFO (ep) Size Register */
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/* 1<=ep<=15, don't use ep=0 !!! */
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#define HPTXFSIZ (*((uint32_t volatile*)(OTGBASE + 0x100)))
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#define DPTXFSIZ(x) (*((uint32_t volatile*)(OTGBASE + 0x100 + 4 * (x))))
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/*** HOST MODE REGISTERS ***/
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/* Host Global Registers */
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#define HCFG (*((uint32_t volatile*)(OTGBASE + 0x400)))
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#define HFIR (*((uint32_t volatile*)(OTGBASE + 0x404)))
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#define HFNUM (*((uint32_t volatile*)(OTGBASE + 0x408)))
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#define HPTXSTS (*((uint32_t volatile*)(OTGBASE + 0x410)))
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#define HAINT (*((uint32_t volatile*)(OTGBASE + 0x414)))
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#define HAINTMSK (*((uint32_t volatile*)(OTGBASE + 0x418)))
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/* Host Port Control and Status Registers */
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#define HPRT (*((uint32_t volatile*)(OTGBASE + 0x440)))
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/* Host Channel-Specific Registers */
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#define HCCHAR(x) (*((uint32_t volatile*)(OTGBASE + 0x500 + 0x20 * (x))))
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#define HCSPLT(x) (*((uint32_t volatile*)(OTGBASE + 0x504 + 0x20 * (x))))
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#define HCINT(x) (*((uint32_t volatile*)(OTGBASE + 0x508 + 0x20 * (x))))
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#define HCINTMSK(x) (*((uint32_t volatile*)(OTGBASE + 0x50C + 0x20 * (x))))
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#define HCTSIZ(x) (*((uint32_t volatile*)(OTGBASE + 0x510 + 0x20 * (x))))
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#define HCDMA(x) (*((uint32_t volatile*)(OTGBASE + 0x514 + 0x20 * (x))))
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#define HCCHAR0 (*((uint32_t volatile*)(OTGBASE + 0x500)))
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#define HCSPLT0 (*((uint32_t volatile*)(OTGBASE + 0x504)))
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#define HCINT0 (*((uint32_t volatile*)(OTGBASE + 0x508)))
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#define HCINTMSK0 (*((uint32_t volatile*)(OTGBASE + 0x50C)))
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#define HCTSIZ0 (*((uint32_t volatile*)(OTGBASE + 0x510)))
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#define HCDMA0 (*((uint32_t volatile*)(OTGBASE + 0x514)))
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#define HCCHAR1 (*((uint32_t volatile*)(OTGBASE + 0x520)))
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#define HCSPLT1 (*((uint32_t volatile*)(OTGBASE + 0x524)))
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#define HCINT1 (*((uint32_t volatile*)(OTGBASE + 0x528)))
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#define HCINTMSK1 (*((uint32_t volatile*)(OTGBASE + 0x52C)))
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#define HCTSIZ1 (*((uint32_t volatile*)(OTGBASE + 0x530)))
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#define HCDMA1 (*((uint32_t volatile*)(OTGBASE + 0x534)))
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#define HCCHAR2 (*((uint32_t volatile*)(OTGBASE + 0x540)))
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#define HCSPLT2 (*((uint32_t volatile*)(OTGBASE + 0x544)))
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#define HCINT2 (*((uint32_t volatile*)(OTGBASE + 0x548)))
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#define HCINTMSK2 (*((uint32_t volatile*)(OTGBASE + 0x54C)))
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#define HCTSIZ2 (*((uint32_t volatile*)(OTGBASE + 0x550)))
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#define HCDMA2 (*((uint32_t volatile*)(OTGBASE + 0x554)))
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#define HCCHAR3 (*((uint32_t volatile*)(OTGBASE + 0x560)))
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#define HCSPLT3 (*((uint32_t volatile*)(OTGBASE + 0x564)))
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#define HCINT3 (*((uint32_t volatile*)(OTGBASE + 0x568)))
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#define HCINTMSK3 (*((uint32_t volatile*)(OTGBASE + 0x56C)))
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#define HCTSIZ3 (*((uint32_t volatile*)(OTGBASE + 0x570)))
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#define HCDMA3 (*((uint32_t volatile*)(OTGBASE + 0x574)))
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#define HCCHAR4 (*((uint32_t volatile*)(OTGBASE + 0x580)))
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#define HCSPLT4 (*((uint32_t volatile*)(OTGBASE + 0x584)))
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#define HCINT4 (*((uint32_t volatile*)(OTGBASE + 0x588)))
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#define HCINTMSK4 (*((uint32_t volatile*)(OTGBASE + 0x58C)))
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#define HCTSIZ4 (*((uint32_t volatile*)(OTGBASE + 0x590)))
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#define HCDMA4 (*((uint32_t volatile*)(OTGBASE + 0x594)))
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#define HCCHAR5 (*((uint32_t volatile*)(OTGBASE + 0x5A0)))
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#define HCSPLT5 (*((uint32_t volatile*)(OTGBASE + 0x5A4)))
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#define HCINT5 (*((uint32_t volatile*)(OTGBASE + 0x5A8)))
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#define HCINTMSK5 (*((uint32_t volatile*)(OTGBASE + 0x5AC)))
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#define HCTSIZ5 (*((uint32_t volatile*)(OTGBASE + 0x5B0)))
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#define HCDMA5 (*((uint32_t volatile*)(OTGBASE + 0x5B4)))
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#define HCCHAR6 (*((uint32_t volatile*)(OTGBASE + 0x5C0)))
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#define HCSPLT6 (*((uint32_t volatile*)(OTGBASE + 0x5C4)))
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#define HCINT6 (*((uint32_t volatile*)(OTGBASE + 0x5C8)))
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#define HCINTMSK6 (*((uint32_t volatile*)(OTGBASE + 0x5CC)))
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#define HCTSIZ6 (*((uint32_t volatile*)(OTGBASE + 0x5D0)))
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#define HCDMA6 (*((uint32_t volatile*)(OTGBASE + 0x5D4)))
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#define HCCHAR7 (*((uint32_t volatile*)(OTGBASE + 0x5E0)))
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#define HCSPLT7 (*((uint32_t volatile*)(OTGBASE + 0x5E4)))
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#define HCINT7 (*((uint32_t volatile*)(OTGBASE + 0x5E8)))
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#define HCINTMSK7 (*((uint32_t volatile*)(OTGBASE + 0x5EC)))
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#define HCTSIZ7 (*((uint32_t volatile*)(OTGBASE + 0x5F0)))
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#define HCDMA7 (*((uint32_t volatile*)(OTGBASE + 0x5F4)))
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#define HCCHAR8 (*((uint32_t volatile*)(OTGBASE + 0x600)))
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#define HCSPLT8 (*((uint32_t volatile*)(OTGBASE + 0x604)))
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#define HCINT8 (*((uint32_t volatile*)(OTGBASE + 0x608)))
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#define HCINTMSK8 (*((uint32_t volatile*)(OTGBASE + 0x60C)))
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#define HCTSIZ8 (*((uint32_t volatile*)(OTGBASE + 0x610)))
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#define HCDMA8 (*((uint32_t volatile*)(OTGBASE + 0x614)))
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#define HCCHAR9 (*((uint32_t volatile*)(OTGBASE + 0x620)))
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#define HCSPLT9 (*((uint32_t volatile*)(OTGBASE + 0x624)))
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#define HCINT9 (*((uint32_t volatile*)(OTGBASE + 0x628)))
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#define HCINTMSK9 (*((uint32_t volatile*)(OTGBASE + 0x62C)))
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#define HCTSIZ9 (*((uint32_t volatile*)(OTGBASE + 0x630)))
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#define HCDMA9 (*((uint32_t volatile*)(OTGBASE + 0x634)))
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#define HCCHAR10 (*((uint32_t volatile*)(OTGBASE + 0x640)))
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#define HCSPLT10 (*((uint32_t volatile*)(OTGBASE + 0x644)))
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#define HCINT10 (*((uint32_t volatile*)(OTGBASE + 0x648)))
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#define HCINTMSK10 (*((uint32_t volatile*)(OTGBASE + 0x64C)))
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#define HCTSIZ10 (*((uint32_t volatile*)(OTGBASE + 0x650)))
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#define HCDMA10 (*((uint32_t volatile*)(OTGBASE + 0x654)))
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#define HCCHAR11 (*((uint32_t volatile*)(OTGBASE + 0x660)))
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#define HCSPLT11 (*((uint32_t volatile*)(OTGBASE + 0x664)))
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#define HCINT11 (*((uint32_t volatile*)(OTGBASE + 0x668)))
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#define HCINTMSK11 (*((uint32_t volatile*)(OTGBASE + 0x66C)))
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#define HCTSIZ11 (*((uint32_t volatile*)(OTGBASE + 0x670)))
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#define HCDMA11 (*((uint32_t volatile*)(OTGBASE + 0x674)))
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#define HCCHAR12 (*((uint32_t volatile*)(OTGBASE + 0x680)))
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#define HCSPLT12 (*((uint32_t volatile*)(OTGBASE + 0x684)))
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#define HCINT12 (*((uint32_t volatile*)(OTGBASE + 0x688)))
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#define HCINTMSK12 (*((uint32_t volatile*)(OTGBASE + 0x68C)))
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#define HCTSIZ12 (*((uint32_t volatile*)(OTGBASE + 0x690)))
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#define HCDMA12 (*((uint32_t volatile*)(OTGBASE + 0x694)))
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#define HCCHAR13 (*((uint32_t volatile*)(OTGBASE + 0x6A0)))
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#define HCSPLT13 (*((uint32_t volatile*)(OTGBASE + 0x6A4)))
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#define HCINT13 (*((uint32_t volatile*)(OTGBASE + 0x6A8)))
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#define HCINTMSK13 (*((uint32_t volatile*)(OTGBASE + 0x6AC)))
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#define HCTSIZ13 (*((uint32_t volatile*)(OTGBASE + 0x6B0)))
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#define HCDMA13 (*((uint32_t volatile*)(OTGBASE + 0x6B4)))
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#define HCCHAR14 (*((uint32_t volatile*)(OTGBASE + 0x6C0)))
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#define HCSPLT14 (*((uint32_t volatile*)(OTGBASE + 0x6C4)))
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#define HCINT14 (*((uint32_t volatile*)(OTGBASE + 0x6C8)))
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#define HCINTMSK14 (*((uint32_t volatile*)(OTGBASE + 0x6CC)))
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#define HCTSIZ14 (*((uint32_t volatile*)(OTGBASE + 0x6D0)))
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#define HCDMA14 (*((uint32_t volatile*)(OTGBASE + 0x6D4)))
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#define HCCHAR15 (*((uint32_t volatile*)(OTGBASE + 0x6E0)))
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#define HCSPLT15 (*((uint32_t volatile*)(OTGBASE + 0x6E4)))
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#define HCINT15 (*((uint32_t volatile*)(OTGBASE + 0x6E8)))
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#define HCINTMSK15 (*((uint32_t volatile*)(OTGBASE + 0x6EC)))
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#define HCTSIZ15 (*((uint32_t volatile*)(OTGBASE + 0x6F0)))
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#define HCDMA15 (*((uint32_t volatile*)(OTGBASE + 0x6F4)))
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/*** DEVICE MODE REGISTERS ***/
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/* Device Global Registers */
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/** Device Configuration Register */
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#define DCFG (*((uint32_t volatile*)(OTGBASE + 0x800)))
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#define DCFG_devspd_bitp 0 /** Device Speed */
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#define DCFG_devspd_bits 0x3
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#define DCFG_devspd_hs_phy_hs 0 /** High speed PHY running at high speed */
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#define DCFG_devspd_hs_phy_fs 1 /** High speed PHY running at full speed */
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#define DCFG_nzstsouthshk (1 << 2) /** Non Zero Length Status OUT Handshake */
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#define DCFG_devadr_bitp 4 /** Device Address */
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#define DCFG_devadr_bits 0x7f
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#define DCFG_perfrint_bitp 11 /** Periodic Frame Interval */
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#define DCFG_perfrint_bits 0x3
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#define DCFG_FRAME_INTERVAL_80 0
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#define DCFG_FRAME_INTERVAL_85 1
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#define DCFG_FRAME_INTERVAL_90 2
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#define DCFG_FRAME_INTERVAL_95 3
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/** Device Control Register */
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#define DCTL (*((uint32_t volatile*)(OTGBASE + 0x804)))
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#define DCTL_rmtwkupsig (1 << 0) /** Remote Wakeup */
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#define DCTL_sftdiscon (1 << 1) /** Soft Disconnect */
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#define DCTL_gnpinnaksts (1 << 2) /** Global Non-Periodic IN NAK Status */
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#define DCTL_goutnaksts (1 << 3) /** Global OUT NAK Status */
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#define DCTL_tstctl_bitp 4 /** Test Control */
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#define DCTL_tstctl_bits 0x7
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#define DCTL_sgnpinnak (1 << 7) /** Set Global Non-Periodic IN NAK */
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#define DCTL_cgnpinnak (1 << 8) /** Clear Global Non-Periodic IN NAK */
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#define DCTL_sgoutnak (1 << 9) /** Set Global OUT NAK */
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#define DCTL_cgoutnak (1 << 10) /** Clear Global OUT NAK */
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#define DCTL_pwronprgdone (1 << 11) /** Power on Program Done ? */
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/** Device Status Register */
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#define DSTS (*((uint32_t volatile*)(OTGBASE + 0x808)))
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#define DSTS_suspsts (1 << 0) /** Suspend status */
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#define DSTS_enumspd_bitp 1 /** Enumerated speed */
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#define DSTS_enumspd_bits 0x3
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#define DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ 0
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#define DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ 1
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#define DSTS_ENUMSPD_LS_PHY_6MHZ 2
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#define DSTS_ENUMSPD_FS_PHY_48MHZ 3
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#define DSTS_errticerr (1 << 3) /** Erratic errors ? */
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#define DSTS_soffn_bitp 8 /** Frame or Microframe Number of the received SOF */
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#define DSTS_soffn_bits 0x3fff
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/** Device IN Endpoint Common Interrupt Mask Register */
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#define DIEPMSK (*((uint32_t volatile*)(OTGBASE + 0x810)))
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/* the following apply to DEPMSK and DEPINT */
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#define DEPINT_xfercompl (1 << 0) /** Transfer complete */
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#define DEPINT_epdisabled (1 << 1) /** Endpoint disabled */
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#define DEPINT_ahberr (1 << 2) /** AHB error */
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#define DIEPINT_timeout (1 << 3) /** Timeout handshake (non-iso TX) */
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#define DOEPINT_setup (1 << 3) /** Setup Phase Done (control EPs)*/
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#define DIEPINT_intktxfemp (1 << 4) /** IN token received with tx fifo empty */
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#define DIEPINT_intknepmis (1 << 5) /** IN token received with ep mismatch */
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#define DIEPINT_inepnakeff (1 << 6) /** IN endpoint NAK effective */
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#define DIEPINT_emptyintr (1 << 7) /** linux doc broken on this, empty fifo ? */
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#define DIEPINT_txfifoundrn (1 << 8) /** linux doc void on this, tx fifo underrun ? */
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/** Device OUT Endpoint Common Interrupt Mask Register */
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#define DOEPMSK (*((uint32_t volatile*)(OTGBASE + 0x814)))
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/** Device All Endpoints Interrupt Register */
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#define DAINT (*((uint32_t volatile*)(OTGBASE + 0x818)))
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/* valid for DAINT and DAINTMSK, for 0<=ep<=15 */
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#define DAINT_IN_EP(i) (1 << (i))
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#define DAINT_OUT_EP(i) (1 << ((i) + 16))
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/** Device Endpoints Interrupt Mask Register */
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#define DAINTMSK (*((uint32_t volatile*)(OTGBASE + 0x81C)))
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/** Device IN Token Sequence Learning Queue Read Register 1 */
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#define DTKNQR1 (*((uint32_t volatile*)(OTGBASE + 0x820)))
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/** Device IN Token Sequence Learning Queue Register 2 */
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#define DTKNQR2 (*((uint32_t volatile*)(OTGBASE + 0x824)))
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/* fixme: those registers are not present in registers.h but are in dwc_otgh_regs.h.
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* the previous registers exists but has a different name :( */
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/** Device VBUS discharge register*/
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#define DVBUSDIS (*((uint32_t volatile*)(OTGBASE + 0x828)))
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/** Device VBUS pulse register */
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#define DVBUSPULSE (*((uint32_t volatile*)(OTGBASE + 0x82C)))
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// FIXME : 2 names for the same reg?
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/** Device IN Token Queue Read Register 3 (RO) */
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/** Device Thresholding control register */
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#define DTKNQR3 (*((uint32_t volatile*)(OTGBASE + 0x830)))
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#define DTHRCTL (*((uint32_t volatile*)(OTGBASE + 0x830)))
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#define DTHRCTL_non_iso_thr_en (1 << 0)
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#define DTHRCTL_iso_thr_en (1 << 1)
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#define DTHRCTL_tx_thr_len_bitp 2
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#define DTHRCTL_tx_thr_len_bits 0x1FF
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#define DTHRCTL_rx_thr_en (1 << 16)
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#define DTHRCTL_rx_thr_len_bitp 17
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#define DTHRCTL_rx_thr_len_bits 0x1FF
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/** Device IN Token Queue Read Register 4 (RO) */
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#define DTKNQR4 (*((uint32_t volatile*)(OTGBASE + 0x834)))
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/* Device Logical Endpoint-Specific Registers */
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#define DEPCTL(x, out) (*((uint32_t volatile*)(OTGBASE + 0x900 + ((!!out) * 0x200) + 0x20 * (x))))
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/** Maximum Packet Size
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* IN/OUT EPn
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* IN/OUT EP0 - 2 bits
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* 2'b00: 64 Bytes
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* 2'b01: 32
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* 2'b10: 16
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* 2'b11: 8 */
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#define DEPCTL_mps_bitp 0
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#define DEPCTL_mps_bits 0x7ff
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#define DEPCTL_MPS_64 0
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#define DEPCTL_MPS_32 1
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#define DEPCTL_MPS_16 2
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#define DEPCTL_MPS_8 3
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/** Next Endpoint
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* IN EPn/IN EP0
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* OUT EPn/OUT EP0 - reserved */
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#define DEPCTL_nextep_bitp 11
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#define DEPCTL_nextep_bits 0xf
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#define DEPCTL_usbactep (1 << 15) /** USB Active Endpoint */
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/** Endpoint DPID (INTR/Bulk IN and OUT endpoints)
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* This field contains the PID of the packet going to
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* be received or transmitted on this endpoint. The
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* application should program the PID of the first
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* packet going to be received or transmitted on this
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* endpoint , after the endpoint is
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* activated. Application use the SetD1PID and
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* SetD0PID fields of this register to program either
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* D0 or D1 PID.
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*
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* The encoding for this field is
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* - 0: D0
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* - 1: D1
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*/
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#define DEPCTL_dpid (1 << 16)
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#define DEPCTL_naksts (1 << 17) /** NAK Status */
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/** Endpoint Type
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* 2'b00: Control
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* 2'b01: Isochronous
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* 2'b10: Bulk
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* 2'b11: Interrupt */
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#define DEPCTL_eptype_bitp 18
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#define DEPCTL_eptype_bits 0x3
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/** Snoop Mode
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* OUT EPn/OUT EP0
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* IN EPn/IN EP0 - reserved */
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#define DEPCTL_snp (1 << 20)
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#define DEPCTL_stall (1 << 21) /** Stall Handshake */
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/** Tx Fifo Number
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* IN EPn/IN EP0
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* OUT EPn/OUT EP0 - reserved */
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#define DEPCTL_txfnum_bitp 22
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#define DEPCTL_txfnum_bits 0xf
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#define DEPCTL_cnak (1 << 26) /** Clear NAK */
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#define DEPCTL_snak (1 << 27) /** Set NAK */
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/** Set DATA0 PID (INTR/Bulk IN and OUT endpoints)
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* Writing to this field sets the Endpoint DPID (DPID)
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* field in this register to DATA0. Set Even
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* (micro)frame (SetEvenFr) (ISO IN and OUT Endpoints)
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* Writing to this field sets the Even/Odd
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* (micro)frame (EO_FrNum) field to even (micro)
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* frame.
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*/
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#define DEPCTL_setd0pid (1 << 28)
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/** Set DATA1 PID (INTR/Bulk IN and OUT endpoints)
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* Writing to this field sets the Endpoint DPID (DPID)
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* field in this register to DATA1 Set Odd
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* (micro)frame (SetOddFr) (ISO IN and OUT Endpoints)
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* Writing to this field sets the Even/Odd
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* (micro)frame (EO_FrNum) field to odd (micro) frame.
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*/
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#define DEPCTL_setd1pid (1 << 29)
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#define DEPCTL_epdis (1 << 30) /** Endpoint disable */
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#define DEPCTL_epena (1 << 31) /** Endpoint enable */
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/** Device Endpoint (ep) Transfer Size Register */
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#define DEPTSIZ(x, out) (*((uint32_t volatile*)(OTGBASE + 0x910 + (0x200 * (!!out)) + 0x20 * (x))))
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/* valid for any D{I,O}EPTSIZi with 1<=i<=15, NOT for i=0 ! */
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#define DEPTSIZ_xfersize_bitp 0 /** Transfer Size */
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#define DEPTSIZ_xfersize_bits 0x7ffff
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#define DEPTSIZ_pkcnt_bitp 19 /** Packet Count */
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#define DEPTSIZ_pkcnt_bits 0x3ff
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#define DEPTSIZ_mc_bitp 29 /** Multi Count - Periodic IN endpoints */
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#define DEPTSIZ_mc_bits 0x3
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/* idem but for i=0 */
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#define DEPTSIZ0_xfersize_bitp 0 /** Transfer Size */
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#define DEPTSIZ0_xfersize_bits 0x7f
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#define DEPTSIZ0_pkcnt_bitp 19 /** Packet Count */
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#define DEPTSIZ0_pkcnt_bits 0x3
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#define DEPTSIZ0_supcnt_bitp 29 /** Setup Packet Count (DOEPTSIZ0 Only) */
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#define DEPTSIZ0_supcnt_bits 0x3
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/** Device Endpoint (ep) Control Register */
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#define DEPINT(x,out) (*((uint32_t volatile*)(OTGBASE + 0x908 + (0x200 * (!!out)) + 0x20 * (x))))
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/** Device Endpoint (ep) DMA Address Register */
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#define DEPDMA(x,out) (*((const void* volatile*)(OTGBASE + 0x914 + (0x200 * (!!out)) + 0x20 * (x))))
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#if 0 /* Those are present in as3525v2, not s5l870x */
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/** Device IN Endpoint (ep) Transmit FIFO Status Register */
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#define DTXFSTS(ep) (*((const void* volatile*)(OTGBASE + 0x918 + 0x20 * (x))))
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/** Device OUT Endpoint (ep) Frame number Register */
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#define DOEPFN(ep) (*((const void* volatile*)(OTGBASE + 0xB04 + 0x20 * (x))))
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#endif
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/* Power and Clock Gating Register */
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#define PCGCCTL (*((uint32_t volatile*)(OTGBASE + 0xE00)))
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/** User HW Config1 Register */
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#define GHWCFG1 (*((uint32_t volatile*)(OTGBASE + 0x044)))
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#define GHWCFG1_epdir_bitp(ep) (2 * (ep))
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#define GHWCFG1_epdir_bits 0x3
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#define GHWCFG1_EPDIR_BIDIR 0
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#define GHWCFG1_EPDIR_IN 1
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#define GHWCFG1_EPDIR_OUT 2
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/** User HW Config2 Register */
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#define GHWCFG2 (*((uint32_t volatile*)(OTGBASE + 0x048)))
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#define GHWCFG2_arch_bitp 3 /** Architecture */
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#define GHWCFG2_arch_bits 0x3
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#define GHWCFG2_hs_phy_type_bitp 6 /** High speed PHY type */
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#define GHWCFG2_hs_phy_type_bits 0x3
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#define GHWCFG2_fs_phy_type_bitp 8 /** Full speed PHY type */
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#define GHWCFG2_fs_phy_type_bits 0x3
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#define GHWCFG2_num_ep_bitp 10 /** Number of endpoints */
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#define GHWCFG2_num_ep_bits 0xf
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#define GHWCFG2_dyn_fifo (1 << 19) /** Dynamic FIFO */
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/* For GHWCFG2_HS_PHY_TYPE and GHWCFG2_FS_PHY_TYPE */
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#define GHWCFG2_PHY_TYPE_UNSUPPORTED 0
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#define GHWCFG2_PHY_TYPE_UTMI 1
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#define GHWCFG2_ARCH_INTERNAL_DMA 2
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/** User HW Config3 Register */
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#define GHWCFG3 (*((uint32_t volatile*)(OTGBASE + 0x04C)))
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#define GHWCFG3_dfifo_len_bitp 16 /** Total fifo size */
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#define GHWCFG3_dfifo_len_bits 0xffff
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/** User HW Config4 Register */
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#define GHWCFG4 (*((uint32_t volatile*)(OTGBASE + 0x050)))
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#define GHWCFG4_utmi_phy_data_width_bitp 14 /** UTMI+ data bus width */
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#define GHWCFG4_utmi_phy_data_width_bits 0x3
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#define GHWCFG4_ded_fifo_en (1 << 25) /** Dedicated Tx FIFOs */
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#define GHWCFG4_num_in_ep_bitp 26 /** Number of IN endpoints */
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#define GHWCFG4_num_in_ep_bits 0xf
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#endif /* USB_S3C6400X_H */
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